add implicit rs detection for maddsubrs
[openpower-isa.git] / src / openpower / decoder / isa /
2023-04-27 Luke Kenneth Casso... link in new parallel-prefix REMAP schedule
2023-04-27 Jacob Lifshayadd scan/prefix-sum support to copy of parallel-reduce...
2023-04-27 Jacob Lifshayformat remap_preduce_yield.py
2023-04-25 Luke Kenneth Casso... check RC1, add data-dependent fail-first LD/ST test
2023-04-25 Jacob Lifshayreplace min/max[su][.] with minmax[.]
2023-04-18 Jacob Lifshayadd shaddw
2023-04-06 Luke Kenneth Casso... add power_decode_svp64_rm.py capability for new LD...
2023-04-04 Luke Kenneth Casso... comment about massive unnecessary code-duplication...
2023-04-04 Luke Kenneth Casso... fix setvl unit test which happened to use deprecated
2023-03-30 Jacob Lifshayfix add-like CA/OV outputs
2023-03-30 Jacob Lifshayadd addex to simulator
2023-03-30 Jacob Lifshayfix typo when getting pseudo-code output variables
2023-03-29 Luke Kenneth Casso... remove DCT/iDCT redundant modes which require less...
2023-03-25 Luke Kenneth Casso... updated simplev setvl specification pseudocode: MAJOR...
2023-03-25 Luke Kenneth Casso... whitespace
2023-03-20 Konstantinos Marga... Pass object code filename instead of actual data
2023-03-12 Luke Kenneth Casso... set MAXVL=VL=32 first, then set vertical-first separately
2023-03-12 Konstantinos Marga... used same input data as the actual C test
2023-03-12 Luke Kenneth Casso... change target registers in test_caller_svp64_chacha20...
2023-03-12 Luke Kenneth Casso... whoops use same temp reg for ctr
2023-03-12 Luke Kenneth Casso... parameterise svstep RT (set to 16 in chacha20 test)
2023-03-12 Luke Kenneth Casso... parameterising VL and SHAPE0-2 in chacha20 test
2023-03-12 Luke Kenneth Casso... parameterise the target block in chacha20 test,
2023-03-12 Luke Kenneth Casso... add print-out for chacha20 schedule
2023-01-15 Dmitry Selyutinpower_enums: clean code
2023-01-15 Dmitry Selyutinpower_insn: sort opcodes by sections
2023-01-01 Luke Kenneth Casso... correct name for Mem test function
2023-01-01 Luke Kenneth Casso... ascii dump on xchacha20 to compare against x86 version
2023-01-01 Luke Kenneth Casso... enable misaligned Mem in ISACaller by default
2022-12-30 Luke Kenneth Casso... corrections to boundary-wrapped store, and add misalign...
2022-12-30 Luke Kenneth Casso... add rollover mem test, store "rolls over" a 64-bit...
2022-12-30 Luke Kenneth Casso... add misaligned mem test
2022-12-30 Luke Kenneth Casso... add misaligned mem test
2022-12-30 Luke Kenneth Casso... add unit test for Mem class, need to add misaligned...
2022-12-29 Luke Kenneth Casso... print out memory exception details, on unaligned
2022-11-11 Jacob Lifshayadd maddedus
2022-10-29 Luke Kenneth Casso... add dsld. (Rc=1) test, make overflow acceptable to...
2022-10-27 Dmitry Selyutinisa/caller.py: support shadd/shadduw instructions
2022-10-24 Luke Kenneth Casso... add maxs. combined with cmp capability
2022-10-23 Luke Kenneth Casso... use svshape2 instead of svindex for the 4th shape
2022-10-22 Jacob Lifshayfix get_masked_reg and add test
2022-10-22 Jacob Lifshayformat code removing unused imports
2022-10-21 Luke Kenneth Casso... code-comments
2022-10-21 Luke Kenneth Casso... add 2nd outer loop, CTR 2 rounds, in chacha20 test
2022-10-21 Luke Kenneth Casso... move chacha20 to separate test, set/get masked regs...
2022-10-20 Luke Kenneth Casso... comments
2022-10-20 Luke Kenneth Casso... add first chacha20 round test
2022-10-19 Luke Kenneth Casso... TODO, sort out remap indices order
2022-10-18 Jacob Lifshayadd missing files to .gitignore
2022-10-16 Luke Kenneth Casso... debug print correction
2022-10-16 Luke Kenneth Casso... sigh, have to use yield from on get_out_map()
2022-10-16 Luke Kenneth Casso... rewrite get_idx_out2 in ISACaller to split out
2022-10-16 Luke Kenneth Casso... rewrite get_idx_out in ISACaller to split out
2022-10-16 Luke Kenneth Casso... add unit test showing two svindex calls, found bugs,
2022-10-16 Luke Kenneth Casso... code-shuffle, rework get_idx_in() to separate out the...
2022-10-14 Luke Kenneth Casso... add max-with-getting-index-of vertical-first loop example
2022-10-14 Luke Kenneth Casso... SVP64RMModeDecode detects Post-Inc LDST-imm mode
2022-10-14 Luke Kenneth Casso... correct comments
2022-10-14 Luke Kenneth Casso... add in zeroing on test strncpy
2022-10-14 Luke Kenneth Casso... remove unneeded svstate from test
2022-10-14 Luke Kenneth Casso... add strncpy example - 6 instructions
2022-10-14 Luke Kenneth Casso... add sv.stwu/pi example in test_sv_load_store_postinc
2022-10-14 Luke Kenneth Casso... add ld/st-immediate "post-inc" mode support. unit test...
2022-10-11 Luke Kenneth Casso... add asciidump option to Mem class
2022-10-11 Luke Kenneth Casso... whoops zero-error on masked-out
2022-10-10 Luke Kenneth Casso... add elwidth overrides on Indexed REMAP, 8-bit example...
2022-10-10 Luke Kenneth Casso... add elwidth overrides to get_idx_out2
2022-10-08 Luke Kenneth Casso... fix format in debug log
2022-10-08 Luke Kenneth Casso... forgot to add offset on GPR() get
2022-10-08 Luke Kenneth Casso... add elwidth overrides on destination (write) in ISACaller.
2022-10-08 Luke Kenneth Casso... split out base,offset in register decoding for elwidth...
2022-10-08 Luke Kenneth Casso... add 8-bit elwidth alu svp64 case
2022-10-07 Luke Kenneth Casso... more work on inssort. add useful reg-dump in ISACaller
2022-10-06 Luke Kenneth Casso... nope. failfirst needs to always save the result, but...
2022-10-06 Luke Kenneth Casso... fix fail-first to exclude failed element in VLi=0 mode
2022-10-06 Luke Kenneth Casso... sort out CROPs fail-first in ISACaller. needed to...
2022-10-06 Luke Kenneth Casso... make fail-first cope with sv.cmp which uses CR[BF]
2022-10-06 Luke Kenneth Casso... add insert sort svp64 test
2022-10-06 Luke Kenneth Casso... search for BF in registers to over-ride Vector lookup...
2022-10-06 Luke Kenneth Casso... starting to add sv.cmp support and failfirst, had to add
2022-10-02 Luke Kenneth Casso... comments for why preinc is called for svstep
2022-10-01 Luke Kenneth Casso... skip svstate_pre_inc on svremap
2022-10-01 Luke Kenneth Casso... no svstate instruction
2022-10-01 Luke Kenneth Casso... svstep calls SVSTATE_NEXT so needs svstate_pre_inc
2022-10-01 Luke Kenneth Casso... replacing setvl-svstep with just svstep
2022-10-01 Luke Kenneth Casso... replacing setvl-svstep with just svstep
2022-10-01 Luke Kenneth Casso... replacing setvl-svstep with just svstep
2022-10-01 Luke Kenneth Casso... comments
2022-10-01 Luke Kenneth Casso... comments
2022-10-01 Luke Kenneth Casso... minor cleanup in ISACaller on result handling
2022-10-01 Luke Kenneth Casso... simplify ISACaller execute_one
2022-10-01 Luke Kenneth Casso... simplify setting default SVSHAPE SPRs to zero
2022-09-30 Luke Kenneth Casso... ctr mode not needed, just use unconditional CTR dec
2022-09-30 Luke Kenneth Casso... set srcstep/dststep to zero in StepLoop (ISACaller...
2022-09-30 Luke Kenneth Casso... add sv.bc vlset-inverted test
2022-09-30 Luke Kenneth Casso... comments/variables-cleanup
2022-09-30 Luke Kenneth Casso... add sv.bc vlset-inverted test
2022-09-30 Luke Kenneth Casso... add sv.bc/vs - VLset - test. truncates VL at the vector...
2022-09-30 Luke Kenneth Casso... add new sv.bc CTR-loop test, subtracts VL from CTR
2022-09-30 Luke Kenneth Casso... whitespace
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