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sigh, check length of string returned, if non-zero add space
[openpower-isa.git]
/
src
/
openpower
/
decoder
/
power_insn.py
2022-09-18
Luke Kenneth Casso...
sigh, check length of string returned, if non-zero...
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2022-09-18
Luke Kenneth Casso...
sort out CR RM Mode (sz/dz bits moved, consistent)
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2022-09-18
Luke Kenneth Casso...
add comments (links to URLs) into power_insns.py for...
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2022-09-18
Luke Kenneth Casso...
remove f"" use simpler code, easier to read
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2022-09-18
Dmitry Selyutin
power_insn: fix Rc operand accessor
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2022-09-18
Dmitry Selyutin
power_insn: support RC1/~RC1 in ff/pr
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2022-09-18
Luke Kenneth Casso...
comment principle behind new tables in power_insn.py
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2022-09-18
Luke Kenneth Casso...
redo branch mode as a table, in power_insn.py
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2022-09-18
Dmitry Selyutin
power_insn: adjust table comments
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2022-09-18
Dmitry Selyutin
power_insn: another minor ld/st imm table cleanup
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2022-09-18
Dmitry Selyutin
power_insn: minor CR cleanup
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2022-09-18
Dmitry Selyutin
power_insn: minor cleanup
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2022-09-18
Luke Kenneth Casso...
code-morph CR ops to table in power_insn.py
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2022-09-18
Luke Kenneth Casso...
code-morph in power_insn.py - move table-search to...
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2022-09-18
Luke Kenneth Casso...
LDST_IDX Mode converted to table
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2022-09-18
Dmitry Selyutin
power_insn: support m/sm/dm specifiers
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2022-09-18
Dmitry Selyutin
power_insn: pass record to specifiers
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2022-09-18
Luke Kenneth Casso...
replace LDST_IMM mode with mask/value match table in...
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2022-09-18
Luke Kenneth Casso...
remove (invalid) NormalSaturationExtRM mode from power_...
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2022-09-18
Luke Kenneth Casso...
reduce NORMAL svp64 mode down to a mask-value search
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2022-09-18
Luke Kenneth Casso...
remove subvector mode from power_insn.py
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2022-09-18
Dmitry Selyutin
power_insn: support mrr specifier
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2022-09-18
Dmitry Selyutin
power_insn: support svm specifier
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2022-09-18
Dmitry Selyutin
power_insn: sync RM modes
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2022-09-18
Dmitry Selyutin
power_insn: support w/dw/sw specifiers
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2022-09-18
Dmitry Selyutin
power_insn: decouple branch modes
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2022-09-18
Dmitry Selyutin
power_insn: decouple cr_op modes
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2022-09-18
Dmitry Selyutin
power_insn: support sw specifier
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2022-09-18
Dmitry Selyutin
power_insn: decouple common normal and ld/st RM
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2022-09-18
Dmitry Selyutin
power_insn: support ew specifier
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2022-09-18
Dmitry Selyutin
power_insn: simplify subvl disassembly
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2022-09-17
Dmitry Selyutin
power_insn: fix sat checks
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2022-09-17
Dmitry Selyutin
power_fields: fix mapping class accessor
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2022-09-17
Dmitry Selyutin
power_insn: fix zz specifiers
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2022-09-17
Dmitry Selyutin
power_insn: decouple base ld/st idx RM
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2022-09-17
Dmitry Selyutin
power_insn: decouple base ld/st imm RM
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2022-09-17
Dmitry Selyutin
power_insn: decouple base normal RM
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2022-09-17
Dmitry Selyutin
power_insn: support saturation mode
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2022-09-17
Dmitry Selyutin
power_insn: support dz/sz specifiers
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2022-09-17
Luke Kenneth Casso...
add MASK_SRC to power_insn.py (SVmask_src from enums)
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2022-09-17
Luke Kenneth Casso...
remove pack/unpack modes from power_insn.py, they no...
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2022-09-17
Dmitry Selyutin
power_insn: support vec2/vec3/vec4
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2022-09-17
Dmitry Selyutin
power_insn: support specifiers
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2022-09-17
Dmitry Selyutin
power_insn: refactor and fix RM mappings
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2022-09-17
Dmitry Selyutin
power_insn: drop redundant table
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2022-09-16
Dmitry Selyutin
power_insn: postpone updating per-instruction operands
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2022-09-15
Dmitry Selyutin
power_insn: perform faster PPC database lookups
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2022-09-15
Dmitry Selyutin
power_insn: support instruction bytes conversion
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2022-09-15
Dmitry Selyutin
power_insn: allow accessing instruction bits
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2022-09-13
Dmitry Selyutin
power_insn: support signed operands
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2022-09-13
Dmitry Selyutin
power_insn: support branch RM
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2022-09-13
Dmitry Selyutin
power_insn: support CR RM
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2022-09-13
Dmitry Selyutin
power_insn: refactor RM mapping
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2022-09-12
Dmitry Selyutin
power_insn: refactor RM mapping
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2022-09-12
Dmitry Selyutin
power_insn: call sv_spec_leave unconditionally
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2022-09-12
Dmitry Selyutin
power_insn: fix RCOE check
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2022-09-12
Dmitry Selyutin
power_insn: introduce pseudo cr_in2
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2022-09-12
Dmitry Selyutin
power_insn: fix typo
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2022-09-12
Dmitry Selyutin
power_insn: support BRANCH and CR mode stubs
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2022-09-12
Dmitry Selyutin
power_insn: refactor register operands
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2022-09-11
Dmitry Selyutin
power_insn: check exact matches directly in set
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2022-09-11
Dmitry Selyutin
power_insn: group opcodes and names
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2022-09-11
Luke Kenneth Casso...
whoops lsbshf=2 for CR5
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2022-09-11
Luke Kenneth Casso...
whoops missed lsb-shift parameter
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2022-09-11
Luke Kenneth Casso...
add comments into CR5Operand class
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2022-09-11
Luke Kenneth Casso...
add CR5Operand and CR3Operand to power_insns.py
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2022-09-10
Dmitry Selyutin
power_insn: perform minor opcodes cleanup
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2022-09-10
Dmitry Selyutin
power_insn: hopefully final take on the opcodes
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2022-09-10
Dmitry Selyutin
power_insn: yet another take on the opcodes
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2022-09-10
Dmitry Selyutin
power_insn: refactor register verbose assembly
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2022-09-10
Dmitry Selyutin
power_insn: support pcode
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2022-09-10
Dmitry Selyutin
power_insn: tune TargetAddrOperand disassembly
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2022-09-10
Dmitry Selyutin
power_insn: support CR remap
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2022-09-10
Dmitry Selyutin
power_insn: support non-zero operands
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2022-09-10
Dmitry Selyutin
power_insn: simplify operand naming conventions
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2022-09-10
Dmitry Selyutin
power_insn: drop redundant dataclass incantations
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2022-09-10
Dmitry Selyutin
power_insn: do not print blob suffix unless needed
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2022-09-10
Dmitry Selyutin
power_insn: do not panic upon database query
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2022-09-10
Dmitry Selyutin
power_insn: refactor opcode matching
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2022-09-10
Dmitry Selyutin
power_insn: support D operand in DX form
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2022-09-10
Dmitry Selyutin
power_insn: refactor span detection
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2022-09-10
Dmitry Selyutin
power_insn: simplify code
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2022-09-10
Dmitry Selyutin
power_insn: remove redundant code
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2022-09-10
Dmitry Selyutin
power_insn: decouple extra merge routine
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2022-09-10
Dmitry Selyutin
power_insn: rename extra to spec
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2022-09-10
Dmitry Selyutin
power_insn: deprecate redundant else section
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2022-09-10
Dmitry Selyutin
power_insn: rename Extra classes
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2022-09-09
Dmitry Selyutin
power_insn: support verbosity levels
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2022-09-09
Dmitry Selyutin
power_insn: indent refactoring
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2022-09-09
Luke Kenneth Casso...
extend short down into rest of disassembly
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2022-09-09
Luke Kenneth Casso...
add "short" form of instruction - not output hex-encoding
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2022-09-07
Dmitry Selyutin
power_insn: dump operand type (scalar/vector)
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2022-09-07
Dmitry Selyutin
power_insn: fix immediate operands
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2022-09-07
Dmitry Selyutin
power_insn: refactor operands disassembly
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2022-09-07
Dmitry Selyutin
power_insn: support EXTRA2/EXTRA3 GPR/FPR
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2022-09-06
Dmitry Selyutin
power_insn: use tuple for bit ranges in fields
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2022-09-06
Dmitry Selyutin
power_insn: fix naming conventions
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2022-09-06
Dmitry Selyutin
power_insn: stricter reg type check
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2022-09-06
Dmitry Selyutin
power_insn: rename value argument to insn in operands
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2022-09-06
Dmitry Selyutin
power_insn: support branch stub
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