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add mm=1 svindex test, setting single targetted SVSHAPE
[openpower-isa.git]
/
src
/
openpower
/
decoder
/
power_regspec_map.py
2022-01-21
Luke Kenneth Casso...
add test for setting TB SPR, fix decode map for STATE...
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2022-01-19
Luke Kenneth Casso...
add spr-to-state conversion, and support for state1...
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2021-12-07
Jacob Lifshay
fix broken url
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2021-12-02
Luke Kenneth Casso...
regspec_decode_write now stores the decoded write info...
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2021-12-02
Luke Kenneth Casso...
specify length in RegDecodeInfo explicitly so that...
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2021-12-02
Luke Kenneth Casso...
use namedtuple for regspec_decode
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2021-12-02
Luke Kenneth Casso...
add module to regspec_decode_* and get_rdflags
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2021-12-01
Luke Kenneth Casso...
add regspec_decode which takes readmode arg and returns...
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2021-11-17
Luke Kenneth Casso...
XER regspec_decode_write was not sophisticated enough.
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2021-11-16
Luke Kenneth Casso...
truncate CR regspec_decode_write reg mask to 8 bit
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2021-11-16
Luke Kenneth Casso...
argh, regspec_decode_write is supposed to return single...
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2021-05-04
Luke Kenneth Casso...
whoops must include SVSTATE in STATE regfile regspec...
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2021-05-04
Luke Kenneth Casso...
add fast3 to PowerDecoder and regspec map
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2021-04-23
Luke Kenneth Casso...
rename soc use openpower consts regfile enums
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2021-04-23
Luke Kenneth Casso...
resolving imports changing over
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2021-04-23
Luke Kenneth Casso...
add first openpower decoder files, copied from soc...
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