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add mm=1 svindex test, setting single targetted SVSHAPE
[openpower-isa.git]
/
src
/
openpower
/
decoder
/
power_svp64_rm.py
2021-09-04
Luke Kenneth Casso...
redo SVP64 RM Decode to new CTR-Test Mode (svstep not...
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2021-08-11
Luke Kenneth Casso...
corrections to SVP64 Branch Conditional
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2021-08-10
Luke Kenneth Casso...
corrections to SVP64 Branch RM Mode decoding
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2021-08-08
Luke Kenneth Casso...
add SVP64 Branch-Conditional decoding
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2021-08-05
Luke Kenneth Casso...
start adding Branch-Conditional decoding to SVP64RMMode...
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2021-08-01
Luke Kenneth Casso...
bit of a big update, remove all bit-reversed LD operati...
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2021-06-23
Luke Kenneth Casso...
add start of bit-reverse mode for LD/ST to SVP64 encode...
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2021-06-19
Luke Kenneth Casso...
add mapreduce "reverse gear" unit tests
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2021-06-19
Luke Kenneth Casso...
add decode of "reverse gear" in SVP64 reduce mode
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2021-05-30
Luke Kenneth Casso...
add "normal" element-strided LD/ST decode/support to...
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2021-05-29
Luke Kenneth Casso...
comments
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2021-05-29
Luke Kenneth Casso...
extract LDST mode from SVP64 RM
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2021-05-29
Luke Kenneth Casso...
add SVP64 RM LDST mode enum
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2021-05-05
Luke Kenneth Casso...
add saturate SVP64 RM mode decode
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2021-05-05
Luke Kenneth Casso...
move SVP64 RM mode decoder into PowerDecodeSubset
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2021-05-05
Luke Kenneth Casso...
add sv_input_record_layout to match SVP64RMModeDecode
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2021-04-23
Luke Kenneth Casso...
resolving imports changing over
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2021-04-23
Luke Kenneth Casso...
add first openpower decoder files, copied from soc...
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