git.libre-soc.org Git - openpower-isa.git/history - src/openpower/decoder/test/

2021-12-26	Mikolaj Wielgus	Give human-readable names to slots, run functions and...	blob \| commitdiff \| raw
2021-12-23	Mikolaj Wielgus	Give unique names to CRTL-generated modules	blob \| commitdiff \| raw \| diff to current
2021-12-23	Mikolaj Wielgus	Move "pending" set to C	blob \| commitdiff \| raw \| diff to current
2021-12-22	Mikolaj Wielgus	Make _PySignalState CRTL-aware	blob \| commitdiff \| raw \| diff to current
2021-12-20	Mikolaj Wielgus	Generate variable declaration in some missing places	blob \| commitdiff \| raw \| diff to current
2021-12-20	Luke Kenneth Casso...	create header/footer for crtl code-generation	blob \| commitdiff \| raw \| diff to current
2021-12-17	Mikolaj Wielgus	Call the simulator-generated C using the CFFI	blob \| commitdiff \| raw \| diff to current
2021-12-08	Luke Kenneth Casso...	add an on_Display function which is being used by some...	blob \| commitdiff \| raw \| diff to current
2021-12-08	Luke Kenneth Casso...	found a way to print out the names of the signals	blob \| commitdiff \| raw \| diff to current
2021-12-08	Mikolaj Wielgus	WIP: Output C instead of Python for Nmigen simulation	blob \| commitdiff \| raw \| diff to current
2021-12-08	Mikolaj Wielgus	Source Nmigen simulator from this repository	blob \| commitdiff \| raw \| diff to current