git.libre-soc.org Git - openpower-isa.git/history - src/openpower/decoder/test/pysim.py

2022-08-25	Jacob Lifshay	allow crtl tests to run in parallel	blob \| commitdiff \| raw
2021-12-26	Mikolaj Wielgus	Give human-readable names to slots, run functions and...	blob \| commitdiff \| raw \| diff to current
2021-12-25	Mikolaj Wielgus	Put CRTL CFFI modules in crtl dir	blob \| commitdiff \| raw \| diff to current
2021-12-23	Luke Kenneth Casso...	code cleanup / comments	blob \| commitdiff \| raw \| diff to current
2021-12-23	Luke Kenneth Casso...	bit of a tidyup of crtl:	blob \| commitdiff \| raw \| diff to current
2021-12-23	Mikolaj Wielgus	Give unique names to CRTL-generated modules	blob \| commitdiff \| raw \| diff to current
2021-12-23	Mikolaj Wielgus	Move "pending" set to C	blob \| commitdiff \| raw \| diff to current
2021-12-22	Mikolaj Wielgus	Make _PySignalState CRTL-aware	blob \| commitdiff \| raw \| diff to current
2021-12-08	Luke Kenneth Casso...	absolute import again	blob \| commitdiff \| raw \| diff to current
2021-12-08	Mikolaj Wielgus	WIP: Output C instead of Python for Nmigen simulation	blob \| commitdiff \| raw \| diff to current
2021-12-08	Mikolaj Wielgus	Source Nmigen simulator from this repository	blob \| commitdiff \| raw \| diff to current