make truediv available to pseudocode
[openpower-isa.git] / src / openpower / decoder /
2023-05-12 Jacob Lifshaymake truediv available to pseudocode
2023-05-12 Jacob Lifshayadd bfp classification predicates
2023-05-12 Jacob Lifshayallow assigning BFPState and SelectableMSB0Fraction...
2023-05-12 Jacob Lifshayadd support for *_flag global variables needed by bfp_...
2023-05-12 Jacob Lifshaymake lexer replace class with class_ since it's a pytho...
2023-05-12 Jacob Lifshayfix SelectableMSB0Fraction's constructor
2023-05-12 Jacob LifshayRevert "add stub reset_xflags function"
2023-05-11 Luke Kenneth Casso... corrections to dd-ffirst tests when VLi=0, the write...
2023-05-11 Jacob LifshaySelectableMSB0Fraction is now basically complete and...
2023-05-10 Luke Kenneth Casso... add very very very basic write-out of instruction log
2023-05-10 Jacob LifshayMerge branch 'support-fields'
2023-05-10 Luke Kenneth Casso... add ld/st data-dependent fail-first /vli (inclusive)
2023-05-10 Luke Kenneth Casso... fix data-dependent fail-first on load
2023-05-10 Dmitry Selyutinpower_insn: remove redundant logs
2023-05-10 Luke Kenneth Casso... extend previous hard-coded magic constant (256) used...
2023-05-10 Jacob Lifshayadd WIP fp_working_format.py
2023-05-10 Jacob Lifshaychange FPSCR to a required parameter of ISACallerHelper support-fields
2023-05-10 Jacob LifshayRevert "remove now-unnecessary SO global, since XER...
2023-05-10 Jacob Lifshayswitch to using self.FPSCR
2023-05-10 Jacob Lifshayswitch to using FPSCRState for double2single.mdwn
2023-05-10 Jacob Lifshayadd self.FPSCR
2023-05-10 Jacob Lifshayremove now-unnecessary SO global, since XER[SO] syntax...
2023-05-10 Jacob Lifshaysupport FPSCR[RN] syntax that translates to FPSCR.RN
2023-05-10 Jacob Lifshayadd support for accessing XER using XER.SO syntax ...
2023-05-09 Luke Kenneth Casso... separate ISAPages out from inherited ISA Class
2023-05-09 Jacob LifshaySetFX is not a normal function -- it can assign to...
2023-05-09 Jacob Lifshayadd parser support for attributes like FPSCR.RN
2023-05-09 Jacob Lifshaymove apply_trailer into parser class
2023-05-09 Jacob Lifshaybypass ply's eating SyntaxErrors
2023-05-09 Jacob Lifshayfix some broken FieldSelectableInt handling
2023-05-07 Luke Kenneth Casso... comment TODO on Load-Fault in strncpy example
2023-05-07 Luke Kenneth Casso... add stub reset_xflags function
2023-05-06 Luke Kenneth Casso... add FPSCR to ISACaller
2023-05-06 Luke Kenneth Casso... add comment about why the new check has been added
2023-05-05 Jacob Lifshayadd initial fmv/fcvt tests, though they're broken due...
2023-05-05 Jacob Lifshayadd check that generated .py files are in .gitignore
2023-05-05 Jacob Lifshayverify fields.txt forms' field separators ('|') line...
2023-05-04 Konstantinos Marga... merge maddrs/msubrs, unit tests changed accordingly
2023-05-04 Konstantinos Marga... Add 2 more instructions to help with 2-coeff butterfly
2023-05-04 Konstantinos Marga... Turns out DCTI-Form is another variant of A-Form
2023-05-04 Konstantinos Marga... WIP: maddsubrs initial approach
2023-05-04 Jacob Lifshayadd fcvt/fmv -- no tests yet
2023-05-04 Jacob Lifshaysupport calling functions with no args in pseudocode
2023-05-04 Jacob Lifshayshow actual mdwn source location in backtrace when...
2023-05-04 Jacob Lifshaymove Assign to parser class in prep for improving synta...
2023-05-04 Jacob Lifshaycomment fmin*/fmax* since they're being replaced with...
2023-05-04 Jacob Lifshayfix non-zero assembly operands being zero
2023-04-30 Dmitry Selyutinpower_insn: forbid zero for non-zero operands
2023-04-30 Dmitry Selyutinpower_insn: drop registers remapping hack
2023-04-30 Dmitry Selyutinpower_insn: support int and index opcode methods
2023-04-28 Luke Kenneth Casso... reduce number of operands to ffmadds as well
2023-04-28 Jacob Lifshayprefix-sum remap works!
2023-04-28 Jacob Lifshaychange order to tuple in remap preduce tests/demos...
2023-04-28 Jacob Lifshayfix <u and >u with int arguments
2023-04-28 Luke Kenneth Casso... reduce fdmadds down to only 3 operands, RT-overwrite...
2023-04-27 Luke Kenneth Casso... add implicit rs detection for maddsubrs
2023-04-27 Luke Kenneth Casso... link in new parallel-prefix REMAP schedule
2023-04-27 Jacob Lifshayadd scan/prefix-sum support to copy of parallel-reduce...
2023-04-27 Jacob Lifshayformat remap_preduce_yield.py
2023-04-26 Dmitry Selyutinpower_insn: deprecate ff/pr common code nopr
2023-04-26 Dmitry Selyutinpower_insn: deprecate PR specifier
2023-04-26 Dmitry Selyutinpower_insn: deprecate normal PR mode
2023-04-26 Dmitry Selyutinpower_enums: sync forms
2023-04-25 Luke Kenneth Casso... check RC1, add data-dependent fail-first LD/ST test
2023-04-25 Jacob Lifshayreplace min/max[su][.] with minmax[.]
2023-04-25 Jacob Lifshayadd MM-form
2023-04-25 Jacob Lifshayfix bug where pseudo-code assignments modify more than...
2023-04-21 Jacob Lifshayrename/convert/merge XLCASTU/XLCASTS to EXTZXL/EXTSXL change-xlenification-bug-1064
2023-04-21 Jacob Lifshayadd EXTZ since it's in PowerISA v3.1B (see lbz for...
2023-04-20 Jacob Lifshayfix EXTSXL/XLCASTU/XLCASTS when inputs are python ints
2023-04-18 Jacob Lifshayadd shaddw
2023-04-06 Luke Kenneth Casso... add power_decode_svp64_rm.py capability for new LD...
2023-04-04 Luke Kenneth Casso... https://bugs.libre-soc.org/show_bug.cgi?id=1047
2023-04-04 Luke Kenneth Casso... whitespace cleanup (80 char per line hard limit)
2023-04-04 Luke Kenneth Casso... comment about massive unnecessary code-duplication...
2023-04-04 Luke Kenneth Casso... fix setvl unit test which happened to use deprecated
2023-03-30 Jacob Lifshayfix add-like CA/OV outputs
2023-03-30 Jacob Lifshayadd addex to simulator
2023-03-30 Jacob Lifshayfix typo when getting pseudo-code output variables
2023-03-29 Luke Kenneth Casso... remove DCT/iDCT redundant modes which require less...
2023-03-25 Luke Kenneth Casso... updated simplev setvl specification pseudocode: MAJOR...
2023-03-25 Luke Kenneth Casso... whitespace
2023-03-24 Luke Kenneth Casso... whoops added "CRB-Form" format not "CRB"
2023-03-20 Konstantinos Marga... Pass object code filename instead of actual data
2023-03-12 Luke Kenneth Casso... set MAXVL=VL=32 first, then set vertical-first separately
2023-03-12 Konstantinos Marga... used same input data as the actual C test
2023-03-12 Luke Kenneth Casso... change target registers in test_caller_svp64_chacha20...
2023-03-12 Luke Kenneth Casso... whoops use same temp reg for ctr
2023-03-12 Luke Kenneth Casso... parameterise svstep RT (set to 16 in chacha20 test)
2023-03-12 Luke Kenneth Casso... parameterising VL and SHAPE0-2 in chacha20 test
2023-03-12 Luke Kenneth Casso... parameterise the target block in chacha20 test,
2023-03-12 Luke Kenneth Casso... add print-out for chacha20 schedule
2023-01-24 Dmitry Selyutinpower_enums: enable Rc-aware dsld/dsrd
2023-01-23 Dmitry Selyutinpower_insn: fix dst/src duplication detection
2023-01-22 Dmitry Selyutinpower_insn: canonicalize SVP64 insn name
2023-01-21 Dmitry Selyutinpower_insn: hack CR assembly
2023-01-20 Dmitry Selyutinpower_insn: override bogus FMA instructions
2023-01-20 Dmitry Selyutinpower_insn: refactor operands; simplify lookups
2023-01-19 Dmitry Selyutinpower_insn: fix paired registers disassembly
2023-01-18 Dmitry Selyutinpower_insn: support legacy style
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