test python_divmod_algorithm
[openpower-isa.git] / src / openpower / decoder /
2023-12-22 Jacob Lifshaytest python_divmod_algorithm
2023-12-22 Jacob Lifshaylog asmop to LogKind.InstrInOuts too since only printin...
2023-12-22 Jacob Lifshayworking on adding divmod 512x256 to 256x256
2023-12-22 Jacob Lifshaylog writing CA[32]/OV[32] for OP_ADD
2023-12-22 Jacob Lifshayfix concat when the first argument is a FieldSelectableInt
2023-12-22 Jacob Lifshayadd MemMMap tests
2023-12-22 Jacob Lifshayskip zero words when iterating words in MemMMap
2023-12-22 Jacob Lifshayformat src/openpower/decoder/isa/test_mem.py
2023-12-22 Luke Kenneth Casso... add basis of Context Manager for capturing which inputs...
2023-12-22 Luke Kenneth Casso... minor alteration of reporting hash in mini-test of...
2023-12-22 Luke Kenneth Casso... detect if add arg2 is greater than 7 and ignore it...
2023-12-22 Luke Kenneth Casso... add an intercept (on all poly1305-donna.py math primitives)
2023-12-22 Luke Kenneth Casso... add link to poly1305-design (really good)
2023-12-22 Luke Kenneth Casso... allow intercept on dsrd (rename DSRD) in poly13005...
2023-12-22 Luke Kenneth Casso... provide intercepts of 64/128-bit math primitives that...
2023-12-22 Luke Kenneth Casso... convert all use of "+" to ADD(a,b) in order to prepare...
2023-12-22 Jacob Lifshayswitch UTF-8 validation tests to use MemMMap so it...
2023-12-22 Jacob Lifshayadd MemMMap class
2023-12-22 Jacob Lifshaysplit out most Mem methods into MemCommon base class
2023-12-22 Jacob Lifshayformat mem.py
2023-12-22 Jacob Lifshaymake scalar EXTRA2 encoding match between tables and...
2023-12-22 Jacob Lifshayformat code
2023-12-22 Jacob LifshayRevert "fix PowerDecoder2 to properly decode scalar...
2023-12-22 Jacob Lifshayfix bug I noticed while reading git history
2023-12-22 Luke Kenneth Casso... add python-based implementation of dsrd to poly1305...
2023-12-22 Luke Kenneth Casso... illustrate the intermediary step of converting poly1305...
2023-12-22 Luke Kenneth Casso... first revision port of https://github.com/floodyberry...
2023-12-22 Luke Kenneth Casso... make the poly1305 quick example identical to the poly13...
2023-12-22 Luke Kenneth Casso... add a quick usage demo to poly1305.py, to serve later...
2023-12-22 Luke Kenneth Casso... add implementation of poly1305 pure python
2023-12-22 Luke Kenneth Casso... add code-comments to chacha20 svp64 unit test
2023-12-22 Luke Kenneth Casso... add links copyright and funding notice to svp64 chacha2...
2023-12-22 Jacob Lifshayfix PowerDecoder2 to properly decode scalar EXTRA2
2023-12-22 Jacob Lifshayadd tests for checking if the simulator and assembler...
2023-12-22 Jacob Lifshaylog more register read/writes to LogKind.InstrInOuts
2023-12-22 Jacob Lifshayadd copyright stuff
2023-12-22 Jacob Lifshayadd SVP64 256x256->512-bit multiply
2023-12-22 Andrey MiroshnikovAdding syscall ISACaller test case (not working yet).
2023-12-22 Jacob Lifshayremove grev, leaving unit tests for later use by grevlut
2023-12-22 Jacob Lifshaymake soc test_pipe_caller tests pass again
2023-12-22 Jacob Lifshaydon't warn for directories
2023-12-22 Jacob Lifshayignore indented comments too
2023-12-22 Jacob Lifshayadd support for pseudocode being a [[!inline]] directive
2023-12-22 Jacob Lifshayput reason for checking for old files in error msg
2023-12-22 Jacob Lifshaymove generated files to .../decoder/isa/generated
2023-12-22 Jacob Lifshaydon't convert CR[BI] to CR.BI
2023-12-22 Jacob Lifshayadd set[n]bc[r] -- tests broken
2023-12-22 Jacob Lifshayadd missing test_caller_cr.py
2023-12-22 Jacob Lifshayadd support for C conditional operator
2023-12-22 Jacob Lifshayadd pdepd/pextd
2023-12-22 Jacob Lifshayadd cfuged
2023-12-22 Jacob Lifshayadd cntlzdm/cnttzdm
2023-12-22 Konstantinos Marga... Moved maddsubrs/maddrs/msubrs instructions to separate...
2023-12-22 Jacob Lifshayadd byte reverse instructions from PowerISA v3.1B
2023-12-22 Jacob Lifshayadd fminmax tests with corresponding pseudocode fixes
2023-12-22 Jacob Lifshayupdate to use new fminmax instruction
2023-12-22 Luke Kenneth Casso... leeetle bit excessive on the log of SPRs...
2023-12-22 Dmitry Selyutinpower_enum: modify SVPtype stringification
2023-12-22 Jacob Lifshayrename fmv[ft]g*/fcvt[ft]g* to m[tf]fpr*/c[tf]fpr*
2023-12-22 Jacob Lifshayuse the CSV "CR out" column to compute which mode to...
2023-12-22 Jacob Lifshaycache get_csv
2023-12-22 Jacob Lifshaycomment out GC collection since it's really slow and...
2023-12-22 Jacob Lifshaycache SVP64Instruction.Prefix instance since it's slow...
2023-12-22 Jacob Lifshayremove fcvttgs since it's redundant
2023-12-22 Jacob Lifshaysilence log by default just in fmv/fcvt and utf-8 tests
2023-12-22 Jacob LifshayRevert "disable fmv-fcvt tests entirely"
2023-12-22 Jacob LifshayRevert "far too much memory (58 GB) being used by these...
2023-12-22 Luke Kenneth Casso... comment out debug log
2023-12-22 Luke Kenneth Casso... remove print log
2023-12-22 Dmitry Selyutinpower_enums: distinguish all reg types
2023-12-22 Dmitry Selyutinpower_enums: simplify sel type string conversion
2023-12-22 Dmitry Selyutinpower_enums: simplify extra idx string conversion
2023-12-22 Dmitry Selyutinpower_enums: align reg pairs
2023-12-22 Dmitry Selyutinpower_enums: simplify reg string conversion
2023-12-22 Dmitry Selyutinpower_enums: simplify selectors string conversion
2023-12-22 Luke Kenneth Casso... rename "none" __repr__ to "NONE" in SVExtra and SelType
2023-12-22 Dmitry Selyutininsndb: rename types into core
2023-12-22 Dmitry Selyutininsndb: revert recent renaming
2023-12-22 Luke Kenneth Casso... using names of modules that are identical to commonly...
2023-12-22 Dmitry Selyutinpysvp64asm: integrate into insndb
2023-12-22 Dmitry Selyutinpower_insn: decouple into separate module
2023-06-02 Dmitry Selyutinpower_insn: disassemble RA0 and RT0 correctly
2023-06-02 Dmitry Selyutinpower_insn: forbid r0 for RA0 and RT0
2023-06-02 Dmitry Selyutinpower_enums: introduce Reg pair property
2023-06-02 Dmitry Selyutinpower_enums: introduce Reg or_zero property
2023-06-02 Dmitry Selyutinpower_insn: drop unused import
2023-06-02 Dmitry Selyutinpower_enums: deprecate SVExtraReg
2023-06-02 Dmitry Selyutinpower_insn: switch to Reg
2023-06-02 Dmitry Selyutinpower_enums: introduce Reg as alias of SVExtraReg
2023-06-02 Dmitry Selyutinpower_insn: guess extra from reg instead of sel
2023-06-02 Dmitry Selyutinpower_enums: provide selector type property
2023-06-02 Dmitry Selyutinpower_enums: deprecate SVExtraRegType
2023-06-02 Dmitry Selyutinpower_insn: switch to SelType
2023-06-02 Dmitry Selyutinpower_enums: introduce SelType as alias of SVExtraRegType
2023-06-02 Dmitry Selyutinpower_insn: completely refactor extras
2023-06-02 Dmitry Selyutinpower_enums: introduce register aliases
2023-06-02 Dmitry Selyutinpower_insn: introduce extras property
2023-06-02 Dmitry Selyutinpower_enums: change SVExtra representation
2023-06-02 Luke Kenneth Casso... far too much memory (58 GB) being used by these unit...
2023-06-02 Luke Kenneth Casso... disable fmv-fcvt tests entirely
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