rename absadd[us] to absdac[ud]
[openpower-isa.git] / src / openpower / decoder /
2022-06-20 Luke Kenneth Casso... rename absadd[us] to absdac[ud]
2022-06-19 Jacob Lifshayupdate after adding av instructions
2022-06-19 Luke Kenneth Casso... add absadd (unsigned) DRAFT
2022-06-19 Luke Kenneth Casso... add absolute-difference DRAFT
2022-06-19 Luke Kenneth Casso... add average-add DRAFT pseudocode and CSV
2022-06-19 Luke Kenneth Casso... add maxs DRAFT instruction
2022-06-19 Luke Kenneth Casso... extend minor_22.csv bitsel pattern to cover bits 21..31
2022-06-17 Luke Kenneth Casso... whoops on an OR rather than an AND
2022-06-17 Luke Kenneth Casso... add "redirection" of MTSPR/MFSPR into TRAP pipeline...
2022-06-17 Luke Kenneth Casso... add KAIVB SPR 850
2022-05-20 Luke Kenneth Casso... bit of a mess being sorted out
2022-05-19 Dmitry Selyutintemporarily revert opcode changes
2022-05-19 Dmitry Selyutinpower_decoder: reflect a new XO bit
2022-05-03 Luke Kenneth Casso... properly fix pagereader.py to parse markdown with inden...
2022-05-03 Luke Kenneth Casso... allow HTML comments to start with whitespace
2022-05-03 Jacob Lifshayadd Rc to ternlogi
2022-05-03 Jacob Lifshayformat code
2022-05-03 Jacob Lifshayadd svfixedarith.py to .gitignore
2022-04-25 Dmitry Selyutinselectable_int: remove debug prints
2022-04-20 Dmitry Selyutinselectable_int: derive SelectableIntMapping on per...
2022-04-20 Dmitry Selyutinisa.caller: support default SVP64PrefixFields initializ...
2022-04-19 Dmitry Selyutinselectable_int: simplify SelectableIntMapping class
2022-04-19 Dmitry Selyutinisa.caller: support whole integer pseudo-field
2022-04-19 Dmitry Selyutinisa.caller: refactor SVP64PrefixFields class
2022-04-19 Dmitry Selyutinisa.caller: refactor SVP64RMFields class
2022-04-19 Dmitry Selyutinselectable_int: introduce SelectableIntMapping class
2022-04-19 Dmitry Selyutinselectable_int: make FieldSelectableInt.__repr__ more...
2022-04-19 Dmitry Selyutinselectable_int: make SelectableInt.__repr__ more flexible
2022-04-19 Dmitry Selyutinselectable_int: allow range in FieldSelectableInt
2022-04-08 Jacob Lifshayadd SPDX-License-Identifier rather than License:
2022-04-08 Jacob Lifshayformat code
2022-04-07 Luke Kenneth Casso... whitespace (80 char limit)
2022-04-07 Luke Kenneth Casso... comment 64-bit of predicate (all 1s)
2022-03-26 Luke Kenneth Casso... Revert "add python generator version of tree reduction"
2022-03-25 Jacob Lifshayadd python generator version of tree reduction
2022-01-24 Luke Kenneth Casso... remove read of SRR1 for TRAP pipeline, pass via LDSTExc...
2022-01-21 Luke Kenneth Casso... add test for setting TB SPR, fix decode map for STATE...
2022-01-19 Luke Kenneth Casso... trap types memory exception (TT.MEMEXC) instead of...
2022-01-19 Luke Kenneth Casso... add spr-to-state conversion, and support for state1...
2022-01-18 Luke Kenneth Casso... see soc/fu/trap/main_stage.py trap() function, and:
2022-01-18 Jacob Lifshaygrev[w][i][.] pseudo-code works
2022-01-18 Jacob Lifshayadd log2 pseudo-code helper
2022-01-18 Jacob Lifshayformat code
2022-01-18 Jacob Lifshayadd test_caller_logical.py
2022-01-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-soc.org:922...
2022-01-18 Jacob Lifshayspeed up pywriter
2022-01-17 Jacob LifshayWIP speed up pywriter by caching stuff more and not...
2022-01-15 Luke Kenneth Casso... correctly identify atomic reservation CSV file field and
2022-01-15 Luke Kenneth Casso... add atomic reservation field to Power Decoder data...
2022-01-10 Luke Kenneth Casso... enable privileged-instruction detection which had previ...
2022-01-06 Jacob Lifshayadd grev[w][i] instructions
2022-01-06 Jacob Lifshayformat code
2022-01-06 Jacob Lifshayadd stand-alone simulator bitmanip test
2022-01-06 Luke Kenneth Casso... add tlbsync and wait as NOPs
2022-01-05 Luke Kenneth Casso... add eieio instruction as a NOP to minor 31 csv
2022-01-05 Luke Kenneth Casso... add lbzcix instruction which had been completely forgot...
2022-01-03 Luke Kenneth Casso... copy over msr and rename cia to nia in PowerDecoder2
2021-12-27 Luke Kenneth Casso... whoops wrong parameter name
2021-12-27 Luke Kenneth Casso... quick attempt to fix test_decoder_gas.py (did not work)
2021-12-27 Mikolaj Wielgusbool() is !!() for integers
2021-12-27 Mikolaj WielgusAdd missing parentheses for explicit operator precedence
2021-12-26 Luke Kenneth Casso... add very basic PowerDecode2 test which at least gets...
2021-12-26 Luke Kenneth Casso... a few extra things discovered needing c syntax not...
2021-12-26 Mikolaj WielgusGive human-readable names to slots, run functions and...
2021-12-25 Mikolaj WielgusPut CRTL CFFI modules in crtl dir
2021-12-23 Luke Kenneth Casso... code cleanup / comments
2021-12-23 Luke Kenneth Casso... repeat power decode test to check performance
2021-12-23 Luke Kenneth Casso... bit of a tidyup of crtl:
2021-12-23 Mikolaj WielgusAdd CRTL templates
2021-12-23 Mikolaj WielgusGive unique names to CRTL-generated modules
2021-12-23 Mikolaj WielgusMove "pending" set to C
2021-12-22 Mikolaj WielgusMake _PySignalState CRTL-aware
2021-12-21 Luke Kenneth Casso... take a copy of the wb_get memory and then for each...
2021-12-21 Luke Kenneth Casso... ISACaller (actually RADIXMMU) only do virtual memory...
2021-12-20 Mikolaj WielgusGenerate variable declaration in some missing places
2021-12-20 Luke Kenneth Casso... create header/footer for crtl code-generation
2021-12-20 Luke Kenneth Casso... whoops forgot to trap if non-execute (instruction)...
2021-12-19 Luke Kenneth Casso... TODO notes for executing ISACaller Invalid Instruction...
2021-12-19 Luke Kenneth Casso... pass the mode (LOAD,EXECUTE,STORE) through ISACaller...
2021-12-17 Mikolaj WielgusCall the simulator-generated C using the CFFI
2021-12-13 Tobias Platenadd namedtuple MSRSpec
2021-12-12 Luke Kenneth Casso... copy over fake OP_FETCH_FAILED and instruction on...
2021-12-10 Jacob Lifshaychange ternlogi to not have Rc field
2021-12-09 Luke Kenneth Casso... add FAST SPRs temporarily to power_enums
2021-12-09 Jacob Lifshaymake ternlogi tests run
2021-12-09 Jacob Lifshayadd initial ternlogi pseudo-code
2021-12-08 Luke Kenneth Casso... add instr_fault to PowerDecoder2
2021-12-08 Luke Kenneth Casso... whitespace
2021-12-08 Luke Kenneth Casso... code-comments for LDSTException.instr_fault
2021-12-08 Luke Kenneth Casso... add an on_Display function which is being used by some...
2021-12-08 Luke Kenneth Casso... found a way to print out the names of the signals
2021-12-08 Luke Kenneth Casso... absolute import again
2021-12-08 Luke Kenneth Casso... use full-path imports (so we know where they come from)
2021-12-08 Mikolaj WielgusWIP: Output C instead of Python for Nmigen simulation
2021-12-08 Mikolaj WielgusSource Nmigen simulator from this repository
2021-12-07 Luke Kenneth Casso... whoops wrong number
2021-12-07 Luke Kenneth Casso... add OP_FETCH_FAILED micro-op
2021-12-07 Jacob Lifshayfix broken url
2021-12-04 Luke Kenneth Casso... raise a MemException in ISACaller RADIXMMU
2021-12-02 Luke Kenneth Casso... regspec_decode_write now stores the decoded write info...
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