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rename absadd[us] to absdac[ud]
[openpower-isa.git]
/
src
/
openpower
/
decoder
/
2022-06-20
Luke Kenneth Casso...
rename absadd[us] to absdac[ud]
tree
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commitdiff
2022-06-19
Jacob Lifshay
update after adding av instructions
tree
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commitdiff
2022-06-19
Luke Kenneth Casso...
add absadd (unsigned) DRAFT
tree
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commitdiff
2022-06-19
Luke Kenneth Casso...
add absolute-difference DRAFT
tree
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commitdiff
2022-06-19
Luke Kenneth Casso...
add average-add DRAFT pseudocode and CSV
tree
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commitdiff
2022-06-19
Luke Kenneth Casso...
add maxs DRAFT instruction
tree
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commitdiff
2022-06-19
Luke Kenneth Casso...
extend minor_22.csv bitsel pattern to cover bits 21..31
tree
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commitdiff
2022-06-17
Luke Kenneth Casso...
whoops on an OR rather than an AND
tree
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commitdiff
2022-06-17
Luke Kenneth Casso...
add "redirection" of MTSPR/MFSPR into TRAP pipeline...
tree
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commitdiff
2022-06-17
Luke Kenneth Casso...
add KAIVB SPR 850
tree
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commitdiff
2022-05-20
Luke Kenneth Casso...
bit of a mess being sorted out
tree
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commitdiff
2022-05-19
Dmitry Selyutin
temporarily revert opcode changes
tree
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commitdiff
2022-05-19
Dmitry Selyutin
power_decoder: reflect a new XO bit
tree
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commitdiff
2022-05-03
Luke Kenneth Casso...
properly fix pagereader.py to parse markdown with inden...
tree
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commitdiff
2022-05-03
Luke Kenneth Casso...
allow HTML comments to start with whitespace
tree
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commitdiff
2022-05-03
Jacob Lifshay
add Rc to ternlogi
tree
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commitdiff
2022-05-03
Jacob Lifshay
format code
tree
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commitdiff
2022-05-03
Jacob Lifshay
add svfixedarith.py to .gitignore
tree
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commitdiff
2022-04-25
Dmitry Selyutin
selectable_int: remove debug prints
tree
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commitdiff
2022-04-20
Dmitry Selyutin
selectable_int: derive SelectableIntMapping on per...
tree
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commitdiff
2022-04-20
Dmitry Selyutin
isa.caller: support default SVP64PrefixFields initializ...
tree
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commitdiff
2022-04-19
Dmitry Selyutin
selectable_int: simplify SelectableIntMapping class
tree
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commitdiff
2022-04-19
Dmitry Selyutin
isa.caller: support whole integer pseudo-field
tree
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commitdiff
2022-04-19
Dmitry Selyutin
isa.caller: refactor SVP64PrefixFields class
tree
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commitdiff
2022-04-19
Dmitry Selyutin
isa.caller: refactor SVP64RMFields class
tree
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commitdiff
2022-04-19
Dmitry Selyutin
selectable_int: introduce SelectableIntMapping class
tree
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commitdiff
2022-04-19
Dmitry Selyutin
selectable_int: make FieldSelectableInt.__repr__ more...
tree
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commitdiff
2022-04-19
Dmitry Selyutin
selectable_int: make SelectableInt.__repr__ more flexible
tree
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commitdiff
2022-04-19
Dmitry Selyutin
selectable_int: allow range in FieldSelectableInt
tree
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commitdiff
2022-04-08
Jacob Lifshay
add SPDX-License-Identifier rather than License:
tree
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commitdiff
2022-04-08
Jacob Lifshay
format code
tree
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commitdiff
2022-04-07
Luke Kenneth Casso...
whitespace (80 char limit)
tree
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commitdiff
2022-04-07
Luke Kenneth Casso...
comment 64-bit of predicate (all 1s)
tree
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commitdiff
2022-03-26
Luke Kenneth Casso...
Revert "add python generator version of tree reduction"
tree
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commitdiff
2022-03-25
Jacob Lifshay
add python generator version of tree reduction
tree
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commitdiff
2022-01-24
Luke Kenneth Casso...
remove read of SRR1 for TRAP pipeline, pass via LDSTExc...
tree
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commitdiff
2022-01-21
Luke Kenneth Casso...
add test for setting TB SPR, fix decode map for STATE...
tree
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commitdiff
2022-01-19
Luke Kenneth Casso...
trap types memory exception (TT.MEMEXC) instead of...
tree
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commitdiff
2022-01-19
Luke Kenneth Casso...
add spr-to-state conversion, and support for state1...
tree
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commitdiff
2022-01-18
Luke Kenneth Casso...
see soc/fu/trap/main_stage.py trap() function, and:
tree
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commitdiff
2022-01-18
Jacob Lifshay
grev[w][i][.] pseudo-code works
tree
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commitdiff
2022-01-18
Jacob Lifshay
add log2 pseudo-code helper
tree
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commitdiff
2022-01-18
Jacob Lifshay
format code
tree
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commitdiff
2022-01-18
Jacob Lifshay
add test_caller_logical.py
tree
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commitdiff
2022-01-18
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-soc.org:922...
tree
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commitdiff
2022-01-18
Jacob Lifshay
speed up pywriter
tree
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commitdiff
2022-01-17
Jacob Lifshay
WIP speed up pywriter by caching stuff more and not...
tree
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commitdiff
2022-01-15
Luke Kenneth Casso...
correctly identify atomic reservation CSV file field and
tree
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commitdiff
2022-01-15
Luke Kenneth Casso...
add atomic reservation field to Power Decoder data...
tree
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commitdiff
2022-01-10
Luke Kenneth Casso...
enable privileged-instruction detection which had previ...
tree
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commitdiff
2022-01-06
Jacob Lifshay
add grev[w][i] instructions
tree
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commitdiff
2022-01-06
Jacob Lifshay
format code
tree
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commitdiff
2022-01-06
Jacob Lifshay
add stand-alone simulator bitmanip test
tree
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commitdiff
2022-01-06
Luke Kenneth Casso...
add tlbsync and wait as NOPs
tree
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commitdiff
2022-01-05
Luke Kenneth Casso...
add eieio instruction as a NOP to minor 31 csv
tree
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commitdiff
2022-01-05
Luke Kenneth Casso...
add lbzcix instruction which had been completely forgot...
tree
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commitdiff
2022-01-03
Luke Kenneth Casso...
copy over msr and rename cia to nia in PowerDecoder2
tree
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commitdiff
2021-12-27
Luke Kenneth Casso...
whoops wrong parameter name
tree
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commitdiff
2021-12-27
Luke Kenneth Casso...
quick attempt to fix test_decoder_gas.py (did not work)
tree
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commitdiff
2021-12-27
Mikolaj Wielgus
bool() is !!() for integers
tree
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commitdiff
2021-12-27
Mikolaj Wielgus
Add missing parentheses for explicit operator precedence
tree
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commitdiff
2021-12-26
Luke Kenneth Casso...
add very basic PowerDecode2 test which at least gets...
tree
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commitdiff
2021-12-26
Luke Kenneth Casso...
a few extra things discovered needing c syntax not...
tree
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commitdiff
2021-12-26
Mikolaj Wielgus
Give human-readable names to slots, run functions and...
tree
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commitdiff
2021-12-25
Mikolaj Wielgus
Put CRTL CFFI modules in crtl dir
tree
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commitdiff
2021-12-23
Luke Kenneth Casso...
code cleanup / comments
tree
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commitdiff
2021-12-23
Luke Kenneth Casso...
repeat power decode test to check performance
tree
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commitdiff
2021-12-23
Luke Kenneth Casso...
bit of a tidyup of crtl:
tree
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commitdiff
2021-12-23
Mikolaj Wielgus
Add CRTL templates
tree
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commitdiff
2021-12-23
Mikolaj Wielgus
Give unique names to CRTL-generated modules
tree
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commitdiff
2021-12-23
Mikolaj Wielgus
Move "pending" set to C
tree
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commitdiff
2021-12-22
Mikolaj Wielgus
Make _PySignalState CRTL-aware
tree
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commitdiff
2021-12-21
Luke Kenneth Casso...
take a copy of the wb_get memory and then for each...
tree
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commitdiff
2021-12-21
Luke Kenneth Casso...
ISACaller (actually RADIXMMU) only do virtual memory...
tree
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commitdiff
2021-12-20
Mikolaj Wielgus
Generate variable declaration in some missing places
tree
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commitdiff
2021-12-20
Luke Kenneth Casso...
create header/footer for crtl code-generation
tree
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commitdiff
2021-12-20
Luke Kenneth Casso...
whoops forgot to trap if non-execute (instruction)...
tree
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commitdiff
2021-12-19
Luke Kenneth Casso...
TODO notes for executing ISACaller Invalid Instruction...
tree
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commitdiff
2021-12-19
Luke Kenneth Casso...
pass the mode (LOAD,EXECUTE,STORE) through ISACaller...
tree
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commitdiff
2021-12-17
Mikolaj Wielgus
Call the simulator-generated C using the CFFI
tree
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commitdiff
2021-12-13
Tobias Platen
add namedtuple MSRSpec
tree
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commitdiff
2021-12-12
Luke Kenneth Casso...
copy over fake OP_FETCH_FAILED and instruction on...
tree
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commitdiff
2021-12-10
Jacob Lifshay
change ternlogi to not have Rc field
tree
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commitdiff
2021-12-09
Luke Kenneth Casso...
add FAST SPRs temporarily to power_enums
tree
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commitdiff
2021-12-09
Jacob Lifshay
make ternlogi tests run
tree
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commitdiff
2021-12-09
Jacob Lifshay
add initial ternlogi pseudo-code
tree
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commitdiff
2021-12-08
Luke Kenneth Casso...
add instr_fault to PowerDecoder2
tree
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commitdiff
2021-12-08
Luke Kenneth Casso...
whitespace
tree
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commitdiff
2021-12-08
Luke Kenneth Casso...
code-comments for LDSTException.instr_fault
tree
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commitdiff
2021-12-08
Luke Kenneth Casso...
add an on_Display function which is being used by some...
tree
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commitdiff
2021-12-08
Luke Kenneth Casso...
found a way to print out the names of the signals
tree
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commitdiff
2021-12-08
Luke Kenneth Casso...
absolute import again
tree
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commitdiff
2021-12-08
Luke Kenneth Casso...
use full-path imports (so we know where they come from)
tree
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commitdiff
2021-12-08
Mikolaj Wielgus
WIP: Output C instead of Python for Nmigen simulation
tree
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commitdiff
2021-12-08
Mikolaj Wielgus
Source Nmigen simulator from this repository
tree
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commitdiff
2021-12-07
Luke Kenneth Casso...
whoops wrong number
tree
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commitdiff
2021-12-07
Luke Kenneth Casso...
add OP_FETCH_FAILED micro-op
tree
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commitdiff
2021-12-07
Jacob Lifshay
fix broken url
tree
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commitdiff
2021-12-04
Luke Kenneth Casso...
raise a MemException in ISACaller RADIXMMU
tree
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commitdiff
2021-12-02
Luke Kenneth Casso...
regspec_decode_write now stores the decoded write info...
tree
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commitdiff
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