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sv_binutils: introduce Integer class
[openpower-isa.git]
/
src
/
openpower
/
decoder
/
2022-04-19
Dmitry Selyutin
selectable_int: simplify SelectableIntMapping class
tree
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commitdiff
2022-04-19
Dmitry Selyutin
isa.caller: support whole integer pseudo-field
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commitdiff
2022-04-19
Dmitry Selyutin
isa.caller: refactor SVP64PrefixFields class
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commitdiff
2022-04-19
Dmitry Selyutin
isa.caller: refactor SVP64RMFields class
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commitdiff
2022-04-19
Dmitry Selyutin
selectable_int: introduce SelectableIntMapping class
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commitdiff
2022-04-19
Dmitry Selyutin
selectable_int: make FieldSelectableInt.__repr__ more...
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commitdiff
2022-04-19
Dmitry Selyutin
selectable_int: make SelectableInt.__repr__ more flexible
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commitdiff
2022-04-19
Dmitry Selyutin
selectable_int: allow range in FieldSelectableInt
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commitdiff
2022-04-08
Jacob Lifshay
add SPDX-License-Identifier rather than License:
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commitdiff
2022-04-08
Jacob Lifshay
format code
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commitdiff
2022-04-07
Luke Kenneth Casso...
whitespace (80 char limit)
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commitdiff
2022-04-07
Luke Kenneth Casso...
comment 64-bit of predicate (all 1s)
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commitdiff
2022-03-26
Luke Kenneth Casso...
Revert "add python generator version of tree reduction"
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commitdiff
2022-03-25
Jacob Lifshay
add python generator version of tree reduction
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commitdiff
2022-01-24
Luke Kenneth Casso...
remove read of SRR1 for TRAP pipeline, pass via LDSTExc...
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commitdiff
2022-01-21
Luke Kenneth Casso...
add test for setting TB SPR, fix decode map for STATE...
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commitdiff
2022-01-19
Luke Kenneth Casso...
trap types memory exception (TT.MEMEXC) instead of...
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commitdiff
2022-01-19
Luke Kenneth Casso...
add spr-to-state conversion, and support for state1...
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commitdiff
2022-01-18
Luke Kenneth Casso...
see soc/fu/trap/main_stage.py trap() function, and:
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commitdiff
2022-01-18
Jacob Lifshay
grev[w][i][.] pseudo-code works
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commitdiff
2022-01-18
Jacob Lifshay
add log2 pseudo-code helper
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commitdiff
2022-01-18
Jacob Lifshay
format code
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commitdiff
2022-01-18
Jacob Lifshay
add test_caller_logical.py
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commitdiff
2022-01-18
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-soc.org:922...
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commitdiff
2022-01-18
Jacob Lifshay
speed up pywriter
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commitdiff
2022-01-17
Jacob Lifshay
WIP speed up pywriter by caching stuff more and not...
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commitdiff
2022-01-15
Luke Kenneth Casso...
correctly identify atomic reservation CSV file field and
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commitdiff
2022-01-15
Luke Kenneth Casso...
add atomic reservation field to Power Decoder data...
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commitdiff
2022-01-10
Luke Kenneth Casso...
enable privileged-instruction detection which had previ...
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commitdiff
2022-01-06
Jacob Lifshay
add grev[w][i] instructions
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commitdiff
2022-01-06
Jacob Lifshay
format code
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commitdiff
2022-01-06
Jacob Lifshay
add stand-alone simulator bitmanip test
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commitdiff
2022-01-06
Luke Kenneth Casso...
add tlbsync and wait as NOPs
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commitdiff
2022-01-05
Luke Kenneth Casso...
add eieio instruction as a NOP to minor 31 csv
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commitdiff
2022-01-05
Luke Kenneth Casso...
add lbzcix instruction which had been completely forgot...
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commitdiff
2022-01-03
Luke Kenneth Casso...
copy over msr and rename cia to nia in PowerDecoder2
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commitdiff
2021-12-27
Luke Kenneth Casso...
whoops wrong parameter name
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commitdiff
2021-12-27
Luke Kenneth Casso...
quick attempt to fix test_decoder_gas.py (did not work)
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commitdiff
2021-12-27
Mikolaj Wielgus
bool() is !!() for integers
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commitdiff
2021-12-27
Mikolaj Wielgus
Add missing parentheses for explicit operator precedence
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commitdiff
2021-12-26
Luke Kenneth Casso...
add very basic PowerDecode2 test which at least gets...
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commitdiff
2021-12-26
Luke Kenneth Casso...
a few extra things discovered needing c syntax not...
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commitdiff
2021-12-26
Mikolaj Wielgus
Give human-readable names to slots, run functions and...
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commitdiff
2021-12-25
Mikolaj Wielgus
Put CRTL CFFI modules in crtl dir
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commitdiff
2021-12-23
Luke Kenneth Casso...
code cleanup / comments
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commitdiff
2021-12-23
Luke Kenneth Casso...
repeat power decode test to check performance
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commitdiff
2021-12-23
Luke Kenneth Casso...
bit of a tidyup of crtl:
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commitdiff
2021-12-23
Mikolaj Wielgus
Add CRTL templates
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commitdiff
2021-12-23
Mikolaj Wielgus
Give unique names to CRTL-generated modules
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commitdiff
2021-12-23
Mikolaj Wielgus
Move "pending" set to C
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commitdiff
2021-12-22
Mikolaj Wielgus
Make _PySignalState CRTL-aware
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commitdiff
2021-12-21
Luke Kenneth Casso...
take a copy of the wb_get memory and then for each...
tree
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commitdiff
2021-12-21
Luke Kenneth Casso...
ISACaller (actually RADIXMMU) only do virtual memory...
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commitdiff
2021-12-20
Mikolaj Wielgus
Generate variable declaration in some missing places
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commitdiff
2021-12-20
Luke Kenneth Casso...
create header/footer for crtl code-generation
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commitdiff
2021-12-20
Luke Kenneth Casso...
whoops forgot to trap if non-execute (instruction)...
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commitdiff
2021-12-19
Luke Kenneth Casso...
TODO notes for executing ISACaller Invalid Instruction...
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commitdiff
2021-12-19
Luke Kenneth Casso...
pass the mode (LOAD,EXECUTE,STORE) through ISACaller...
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commitdiff
2021-12-17
Mikolaj Wielgus
Call the simulator-generated C using the CFFI
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commitdiff
2021-12-13
Tobias Platen
add namedtuple MSRSpec
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commitdiff
2021-12-12
Luke Kenneth Casso...
copy over fake OP_FETCH_FAILED and instruction on...
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commitdiff
2021-12-10
Jacob Lifshay
change ternlogi to not have Rc field
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commitdiff
2021-12-09
Luke Kenneth Casso...
add FAST SPRs temporarily to power_enums
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commitdiff
2021-12-09
Jacob Lifshay
make ternlogi tests run
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commitdiff
2021-12-09
Jacob Lifshay
add initial ternlogi pseudo-code
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commitdiff
2021-12-08
Luke Kenneth Casso...
add instr_fault to PowerDecoder2
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commitdiff
2021-12-08
Luke Kenneth Casso...
whitespace
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commitdiff
2021-12-08
Luke Kenneth Casso...
code-comments for LDSTException.instr_fault
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commitdiff
2021-12-08
Luke Kenneth Casso...
add an on_Display function which is being used by some...
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commitdiff
2021-12-08
Luke Kenneth Casso...
found a way to print out the names of the signals
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commitdiff
2021-12-08
Luke Kenneth Casso...
absolute import again
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commitdiff
2021-12-08
Luke Kenneth Casso...
use full-path imports (so we know where they come from)
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commitdiff
2021-12-08
Mikolaj Wielgus
WIP: Output C instead of Python for Nmigen simulation
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commitdiff
2021-12-08
Mikolaj Wielgus
Source Nmigen simulator from this repository
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commitdiff
2021-12-07
Luke Kenneth Casso...
whoops wrong number
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commitdiff
2021-12-07
Luke Kenneth Casso...
add OP_FETCH_FAILED micro-op
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commitdiff
2021-12-07
Jacob Lifshay
fix broken url
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commitdiff
2021-12-04
Luke Kenneth Casso...
raise a MemException in ISACaller RADIXMMU
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commitdiff
2021-12-02
Luke Kenneth Casso...
regspec_decode_write now stores the decoded write info...
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commitdiff
2021-12-02
Luke Kenneth Casso...
specify length in RegDecodeInfo explicitly so that...
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commitdiff
2021-12-02
Luke Kenneth Casso...
use namedtuple in get_rdflags
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commitdiff
2021-12-02
Luke Kenneth Casso...
use namedtuple for regspec_decode
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commitdiff
2021-12-02
Luke Kenneth Casso...
add module to regspec_decode_* and get_rdflags
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commitdiff
2021-12-01
Luke Kenneth Casso...
add regspec_decode which takes readmode arg and returns...
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commitdiff
2021-11-30
Luke Kenneth Casso...
attempting to use PowerDecode2 in non-svp64 mode
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commitdiff
2021-11-17
Jacob Lifshay
rename ternary->ternlog and associated form/field TI...
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commitdiff
2021-11-17
Luke Kenneth Casso...
XER regspec_decode_write was not sophisticated enough.
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commitdiff
2021-11-16
Luke Kenneth Casso...
truncate CR regspec_decode_write reg mask to 8 bit
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commitdiff
2021-11-16
Luke Kenneth Casso...
argh, regspec_decode_write is supposed to return single...
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commitdiff
2021-11-16
Luke Kenneth Casso...
name of cr reg3 was numbered 2
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commitdiff
2021-11-13
Jacob Lifshay
remove excess I from ternary-related names
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commitdiff
2021-11-12
Jacob Lifshay
change ternaryi to correct register fields
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commitdiff
2021-11-12
Jacob Lifshay
format code
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commitdiff
2021-11-10
Luke Kenneth Casso...
add RT as an option for ternary instruction as 3rd...
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commitdiff
2021-11-10
Luke Kenneth Casso...
add creation of 8 and 16 DCT butterfly diagrams
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commitdiff
2021-11-09
Tobias Platen
forward mmu sprs
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commitdiff
2021-11-05
Jacob Lifshay
add ternaryi
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commitdiff
2021-11-05
Jacob Lifshay
format code
tree
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commitdiff
2021-11-05
Jacob Lifshay
format code
tree
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commitdiff
2021-11-04
klehman
caller.py: Fix ISACaller modifying test state
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commitdiff
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