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add fmvis as a new RM-1P-1S SVP64 RM type
[openpower-isa.git]
/
src
/
openpower
/
sv
/
sv_analysis.py
2022-07-28
Luke Kenneth Casso...
add fmvis as a new RM-1P-1S SVP64 RM type
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2022-06-30
Luke Kenneth Casso...
do CSV isatables explicitly in sv_analysis.py
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2022-06-30
Luke Kenneth Casso...
explicit output of opcode_regs_deduped in mdwn table...
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2022-05-02
Luke Kenneth Casso...
add missing SVP64 RM "Mode" field which qualifies instr...
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2021-12-09
Luke Kenneth Casso...
add warning about creation of "-.csv" which indicates...
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2021-12-02
Jacob Lifshay
fix sv_analysis command, cuz script created by setup...
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2021-12-02
Jacob Lifshay
format code
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2021-11-30
Dmitry Selyutin
sv_analysis: decouple declarations and definitions
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2021-11-30
Dmitry Selyutin
sv_analysis: use is instead of eq for enums
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2021-11-30
Dmitry Selyutin
sv_analysis: fix single-line binutils comments
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2021-11-27
Dmitry Selyutin
sv_analysis: decouple common disclaimer
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2021-11-27
Dmitry Selyutin
sv_analysis: introduce stub binutils format
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2021-11-27
Dmitry Selyutin
sv_analysis: support format argument
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2021-11-12
Jacob Lifshay
change ternaryi to correct register fields
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2021-11-12
Jacob Lifshay
format code
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2021-08-08
Luke Kenneth Casso...
add bc and bclr to sv_analysis
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2021-07-24
Luke Kenneth Casso...
added an extra SVP64 instruction, svstep, to replace...
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2021-06-25
Luke Kenneth Casso...
identify SVP64 LD bit-reverse pattern as pseudo-assembler
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2021-06-25
Luke Kenneth Casso...
update sv_analysis.py to match new CONDITIONs field...
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2021-06-15
Luke Kenneth Casso...
fix sv_analysis.py for 3R-1W-CRo case, add fmadds/fmsub...
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2021-05-18
Luke Kenneth Casso...
fix SVP64 EXTRA2/3 decode for IEEE754 FP LD/ST operations
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2021-04-23
Luke Kenneth Casso...
sort out sv_analysys.py moving to openpower-isa
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