pcdec. works!
[openpower-isa.git] / src / openpower / test / alu /
2022-07-27 Jacob Lifshayadd another test and fix broken fishmv pseudocode
2022-07-27 Konstantinos Marga... Fix fmvis & fishmv bit handling for d0, add tests for...
2022-07-27 Konstantinos Marga... Add fishmv instruction (bug #887)
2022-07-27 Konstantinos Marga... fix wrong shift in fmvis, use correct immediates in...
2022-07-26 Luke Kenneth Casso... update comments in fmvis case
2022-07-26 Luke Kenneth Casso... add first FP "expected state" use it in fmvis
2022-07-26 Luke Kenneth Casso... bit more docs on fmvis
2022-07-26 Konstantinos Marga... fix form and pseudo-code for fmvis, tests in 64-bit...
2022-07-26 Konstantinos Marga... fix fmvis decoder, it's now a 2-operand instruction
2022-07-26 Konstantinos Marga... Add fmvis instruction + tests, bug #887
2022-07-06 Luke Kenneth Casso... convert ALU svp64_cases.py to new vector reg form
2021-11-26 R Veera KumarShorten expected state code for case_extsb using exts...
2021-11-26 R Veera KumarShorten expected state code for case_extsb in alu_cases...
2021-11-26 R Veera KumarShorten expected state code for case_rand in alu_cases...
2021-11-26 R Veera KumarShorten case_rand_imm alu test case code
2021-11-26 R Veera KumarMake carry_out32 variable boolean and expected state...
2021-11-25 R Veera KumarShortened code in case_addis_nonzero_r0 alu test case
2021-11-25 R Veera KumarCorrect add-equal operator in case_rand_imm
2021-11-25 R Veera KumarShort the code of case_rand_imm
2021-11-24 R Veera KumarFix line so that 80 characters per line is kept and...
2021-11-24 R Veera KumarAdd expected state to case_rand_imm in alu_cases unit...
2021-11-24 Luke Kenneth Casso... tidyup on case_0_adde
2021-11-23 R Veera KumarAdd expected state to case_0_adde in alu_cases unit...
2021-11-23 R Veera KumarAdd expected state to case_rand in alu_cases unit test
2021-11-23 R Veera KumarAdd expected state to case_addis_nonzero_r0 in alu_case...
2021-11-23 R Veera KumarAdd expected state to case_extsb in alu_cases unit...
2021-11-23 R Veera KumarAdd computed CR0 to expected version of case_adde_0
2021-11-22 Luke Kenneth Casso... add expected version of case_adde_0
2021-11-22 R Veera KumarAdd expected state to case_cmpeqb in alu_cases unit...
2021-11-22 R Veera KumarAdd expected state to case_cmplw_microwatt_1 in alu_cas...
2021-11-22 R Veera KumarAdd expected state to case_cmpli_microwatt in alu_cases...
2021-11-22 R Veera KumarAdd expected state to case_cmpl_microwatt_0_disasm...
2021-11-22 R Veera KumarAdd expected state to case_cmpl_microwatt_0 in alu_case...
2021-11-22 R Veera KumarAdd expected state to case_addme_ca_so_4 in alu_cases...
2021-11-22 R Veera KumarAdd expected state to case_addme_ca_so_3 in alu_cases...
2021-11-22 R Veera KumarAdd expected state to case_addme_ca_1 in alu_cases...
2021-11-21 R Veera KumarAdd expected state to case_cmp3 in alu_cases unit test
2021-11-21 R Veera KumarAdd expected state to case_cmp2 in alu_cases unit test
2021-11-21 R Veera KumarAdd expected state to case_cmp in alu_cases unit test
2021-11-21 R Veera KumarAdd expected state to all of case_addze in alu_cases...
2021-11-17 Luke Kenneth Casso... XER regspec_decode_write was not sophisticated enough.
2021-11-17 Luke Kenneth Casso... split up regression cases so that a single Rc=1 add...
2021-11-11 Luke Kenneth Casso... add case-based expected results in addme alu_cases
2021-11-11 Luke Kenneth Casso... invert speedup (commenting-out) of tests
2021-11-11 Luke Kenneth Casso... whitespace
2021-11-11 Luke Kenneth Casso... https://bugs.libre-soc.org/show_bug.cgi?id=730#c27
2021-11-11 Luke Kenneth Casso... add unexpected result to see what happens
2021-11-11 R Veera KumarAdd expected state to case_addze for addze in alu_cases...
2021-11-11 R Veera KumarAdd expected state to case_1_regression for 'add' in...
2021-11-11 R Veera KumarAdd expected state to case_1_regression for extsb in...
2021-11-11 R Veera KumarAdd expected state to case_1_regression for subf (2...
2021-11-10 R Veera KumarAdd expected state to case_1_regression for subf in...
2021-11-09 R Veera KumarAdd expected state to case_1_regression for extsw for...
2021-09-22 Luke Kenneth Casso... add first "ExpectedState" to HDL-sim ALU test cases
2021-07-15 Luke Kenneth Casso... big intrusive update: merge SVREMAP with SVSTATE, remov...
2021-05-06 Luke Kenneth Casso... reformat SVP64 docstrings to vaguely resemble something...
2021-05-06 Luke Kenneth Casso... sphinx docstring highlight of SVP64 listings
2021-05-06 Luke Kenneth Casso... move logical SVP64 test cases to separate file/directory
2021-05-06 Luke Kenneth Casso... whoops error in docstring
2021-05-06 Luke Kenneth Casso... tidy up svp64 cases to make it better suited to documen...
2021-04-25 Cesar StraussAdd a reentrant CR predication test case
2021-04-24 Luke Kenneth Casso... add missing __init__.py to get sphinxdoc working
2021-04-23 Luke Kenneth Casso... add div test cases
2021-04-23 Luke Kenneth Casso... more migration to openpower-isa