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pysvp64db: fix traversal
[openpower-isa.git] / src / openpower / test / bitmanip / bitmanip_cases.py
2024-02-05 Luke Kenneth Casso... bug 1034: add crbinlog unit test commit | commitdiff
2024-02-05 Luke Kenneth Casso... bug 1034: invert ordering of lut indices to match xxeval commit | commitdiff
2024-02-03 Luke Kenneth Casso... fix merge commit | commitdiff
2024-02-02 Luke Kenneth Casso... bug 1034: hooray! sv.crternlogi works. was the test... bug_1034_cr_bin_and_tern commit | commitdiff
2024-01-29 Luke Kenneth Casso... bug 1034: make sv.crternlogi test a vector-vector-scala... commit | commitdiff
2024-01-28 Luke Kenneth Casso... bug 1034: clarify CR field encoding (extra/value) commit | commitdiff
2024-01-27 Luke Kenneth Casso... bug 1034: add first version of sv.crternlogi unit test commit | commitdiff
2024-01-27 Luke Kenneth Casso... bug 1034: yet again move crternlogi due to size of... commit | commitdiff
2024-01-27 Luke Kenneth Casso... bug 10344: had to move crfternlogi to TLI-Form commit | commitdiff
2024-01-25 Luke Kenneth Casso... bug 1034: add crbinlog and crternlogi, rename crbinlog... commit | commitdiff
2024-01-20 Luke Kenneth Casso... bug 1034: add crbinlog unit test, fix binlog test,... commit | commitdiff
2024-01-20 Luke Kenneth Casso... bug 1034: add crbinlog and binlog, unit test binlog... commit | commitdiff
2024-01-17 Luke Kenneth Casso... bug 1034: add crternlogi. involved adding a new CR... commit | commitdiff
2023-12-07 Luke Kenneth Casso... add gbbd (bmatflip) test case - just the one for now commit | commitdiff
2023-09-12 Jacob Lifshayremove grev, leaving unit tests for later use by grevlut commit | commitdiff
2023-07-22 Luke Kenneth Casso... shortened variable names, commit | commitdiff
2023-07-22 Jacob Lifshayadd SVP64 test for byte reverse insns commit | commitdiff
2023-07-20 Jacob Lifshayadd byte reverse instructions from PowerISA v3.1B commit | commitdiff
2023-06-02 Dmitry Selyutinpysvp64asm: integrate into insndb commit | commitdiff
2022-08-13 Luke Kenneth Casso... invalidate grev cases, replaced by grevlut commit | commitdiff
2022-05-03 Jacob Lifshayadd Rc to ternlogi commit | commitdiff
2022-01-18 Jacob Lifshaygrev[w][i][.] pseudo-code works commit | commitdiff
2022-01-06 Jacob Lifshayadd stand-alone simulator bitmanip test commit | commitdiff
2021-12-10 Jacob Lifshayadd ternlogi to SVP64Asm commit | commitdiff
2021-12-10 Jacob Lifshaychange ternlogi to not have Rc field commit | commitdiff
2021-12-09 Jacob Lifshaymake ternlogi tests run commit | commitdiff
2021-12-09 Jacob Lifshayrename ternaryi to ternlogi commit | commitdiff
2021-11-17 Jacob Lifshayadd bitmanip_cases.py commit | commitdiff