add code-comments explaining that setvl, svstep svremap and svshape are
[openpower-isa.git] / src / openpower / test / bitmanip /
2022-05-03 Jacob Lifshayadd Rc to ternlogi
2022-01-18 Jacob Lifshaygrev[w][i][.] pseudo-code works
2022-01-06 Jacob Lifshayadd stand-alone simulator bitmanip test
2021-12-10 Jacob Lifshayadd ternlogi to SVP64Asm
2021-12-10 Jacob Lifshaychange ternlogi to not have Rc field
2021-12-09 Jacob Lifshaymake ternlogi tests run
2021-12-09 Jacob Lifshayrename ternaryi to ternlogi
2021-11-17 Jacob Lifshayadd bitmanip_cases.py