whoops missed lsb-shift parameter
[openpower-isa.git] / src / openpower / test /
2022-08-31 Jacob Lifshaytest less cases of utf-8 validation, to avoid taking...
2022-08-29 Jacob Lifshaysvp64_utf_8_validation.py works!
2022-08-29 Jacob Lifshayallow tests to pass None in order to not have to match...
2022-08-29 Jacob Lifshaylog memory in a more fancy format, like hexdump -C
2022-08-26 Jacob Lifshayworking on svp64_utf_8_validation.py -- still broken...
2022-08-26 Jacob Lifshayadd more logging
2022-08-26 Jacob Lifshayconvert more `print`s to `log`s
2022-08-26 Jacob Lifshaylog rather than print SKIPPED
2022-08-25 Jacob Lifshaymark all known-broken tests so CI passes
2022-08-25 Jacob Lifshaymake pytest ignore non-test classes, these're the last...
2022-08-25 Jacob Lifshayremove last uses of soc
2022-08-25 Jacob Lifshayformat test/runner.py
2022-08-24 Jacob Lifshayworking on svp64 utf-8 validation -- still broken
2022-08-24 Jacob Lifshayadd self.subTest and src_loc_at support to TestAccumula...
2022-08-24 Jacob Lifshayfinished writing svp64 utf-8 validation algorithm ...
2022-08-23 Jacob Lifshayadd WIP svp64 utf-8 validation algorithm
2022-08-13 Luke Kenneth Casso... invalidate grev cases, replaced by grevlut
2022-07-27 Jacob Lifshayadd another test and fix broken fishmv pseudocode
2022-07-27 Konstantinos Marga... Fix fmvis & fishmv bit handling for d0, add tests for...
2022-07-27 Konstantinos Marga... Add fishmv instruction (bug #887)
2022-07-27 Konstantinos Marga... fix wrong shift in fmvis, use correct immediates in...
2022-07-26 Luke Kenneth Casso... update comments in fmvis case
2022-07-26 Luke Kenneth Casso... add first FP "expected state" use it in fmvis
2022-07-26 Luke Kenneth Casso... bit more docs on fmvis
2022-07-26 Konstantinos Marga... fix form and pseudo-code for fmvis, tests in 64-bit...
2022-07-26 Konstantinos Marga... fix fmvis decoder, it's now a 2-operand instruction
2022-07-26 Konstantinos Marga... Add fmvis instruction + tests, bug #887
2022-07-06 Luke Kenneth Casso... convert Logical svp64_cases.py to new vector reg form
2022-07-06 Luke Kenneth Casso... convert ALU svp64_cases.py to new vector reg form
2022-07-05 Luke Kenneth Casso... add regression test for completely borked value from...
2022-07-05 Luke Kenneth Casso... take deepcopy of regs passed in to avoid accidental...
2022-06-26 Luke Kenneth Casso... add test case for kaivb to jump to 0x2700
2022-06-26 Luke Kenneth Casso... add TrapTestCase for KAIVB
2022-06-26 Luke Kenneth Casso... hmm do expected state in rfid trap case
2022-06-25 Luke Kenneth Casso... correct input example for SOF case_3_bmask
2022-06-25 Andrey MiroshnikovAdded sif/sof
2022-06-25 Luke Kenneth Casso... corrections to test cases, it is not quite
2022-06-25 Luke Kenneth Casso... update comments in av_cases.py test_1_bmask
2022-06-24 Andrey MiroshnikovAdded second bmask test case, designed to be multi...
2022-06-24 Luke Kenneth Casso... add first bmask unit test
2022-06-22 Andrey MiroshnikovAdded pc based on len(lst)
2022-06-22 Luke Kenneth Casso... add another cprop test, experimenting
2022-06-22 Luke Kenneth Casso... add 2nd cprop test to see what happens
2022-06-22 Luke Kenneth Casso... expected number of instructions is 1 (therefore PC...
2022-06-22 Andrey MiroshnikovAdded cprop test case, fails atm (not enabled by default)
2022-06-20 Luke Kenneth Casso... add absolute-signed-diff next to absolute-unsigned...
2022-06-20 Luke Kenneth Casso... rename absadd[us] to absdac[ud]
2022-06-19 Jacob Lifshayfix minu[.] to be unsigned
2022-06-19 Luke Kenneth Casso... add absadds - signed accumulating add. DRAFT
2022-06-19 Luke Kenneth Casso... add absadd (unsigned) DRAFT
2022-06-19 Luke Kenneth Casso... add absolute-difference DRAFT
2022-06-19 Luke Kenneth Casso... add average-add DRAFT pseudocode and CSV
2022-06-19 Luke Kenneth Casso... add the rest of min/max DRAFT av opcodes
2022-06-19 Luke Kenneth Casso... add maxs DRAFT instruction
2022-05-03 Jacob Lifshayadd Rc to ternlogi
2022-04-08 Jacob Lifshayadd SPDX-License-Identifier rather than License:
2022-02-28 Luke Kenneth Casso... add default XLEN=64 as temporary hack
2022-02-28 Luke Kenneth Casso... hmm something wrong with negative branch
2022-02-24 Jacob Lifshayadd rldimi test case
2022-01-28 Luke Kenneth Casso... rename wb_get_classic
2022-01-24 Luke Kenneth Casso... add extra bc regression test
2022-01-21 Luke Kenneth Casso... add test for setting TB SPR, fix decode map for STATE...
2022-01-18 Jacob Lifshaygrev[w][i][.] pseudo-code works
2022-01-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-soc.org:922...
2022-01-17 Luke Kenneth Casso... add a couple of trap pipeline unit tests
2022-01-12 Luke Kenneth Casso... add second version of wb_get which can cope with pipelines
2022-01-10 Luke Kenneth Casso... increase addr_wid to 64 in TestRunnerBase. hm this...
2022-01-06 Jacob Lifshayadd stand-alone simulator bitmanip test
2022-01-05 Luke Kenneth Casso... add lbzcix instruction which had been completely forgot...
2021-12-28 Cesar StraussAdd an inorder flag to pspec
2021-12-27 Luke Kenneth Casso... add empty default_mem for running without MMU
2021-12-24 Luke Kenneth Casso... clear memory is optional
2021-12-24 Luke Kenneth Casso... whoops forgot to put the copy of the wb_get memory...
2021-12-23 Luke Kenneth Casso... add load-store byte-reverse 64-bit unit test
2021-12-21 Luke Kenneth Casso... take a copy of the wb_get memory and then for each...
2021-12-19 Luke Kenneth Casso... add "stop at pc" argument to TestCase,
2021-12-19 Luke Kenneth Casso... save mmu simulation to different gtkwave file in TestRu...
2021-12-18 Luke Kenneth Casso... bit more verbose info about number of instructions run
2021-12-18 Luke Kenneth Casso... use new core domain variable in TestRunnerBase
2021-12-18 Luke Kenneth Casso... update comments in wb_get
2021-12-18 Luke Kenneth Casso... ooo annoying, it is actually icache.ibus
2021-12-18 Luke Kenneth Casso... whoops error in accessing icache.ibus which is an inter...
2021-12-16 Luke Kenneth Casso... start/stop wb_get in TestRunnerBase, otherwise it never...
2021-12-15 Luke Kenneth Casso... must read off of ibus in wb_get TestRunnerBase
2021-12-12 Luke Kenneth Casso... enable mmu_cache_wb for wb_get mode in TestRunnerBase
2021-12-12 Luke Kenneth Casso... add pretty-print of MMU memory to be used for a TestRun...
2021-12-10 Jacob Lifshayadd ternlogi to SVP64Asm
2021-12-10 Jacob Lifshaychange ternlogi to not have Rc field
2021-12-09 Luke Kenneth Casso... add I-Cache wishbone bus to wb_get when MMU and ROM...
2021-12-09 Jacob Lifshaymake ternlogi tests run
2021-12-09 Jacob Lifshayrename ternaryi to ternlogi
2021-12-05 Tobias Platenfix microwatt_mmu and and wishbone_memory output in...
2021-12-05 Luke Kenneth Casso... connect to dcache.bus standard interface when using...
2021-12-05 Luke Kenneth Casso... correct import of wb_get function
2021-12-04 Luke Kenneth Casso... add name parameter to wb_get
2021-12-04 Luke Kenneth Casso... add wb_get function for emulating wishbone interface
2021-12-04 Luke Kenneth Casso... enable MMU in SimRunner if requested. now HDL and...
2021-12-04 Luke Kenneth Casso... test in SimState for access to RADIX memory, bypass...
2021-12-03 Luke Kenneth Casso... add link to exceptions in gtkw traces
2021-12-01 Luke Kenneth Casso... fix expected state in hazard test
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