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sv_binutils: introduce Integer class
[openpower-isa.git]
/
src
/
openpower
/
test
/
2022-04-08
Jacob Lifshay
add SPDX-License-Identifier rather than License:
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commitdiff
2022-02-28
Luke Kenneth Casso...
add default XLEN=64 as temporary hack
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commitdiff
2022-02-28
Luke Kenneth Casso...
hmm something wrong with negative branch
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commitdiff
2022-02-24
Jacob Lifshay
add rldimi test case
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commitdiff
2022-01-28
Luke Kenneth Casso...
rename wb_get_classic
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commitdiff
2022-01-24
Luke Kenneth Casso...
add extra bc regression test
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commitdiff
2022-01-21
Luke Kenneth Casso...
add test for setting TB SPR, fix decode map for STATE...
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commitdiff
2022-01-18
Jacob Lifshay
grev[w][i][.] pseudo-code works
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commitdiff
2022-01-18
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-soc.org:922...
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commitdiff
2022-01-17
Luke Kenneth Casso...
add a couple of trap pipeline unit tests
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commitdiff
2022-01-12
Luke Kenneth Casso...
add second version of wb_get which can cope with pipelines
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commitdiff
2022-01-10
Luke Kenneth Casso...
increase addr_wid to 64 in TestRunnerBase. hm this...
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commitdiff
2022-01-06
Jacob Lifshay
add stand-alone simulator bitmanip test
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commitdiff
2022-01-05
Luke Kenneth Casso...
add lbzcix instruction which had been completely forgot...
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commitdiff
2021-12-28
Cesar Strauss
Add an inorder flag to pspec
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commitdiff
2021-12-27
Luke Kenneth Casso...
add empty default_mem for running without MMU
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commitdiff
2021-12-24
Luke Kenneth Casso...
clear memory is optional
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commitdiff
2021-12-24
Luke Kenneth Casso...
whoops forgot to put the copy of the wb_get memory...
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commitdiff
2021-12-23
Luke Kenneth Casso...
add load-store byte-reverse 64-bit unit test
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commitdiff
2021-12-21
Luke Kenneth Casso...
take a copy of the wb_get memory and then for each...
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commitdiff
2021-12-19
Luke Kenneth Casso...
add "stop at pc" argument to TestCase,
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commitdiff
2021-12-19
Luke Kenneth Casso...
save mmu simulation to different gtkwave file in TestRu...
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commitdiff
2021-12-18
Luke Kenneth Casso...
bit more verbose info about number of instructions run
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commitdiff
2021-12-18
Luke Kenneth Casso...
use new core domain variable in TestRunnerBase
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commitdiff
2021-12-18
Luke Kenneth Casso...
update comments in wb_get
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commitdiff
2021-12-18
Luke Kenneth Casso...
ooo annoying, it is actually icache.ibus
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commitdiff
2021-12-18
Luke Kenneth Casso...
whoops error in accessing icache.ibus which is an inter...
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commitdiff
2021-12-16
Luke Kenneth Casso...
start/stop wb_get in TestRunnerBase, otherwise it never...
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commitdiff
2021-12-15
Luke Kenneth Casso...
must read off of ibus in wb_get TestRunnerBase
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commitdiff
2021-12-12
Luke Kenneth Casso...
enable mmu_cache_wb for wb_get mode in TestRunnerBase
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commitdiff
2021-12-12
Luke Kenneth Casso...
add pretty-print of MMU memory to be used for a TestRun...
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commitdiff
2021-12-10
Jacob Lifshay
add ternlogi to SVP64Asm
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commitdiff
2021-12-10
Jacob Lifshay
change ternlogi to not have Rc field
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commitdiff
2021-12-09
Luke Kenneth Casso...
add I-Cache wishbone bus to wb_get when MMU and ROM...
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commitdiff
2021-12-09
Jacob Lifshay
make ternlogi tests run
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commitdiff
2021-12-09
Jacob Lifshay
rename ternaryi to ternlogi
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commitdiff
2021-12-05
Tobias Platen
fix microwatt_mmu and and wishbone_memory output in...
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commitdiff
2021-12-05
Luke Kenneth Casso...
connect to dcache.bus standard interface when using...
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commitdiff
2021-12-05
Luke Kenneth Casso...
correct import of wb_get function
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commitdiff
2021-12-04
Luke Kenneth Casso...
add name parameter to wb_get
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commitdiff
2021-12-04
Luke Kenneth Casso...
add wb_get function for emulating wishbone interface
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commitdiff
2021-12-04
Luke Kenneth Casso...
enable MMU in SimRunner if requested. now HDL and...
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commitdiff
2021-12-04
Luke Kenneth Casso...
test in SimState for access to RADIX memory, bypass...
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commitdiff
2021-12-03
Luke Kenneth Casso...
add link to exceptions in gtkw traces
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commitdiff
2021-12-01
Luke Kenneth Casso...
fix expected state in hazard test
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commitdiff
2021-12-01
Luke Kenneth Casso...
fix expected state in hazard case_regression_1
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commitdiff
2021-12-01
Luke Kenneth Casso...
add a proper twin addi regression which tests Reservati...
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commitdiff
2021-11-30
Luke Kenneth Casso...
add randomised hazard test
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commitdiff
2021-11-30
Luke Kenneth Casso...
add two more hazard tests
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commitdiff
2021-11-30
Luke Kenneth Casso...
attempting to use PowerDecode2 in non-svp64 mode
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commitdiff
2021-11-27
Luke Kenneth Casso...
add extra overlap hazard test
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commitdiff
2021-11-26
R Veera Kumar
Shorten expected state code for case_extsb using exts...
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commitdiff
2021-11-26
R Veera Kumar
Shorten expected state code for case_extsb in alu_cases...
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commitdiff
2021-11-26
R Veera Kumar
Shorten expected state code for case_rand in alu_cases...
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commitdiff
2021-11-26
R Veera Kumar
Shorten case_rand_imm alu test case code
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commitdiff
2021-11-26
R Veera Kumar
Make carry_out32 variable boolean and expected state...
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commitdiff
2021-11-25
R Veera Kumar
Shortened code in case_addis_nonzero_r0 alu test case
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commitdiff
2021-11-25
R Veera Kumar
Correct add-equal operator in case_rand_imm
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commitdiff
2021-11-25
R Veera Kumar
Short the code of case_rand_imm
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commitdiff
2021-11-24
R Veera Kumar
Fix line so that 80 characters per line is kept and...
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commitdiff
2021-11-24
R Veera Kumar
Add expected state to case_rand_imm in alu_cases unit...
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commitdiff
2021-11-24
Luke Kenneth Casso...
corrections to hazard overlap test
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commitdiff
2021-11-24
Luke Kenneth Casso...
add extra hazard unit tests
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commitdiff
2021-11-24
Luke Kenneth Casso...
tidyup on case_0_adde
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commitdiff
2021-11-24
Luke Kenneth Casso...
correct write-after-write hazard test (expected values)
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commitdiff
2021-11-23
R Veera Kumar
Add expected state to case_0_adde in alu_cases unit...
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commitdiff
2021-11-23
Luke Kenneth Casso...
add write-after-write hazard test for inorder core
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commitdiff
2021-11-23
R Veera Kumar
Add expected state to case_rand in alu_cases unit test
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commitdiff
2021-11-23
R Veera Kumar
Add expected state to case_addis_nonzero_r0 in alu_case...
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commitdiff
2021-11-23
R Veera Kumar
Add expected state to case_extsb in alu_cases unit...
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commitdiff
2021-11-23
R Veera Kumar
Add computed CR0 to expected version of case_adde_0
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commitdiff
2021-11-22
Luke Kenneth Casso...
add expected version of case_adde_0
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commitdiff
2021-11-22
Luke Kenneth Casso...
adding a couple more hazard avoidance cases
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commitdiff
2021-11-22
R Veera Kumar
Add expected state to case_cmpeqb in alu_cases unit...
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commitdiff
2021-11-22
R Veera Kumar
Add expected state to case_cmplw_microwatt_1 in alu_cas...
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commitdiff
2021-11-22
R Veera Kumar
Add expected state to case_cmpli_microwatt in alu_cases...
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commitdiff
2021-11-22
R Veera Kumar
Add expected state to case_cmpl_microwatt_0_disasm...
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commitdiff
2021-11-22
R Veera Kumar
Add expected state to case_cmpl_microwatt_0 in alu_case...
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commitdiff
2021-11-22
R Veera Kumar
Add expected state to case_addme_ca_so_4 in alu_cases...
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commitdiff
2021-11-22
R Veera Kumar
Add expected state to case_addme_ca_so_3 in alu_cases...
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commitdiff
2021-11-22
R Veera Kumar
Add expected state to case_addme_ca_1 in alu_cases...
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commitdiff
2021-11-21
Luke Kenneth Casso...
sigh, for overlap mode there is no safe way to get...
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commitdiff
2021-11-21
Luke Kenneth Casso...
move dump state to base class State in test API
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commitdiff
2021-11-21
R Veera Kumar
Add expected state to case_cmp3 in alu_cases unit test
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commitdiff
2021-11-21
R Veera Kumar
Add expected state to case_cmp2 in alu_cases unit test
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commitdiff
2021-11-21
R Veera Kumar
Add expected state to case_cmp in alu_cases unit test
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commitdiff
2021-11-21
R Veera Kumar
Add expected state to all of case_addze in alu_cases...
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commitdiff
2021-11-17
Jacob Lifshay
add bitmanip_cases.py
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commitdiff
2021-11-17
Luke Kenneth Casso...
add allow_overlap argument to TestRunnerBase
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commitdiff
2021-11-17
Luke Kenneth Casso...
code-comments
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commitdiff
2021-11-17
Luke Kenneth Casso...
XER regspec_decode_write was not sophisticated enough.
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commitdiff
2021-11-17
Luke Kenneth Casso...
split up regression cases so that a single Rc=1 add...
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commitdiff
2021-11-11
Luke Kenneth Casso...
add case-based expected results in addme alu_cases
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commitdiff
2021-11-11
Luke Kenneth Casso...
invert speedup (commenting-out) of tests
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commitdiff
2021-11-11
Luke Kenneth Casso...
sort out numbering on CRs in SimState
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commitdiff
2021-11-11
Luke Kenneth Casso...
whitespace
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commitdiff
2021-11-11
Luke Kenneth Casso...
fix test API State.compare which was overwriting intreg...
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commitdiff
2021-11-11
Luke Kenneth Casso...
https://bugs.libre-soc.org/show_bug.cgi?id=730#c27
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commitdiff
2021-11-11
Luke Kenneth Casso...
add unexpected result to see what happens
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commitdiff
2021-11-11
Luke Kenneth Casso...
use append on expected state dump, not ideal but
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