sv_binutils: introduce Integer class
[openpower-isa.git] / src / openpower / test /
2022-04-08 Jacob Lifshayadd SPDX-License-Identifier rather than License:
2022-02-28 Luke Kenneth Casso... add default XLEN=64 as temporary hack
2022-02-28 Luke Kenneth Casso... hmm something wrong with negative branch
2022-02-24 Jacob Lifshayadd rldimi test case
2022-01-28 Luke Kenneth Casso... rename wb_get_classic
2022-01-24 Luke Kenneth Casso... add extra bc regression test
2022-01-21 Luke Kenneth Casso... add test for setting TB SPR, fix decode map for STATE...
2022-01-18 Jacob Lifshaygrev[w][i][.] pseudo-code works
2022-01-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-soc.org:922...
2022-01-17 Luke Kenneth Casso... add a couple of trap pipeline unit tests
2022-01-12 Luke Kenneth Casso... add second version of wb_get which can cope with pipelines
2022-01-10 Luke Kenneth Casso... increase addr_wid to 64 in TestRunnerBase. hm this...
2022-01-06 Jacob Lifshayadd stand-alone simulator bitmanip test
2022-01-05 Luke Kenneth Casso... add lbzcix instruction which had been completely forgot...
2021-12-28 Cesar StraussAdd an inorder flag to pspec
2021-12-27 Luke Kenneth Casso... add empty default_mem for running without MMU
2021-12-24 Luke Kenneth Casso... clear memory is optional
2021-12-24 Luke Kenneth Casso... whoops forgot to put the copy of the wb_get memory...
2021-12-23 Luke Kenneth Casso... add load-store byte-reverse 64-bit unit test
2021-12-21 Luke Kenneth Casso... take a copy of the wb_get memory and then for each...
2021-12-19 Luke Kenneth Casso... add "stop at pc" argument to TestCase,
2021-12-19 Luke Kenneth Casso... save mmu simulation to different gtkwave file in TestRu...
2021-12-18 Luke Kenneth Casso... bit more verbose info about number of instructions run
2021-12-18 Luke Kenneth Casso... use new core domain variable in TestRunnerBase
2021-12-18 Luke Kenneth Casso... update comments in wb_get
2021-12-18 Luke Kenneth Casso... ooo annoying, it is actually icache.ibus
2021-12-18 Luke Kenneth Casso... whoops error in accessing icache.ibus which is an inter...
2021-12-16 Luke Kenneth Casso... start/stop wb_get in TestRunnerBase, otherwise it never...
2021-12-15 Luke Kenneth Casso... must read off of ibus in wb_get TestRunnerBase
2021-12-12 Luke Kenneth Casso... enable mmu_cache_wb for wb_get mode in TestRunnerBase
2021-12-12 Luke Kenneth Casso... add pretty-print of MMU memory to be used for a TestRun...
2021-12-10 Jacob Lifshayadd ternlogi to SVP64Asm
2021-12-10 Jacob Lifshaychange ternlogi to not have Rc field
2021-12-09 Luke Kenneth Casso... add I-Cache wishbone bus to wb_get when MMU and ROM...
2021-12-09 Jacob Lifshaymake ternlogi tests run
2021-12-09 Jacob Lifshayrename ternaryi to ternlogi
2021-12-05 Tobias Platenfix microwatt_mmu and and wishbone_memory output in...
2021-12-05 Luke Kenneth Casso... connect to dcache.bus standard interface when using...
2021-12-05 Luke Kenneth Casso... correct import of wb_get function
2021-12-04 Luke Kenneth Casso... add name parameter to wb_get
2021-12-04 Luke Kenneth Casso... add wb_get function for emulating wishbone interface
2021-12-04 Luke Kenneth Casso... enable MMU in SimRunner if requested. now HDL and...
2021-12-04 Luke Kenneth Casso... test in SimState for access to RADIX memory, bypass...
2021-12-03 Luke Kenneth Casso... add link to exceptions in gtkw traces
2021-12-01 Luke Kenneth Casso... fix expected state in hazard test
2021-12-01 Luke Kenneth Casso... fix expected state in hazard case_regression_1
2021-12-01 Luke Kenneth Casso... add a proper twin addi regression which tests Reservati...
2021-11-30 Luke Kenneth Casso... add randomised hazard test
2021-11-30 Luke Kenneth Casso... add two more hazard tests
2021-11-30 Luke Kenneth Casso... attempting to use PowerDecode2 in non-svp64 mode
2021-11-27 Luke Kenneth Casso... add extra overlap hazard test
2021-11-26 R Veera KumarShorten expected state code for case_extsb using exts...
2021-11-26 R Veera KumarShorten expected state code for case_extsb in alu_cases...
2021-11-26 R Veera KumarShorten expected state code for case_rand in alu_cases...
2021-11-26 R Veera KumarShorten case_rand_imm alu test case code
2021-11-26 R Veera KumarMake carry_out32 variable boolean and expected state...
2021-11-25 R Veera KumarShortened code in case_addis_nonzero_r0 alu test case
2021-11-25 R Veera KumarCorrect add-equal operator in case_rand_imm
2021-11-25 R Veera KumarShort the code of case_rand_imm
2021-11-24 R Veera KumarFix line so that 80 characters per line is kept and...
2021-11-24 R Veera KumarAdd expected state to case_rand_imm in alu_cases unit...
2021-11-24 Luke Kenneth Casso... corrections to hazard overlap test
2021-11-24 Luke Kenneth Casso... add extra hazard unit tests
2021-11-24 Luke Kenneth Casso... tidyup on case_0_adde
2021-11-24 Luke Kenneth Casso... correct write-after-write hazard test (expected values)
2021-11-23 R Veera KumarAdd expected state to case_0_adde in alu_cases unit...
2021-11-23 Luke Kenneth Casso... add write-after-write hazard test for inorder core
2021-11-23 R Veera KumarAdd expected state to case_rand in alu_cases unit test
2021-11-23 R Veera KumarAdd expected state to case_addis_nonzero_r0 in alu_case...
2021-11-23 R Veera KumarAdd expected state to case_extsb in alu_cases unit...
2021-11-23 R Veera KumarAdd computed CR0 to expected version of case_adde_0
2021-11-22 Luke Kenneth Casso... add expected version of case_adde_0
2021-11-22 Luke Kenneth Casso... adding a couple more hazard avoidance cases
2021-11-22 R Veera KumarAdd expected state to case_cmpeqb in alu_cases unit...
2021-11-22 R Veera KumarAdd expected state to case_cmplw_microwatt_1 in alu_cas...
2021-11-22 R Veera KumarAdd expected state to case_cmpli_microwatt in alu_cases...
2021-11-22 R Veera KumarAdd expected state to case_cmpl_microwatt_0_disasm...
2021-11-22 R Veera KumarAdd expected state to case_cmpl_microwatt_0 in alu_case...
2021-11-22 R Veera KumarAdd expected state to case_addme_ca_so_4 in alu_cases...
2021-11-22 R Veera KumarAdd expected state to case_addme_ca_so_3 in alu_cases...
2021-11-22 R Veera KumarAdd expected state to case_addme_ca_1 in alu_cases...
2021-11-21 Luke Kenneth Casso... sigh, for overlap mode there is no safe way to get...
2021-11-21 Luke Kenneth Casso... move dump state to base class State in test API
2021-11-21 R Veera KumarAdd expected state to case_cmp3 in alu_cases unit test
2021-11-21 R Veera KumarAdd expected state to case_cmp2 in alu_cases unit test
2021-11-21 R Veera KumarAdd expected state to case_cmp in alu_cases unit test
2021-11-21 R Veera KumarAdd expected state to all of case_addze in alu_cases...
2021-11-17 Jacob Lifshayadd bitmanip_cases.py
2021-11-17 Luke Kenneth Casso... add allow_overlap argument to TestRunnerBase
2021-11-17 Luke Kenneth Casso... code-comments
2021-11-17 Luke Kenneth Casso... XER regspec_decode_write was not sophisticated enough.
2021-11-17 Luke Kenneth Casso... split up regression cases so that a single Rc=1 add...
2021-11-11 Luke Kenneth Casso... add case-based expected results in addme alu_cases
2021-11-11 Luke Kenneth Casso... invert speedup (commenting-out) of tests
2021-11-11 Luke Kenneth Casso... sort out numbering on CRs in SimState
2021-11-11 Luke Kenneth Casso... whitespace
2021-11-11 Luke Kenneth Casso... fix test API State.compare which was overwriting intreg...
2021-11-11 Luke Kenneth Casso... https://bugs.libre-soc.org/show_bug.cgi?id=730#c27
2021-11-11 Luke Kenneth Casso... add unexpected result to see what happens
2021-11-11 Luke Kenneth Casso... use append on expected state dump, not ideal but
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