add sv.ffmadds test to test_pysvp64dis.py
[openpower-isa.git] / src / openpower /
2023-05-15 Luke Kenneth Casso... add sv.ffmadds test to test_pysvp64dis.py
2023-05-15 Luke Kenneth Casso... in DCT/FFT 3-in 2-out set had to make RT same source...
2023-05-15 Luke Kenneth Casso... move RG bit in CRops to Mode[2] from Mode[3] MSB0-numbering
2023-05-15 Luke Kenneth Casso... got linked-list-pointer-chasing working
2023-05-15 Luke Kenneth Casso... bug in power_insn.py where record.svp64 is None (??)
2023-05-15 Luke Kenneth Casso... have to now add LD/ST-update instructions to list of...
2023-05-15 Luke Kenneth Casso... prevent duplicate EXTRA2/3 in power_insndb when assembl...
2023-05-14 Dmitry Selyutinpower_insn: filter out empty pcode lines
2023-05-14 Dmitry Selyutinpower_insn: fix verbose assembly extra info
2023-05-14 Luke Kenneth Casso... attempting to get LD/ST-Update SVP64 EXTRA3 working...
2023-05-14 Luke Kenneth Casso... classify LD/ST-Immediate-Update as EXTRA3.
2023-05-14 Luke Kenneth Casso... whitespace cleanup and remove as many PHP-style-formatt...
2023-05-13 Jacob Lifshayadd rest of bfp_* helpers needed to run fcvt js test
2023-05-13 Jacob Lifshayignore FPSCR in fcvt js test
2023-05-13 Jacob Lifshayallow ignoring FPSCR in tests
2023-05-13 Jacob Lifshaypow should not become self.pow
2023-05-12 Luke Kenneth Casso... check expected CR fields in Data-Dependent Fail-First
2023-05-12 Jacob Lifshaymake truediv available to pseudocode
2023-05-12 Jacob Lifshayadd bfp classification predicates
2023-05-12 Jacob Lifshayallow assigning BFPState and SelectableMSB0Fraction...
2023-05-12 Jacob Lifshayadd support for *_flag global variables needed by bfp_...
2023-05-12 Jacob Lifshaymake lexer replace class with class_ since it's a pytho...
2023-05-12 Jacob Lifshayfix SelectableMSB0Fraction's constructor
2023-05-12 Jacob Lifshayfix broken FPSCR fields
2023-05-12 Jacob LifshayRevert "add stub reset_xflags function"
2023-05-11 Luke Kenneth Casso... corrections to dd-ffirst tests when VLi=0, the write...
2023-05-11 Jacob LifshaySelectableMSB0Fraction is now basically complete and...
2023-05-10 Luke Kenneth Casso... add very very very basic write-out of instruction log
2023-05-10 Jacob LifshayMerge branch 'support-fields'
2023-05-10 Luke Kenneth Casso... add ld/st data-dependent fail-first /vli (inclusive)
2023-05-10 Luke Kenneth Casso... fix data-dependent fail-first on load
2023-05-10 Dmitry Selyutinpower_insn: remove redundant logs
2023-05-10 Dmitry Selyutincyclemodel/inorder: hide set inheritance
2023-05-10 Dmitry Selyutincyclemodel/inorder: fix coding style
2023-05-10 Luke Kenneth Casso... extend previous hard-coded magic constant (256) used...
2023-05-10 Jacob Lifshayadd WIP fp_working_format.py
2023-05-10 Jacob Lifshaychange FPSCR to a required parameter of ISACallerHelper support-fields
2023-05-10 Jacob LifshayRevert "remove now-unnecessary SO global, since XER...
2023-05-10 Jacob Lifshayswitch to using self.FPSCR
2023-05-10 Jacob Lifshayswitch to using FPSCRState for double2single.mdwn
2023-05-10 Jacob Lifshayadd self.FPSCR
2023-05-10 Jacob Lifshayremove now-unnecessary SO global, since XER[SO] syntax...
2023-05-10 Jacob Lifshaysupport FPSCR[RN] syntax that translates to FPSCR.RN
2023-05-10 Jacob Lifshayadd support for accessing XER using XER.SO syntax ...
2023-05-09 Luke Kenneth Casso... separate ISAPages out from inherited ISA Class
2023-05-09 Jacob LifshaySetFX is not a normal function -- it can assign to...
2023-05-09 Jacob Lifshayadd parser support for attributes like FPSCR.RN
2023-05-09 Jacob Lifshaymove apply_trailer into parser class
2023-05-09 Jacob Lifshaybypass ply's eating SyntaxErrors
2023-05-09 Jacob LifshayFPSCR.FPRF can be assigned strings
2023-05-09 Jacob Lifshayadd XERState since XER has fields too
2023-05-09 Jacob Lifshayfix some broken FieldSelectableInt handling
2023-05-07 Luke Kenneth Casso... comment TODO on Load-Fault in strncpy example
2023-05-07 Luke Kenneth Casso... add stub reset_xflags function
2023-05-06 Luke Kenneth Casso... add FPSCR to Test API (ExpectedState, SimState). untested
2023-05-06 Luke Kenneth Casso... add FPSCR to ISACaller
2023-05-06 Luke Kenneth Casso... notes: make FPSCR definition more like MSR (see openpow...
2023-05-06 Luke Kenneth Casso... drastically simplify fpscr.py. extreme overcomplexity...
2023-05-06 Luke Kenneth Casso... add comment about why the new check has been added
2023-05-06 Luke Kenneth Casso... get table down to under 80 chars per line
2023-05-06 Jacob Lifshayfix fpscr table parser error reporting
2023-05-06 Jacob Lifshayadd FPSCRState and FPSCRRecord and a FPSCR smoke-test
2023-05-05 Jacob Lifshayadd initial fmv/fcvt tests, though they're broken due...
2023-05-05 Jacob Lifshayadd check that generated .py files are in .gitignore
2023-05-05 Jacob Lifshayverify fields.txt forms' field separators ('|') line...
2023-05-04 Konstantinos Marga... merge maddrs/msubrs, unit tests changed accordingly
2023-05-04 Konstantinos Marga... Add 2 more instructions to help with 2-coeff butterfly
2023-05-04 Konstantinos Marga... Handle large 64-bit values, but only the low 64-bit...
2023-05-04 Konstantinos Marga... do proper rounding, no rounding for SH=0 (for now)...
2023-05-04 Konstantinos Marga... handle negatives correctly by adding sign bit to final...
2023-05-04 Konstantinos Marga... almost there, positive values work, negative values...
2023-05-04 Konstantinos Marga... Turns out DCTI-Form is another variant of A-Form
2023-05-04 Konstantinos Marga... WIP: maddsubrs initial approach
2023-05-04 Luke Kenneth Casso... maddsubrs no longer has CR0
2023-05-04 Jacob Lifshayfix forgotten stuff from last commit
2023-05-04 Jacob Lifshayadd fcvt/fmv -- no tests yet
2023-05-04 Jacob Lifshaysupport calling functions with no args in pseudocode
2023-05-04 Jacob Lifshayshow actual mdwn source location in backtrace when...
2023-05-04 Jacob Lifshaymove Assign to parser class in prep for improving synta...
2023-05-04 Jacob Lifshaycomment fmin*/fmax* since they're being replaced with...
2023-05-04 Jacob Lifshayfix non-zero assembly operands being zero
2023-05-02 Luke Kenneth Casso... add links between decode and issue
2023-05-02 Luke Kenneth Casso... reserve writes in Issue Phase, add comment
2023-05-02 Luke Kenneth Casso... add Issue phase and writes/reads possible in CPU
2023-05-02 Luke Kenneth Casso... add Decode and CPU classes
2023-05-02 Luke Kenneth Casso... add quick preamble header
2023-05-02 Luke Kenneth Casso... update comments and correct retiring, remove registers...
2023-05-02 Luke Kenneth Casso... start on cycle-accurate model of inorder core
2023-04-30 Dmitry Selyutinpower_insn: forbid zero for non-zero operands
2023-04-30 Dmitry Selyutinpower_insn: drop registers remapping hack
2023-04-30 Dmitry Selyutinpower_insn: support int and index opcode methods
2023-04-28 Luke Kenneth Casso... reduce number of operands to ffmadds as well
2023-04-28 Jacob Lifshayprefix-sum remap works!
2023-04-28 Jacob Lifshaychange order to tuple in remap preduce tests/demos...
2023-04-28 Jacob Lifshayfix <u and >u with int arguments
2023-04-28 Luke Kenneth Casso... reduce fdmadds down to only 3 operands, RT-overwrite...
2023-04-27 Luke Kenneth Casso... add implicit rs detection for maddsubrs
2023-04-27 Luke Kenneth Casso... link in new parallel-prefix REMAP schedule
2023-04-27 Jacob Lifshayadd scan/prefix-sum support to copy of parallel-reduce...
2023-04-27 Jacob Lifshayformat remap_preduce_yield.py
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