power: Add support for power models
[gem5.git] / src / sim / SConscript
2016-04-05 David Guillen Fandospower: Add support for power models
2014-11-18 Akash Bagdiapower: Add power states to ClockedObject
2015-05-12 David Guillen Fandossim: Adding thermal model support
2016-03-17 Alexandru Dutusyscall_emul: add extra debug support for syscalls
2015-12-04 Andreas Sandbergsim: Add support for generating back traces on errors
2015-09-03 Nilay Vaishmerged with recent commits.
2015-09-02 Curtis Dunhamsim: tag-based checkpoint versioning
2015-07-24 Brandon Potterbase: refactor process class (specifically FdMap and...
2015-02-11 Andreas Sandbergsim: Move the BaseTLB to src/arch/generic/
2014-10-16 Andreas Hanssonconfig: Add the ability to read a config file using...
2014-10-16 Andrew Bardsleyconfig: Add a --without-python option to build process
2014-08-10 Geoffrey Blakeconfig: Add SubSystem container for simobjects
2014-07-23 Andrew Bardsleycpu: `Minor' in-order CPU model
2014-06-30 Stephan Diestelhorstpower: Add basic DVFS support for gem5
2013-11-25 Steve Reinhardt... sim: simulate with multiple threads and event queues
2013-09-04 Andreas Hanssonarch: Resurrect the NOISA build target and rename it...
2013-08-19 Akash Bagdiapower: Add voltage domains to the clock domains
2013-06-27 Akash Bagdiasim: Add the notion of clock domains to all ClockedObjects
2013-06-03 Andreas Sandbergsim: Add debug output when executing pseudo-instructions
2012-11-02 Andreas Sandbergsim: Move the draining interface into a separate base...
2012-08-21 Andreas HanssonClock: Move the clock and related functions to ClockedO...
2012-08-15 Anthony GutierrezO3,ARM: fix some problems with drain/switchout function...
2012-02-01 Gabe BlackMerge ... head, hopefully the last time for this batch.
2012-01-31 Gabe BlackMerge with main repository.
2012-01-29 Gabe BlackYet another merge with the main repository.
2012-01-28 Gabe BlackMerge with the main repo.
2012-01-16 Gabe BlackMerge yet again with the main repository.
2012-01-07 Gabe BlackAnother merge with the main repository.
2012-01-07 Gabe BlackMerge with the main repository again.
2012-01-07 Gabe BlackMerge with main repository.
2011-11-02 Gabe BlackSE/FS: Get rid of FULL_SYSTEM in sim.
2011-10-31 Gabe BlackSE/FS: Compile in system events in SE mode.
2011-10-30 Gabe BlackSE/FS: Build syscall_emul.cc in FS mode.
2011-10-30 Gabe BlackSE/FS: Build the base process class in FS.
2011-06-03 Nathan Binkertscons: rename TraceFlags to DebugFlags
2011-04-15 Nathan Binkertscons: make a flexible system for guarding source files
2011-02-07 Brad Beckmannm5: added work completed monitoring support
2011-01-19 Gabe BlackTime: Add a mechanism to prevent M5 from running faster...
2010-11-20 Ali SaidiSCons: Support building without an ISA
2010-11-08 Ali SaidiARM: Add checkpointing support
2010-07-06 Steve Reinhardtsim: fold StartupCallback into SimObject
2009-05-05 Korey Sewellmerge code
2009-05-04 Nathan Binkertscons: re-work the *Source functions to take more infor...
2009-04-06 Gabe BlackMerge ARM into the head. ARM will compile but may not...
2009-01-19 Nathan Binkertpython: Rework how things are imported
2008-12-17 Steve ReinhardtMake Alpha pseudo-insts available from SE mode.
2008-10-11 Gabe BlackTLB: Make all tlbs derive from a common base class...
2008-08-04 Nathan Binkertlibm5: Create a libm5 static library for embedding m5.
2008-06-24 Ali SaidiAutomated merge with repo.m5sim.org/m5-stable
2008-06-16 Nathan Binkertadd compile flags to m5
2007-10-31 Steve ReinhardtMerge in bus DPRINTF changes.
2007-10-31 Ali SaidiTraceflags: Add SCons function to created a traceflag...
2007-08-28 Gabe BlackMerge with head.
2007-08-28 Gabe BlackAddress Translation: Make the Generic TLB only compile...
2007-08-27 Gabe BlackAddress Translation: Make SE mode use an actual TLB...
2007-08-01 Gabe BlackMerge with head.
2007-08-01 Gabe BlackMerge with head.
2007-08-01 Ali SaidiMerge Gabe and my changes to arch/mips/utility.hh
2007-08-01 Ali SaidiArguments: Get rid of duplicate code for the Arguments...
2007-07-29 Steve ReinhardtMerge Gabe's changes from head.
2007-07-29 Gabe BlackMerge ... head. style.py was also missing an argument...
2007-07-29 Gabe BlackMerge with head.
2007-07-29 Gabe BlackTurn the instruction tracing code into pluggable sim...
2007-07-27 Nathan BinkertMerge python and x86 changes with cache branch
2007-07-24 Gabe BlackMerge with head.
2007-07-24 Nathan BinkertMajor changes to how SimObjects are created and initial...
2007-06-20 Gabe BlackMerge zizzer.eecs.umich.edu:/bk/newmem
2007-05-31 Gabe BlackMerge zizzer.eecs.umich.edu:/bk/newmem
2007-05-28 Steve ReinhardtMerge vm1.(none):/home/stever/bk/newmem-head
2007-05-28 Nathan BinkertMove SimObject python files alongside the C++ and fix
2007-04-03 Ali SaidiMerge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
2007-03-23 Kevin LimMerge ktlim@zizzer:/bk/newmem
2007-03-15 Gabe BlackMerge zizzer.eecs.umich.edu:/bk/newmem
2007-03-12 Ali SaidiMerge zizzer:/bk/newmem
2007-03-11 Gabe BlackMerge zizzer.eecs.umich.edu:/bk/newmem
2007-03-11 Nathan BinkertRework the way SCons recurses into subdirectories,...