2023-01-15 |
Dmitry Selyutin | power_insn: hide records repr from operands |
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2023-01-15 |
Dmitry Selyutin | power_insn: sort opcodes by sections |
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2023-01-15 |
Dmitry Selyutin | power_insn: fix repr for opcode mask and value |
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2023-01-15 |
Dmitry Selyutin | power_insn: support tables priorities |
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2023-01-15 |
Dmitry Selyutin | power_insn: provide operands helpers |
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2023-01-15 |
Dmitry Selyutin | power_insn: cache operands |
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2023-01-15 |
Dmitry Selyutin | power_insn: deprecate operand record argument |
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2023-01-15 |
Dmitry Selyutin | power_insn: simplify word instruction assembly |
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2023-01-15 |
Dmitry Selyutin | power_insn: introduce PO and XO static operands |
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2023-01-15 |
Dmitry Selyutin | power_insn: introduce record operands helpers |
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2023-01-15 |
Dmitry Selyutin | power_insn: convert spans into properties |
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2023-01-15 |
Dmitry Selyutin | power_insn: bind records to operands |
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2023-01-15 |
Dmitry Selyutin | power_insn: postpone operands initialization |
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2023-01-15 |
Dmitry Selyutin | power_insn: ensure operands are always dataclasses |
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2023-01-15 |
Dmitry Selyutin | power_insn: provide basics for insndb assembly |
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2023-01-15 |
Dmitry Selyutin | power_insn: return None for unknown insn names |
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2023-01-15 |
Dmitry Selyutin | power_insn: introduce signed immediate operand class |
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2023-01-15 |
Dmitry Selyutin | power_insn: rename register operand class |
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2023-01-15 |
Dmitry Selyutin | power_insn: clean and simplify EXTS operands |
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2023-01-15 |
Dmitry Selyutin | power_insn: support FPR operands assembly |
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2023-01-15 |
Dmitry Selyutin | power_insn: support GPR operands |
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2023-01-15 |
Dmitry Selyutin | power_insn: support non-zero operands |
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2023-01-15 |
Dmitry Selyutin | power_insn: allow sign only for SignedOperand |
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2023-01-15 |
Dmitry Selyutin | power_insn: add support for a trivial assembly |
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2023-01-01 |
Luke Kenneth Casso... | correct name for Mem test function |
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2023-01-01 |
Luke Kenneth Casso... | ascii dump on xchacha20 to compare against x86 version |
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2023-01-01 |
Luke Kenneth Casso... | enable misaligned Mem in ISACaller by default |
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2023-01-01 |
Cesar Strauss | Handle newer nMigen adding a "bench" top-level root... |
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2022-12-30 |
Luke Kenneth Casso... | corrections to boundary-wrapped store, and add misalign... |
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2022-12-30 |
Luke Kenneth Casso... | add rollover mem test, store "rolls over" a 64-bit... |
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2022-12-30 |
Luke Kenneth Casso... | add misaligned mem test |
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2022-12-30 |
Luke Kenneth Casso... | add misaligned mem test |
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2022-12-30 |
Luke Kenneth Casso... | add unit test for Mem class, need to add misaligned... |
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2022-12-29 |
Luke Kenneth Casso... | print out memory exception details, on unaligned |
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2022-11-11 |
Jacob Lifshay | add maddedus |
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2022-11-11 |
Jacob Lifshay | fix case_sv_bigint_shift_left_then_back |
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2022-11-11 |
Jacob Lifshay | fix bug in parser when concatenating stuff that isn... |
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2022-11-01 |
Dmitry Selyutin | tests/bigint: provide shadd/shadduw tests |
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2022-11-01 |
Dmitry Selyutin | selectable_int: support variable concatenation |
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2022-10-29 |
Luke Kenneth Casso... | add dsld. (Rc=1) test, make overflow acceptable to... |
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2022-10-28 |
Jacob Lifshay | add tests for carry/overflow calculation of addmeo... |
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2022-10-28 |
Jacob Lifshay | format code |
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2022-10-28 |
Luke Kenneth Casso... | fix dsld pseudocode to use ROTL64 instead of ROTL128 |
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2022-10-28 |
Luke Kenneth Casso... | add test showing that dsld and dsrd are not quite inverses |
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2022-10-28 |
Jacob Lifshay | fix bigint shift tests |
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2022-10-28 |
Luke Kenneth Casso... | fix dsrd, ROTL128 use 128-n not 64-n, |
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2022-10-28 |
Luke Kenneth Casso... | fix dsrd pseudocode for new 3-in 2-out |
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2022-10-28 |
Luke Kenneth Casso... | sort out dsld pseudocode, creating mask is tricky |
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2022-10-28 |
Luke Kenneth Casso... | endeavouring to implement shift-carry-dsld |
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2022-10-28 |
Luke Kenneth Casso... | restore Z23 shadd/shadduw |
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2022-10-28 |
Luke Kenneth Casso... | redo the 3-in 1-out move of dsld/dsrd to EXT04 VA2... |
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2022-10-27 |
Luke Kenneth Casso... | add test for identifying [expr] * name in parser |
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2022-10-27 |
Dmitry Selyutin | power_enums: support shadd/shadduw instructions |
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2022-10-27 |
Dmitry Selyutin | isa/caller.py: support shadd/shadduw instructions |
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2022-10-25 |
Dmitry Selyutin | pysvp64asm: support shadd/shadduw instructions |
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2022-10-25 |
Dmitry Selyutin | pysvp64asm: introduce more flexible Z23 wrapper |
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2022-10-25 |
Dmitry Selyutin | test_pysvp64dis: test shadd/shadduw instructions |
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2022-10-25 |
Dmitry Selyutin | minor_4.csv: support shadd/shadduw instructions |
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2022-10-24 |
Luke Kenneth Casso... | add maxs. combined with cmp capability |
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2022-10-23 |
Luke Kenneth Casso... | use svshape2 instead of svindex for the 4th shape |
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2022-10-22 |
Luke Kenneth Casso... | add extra pysvp64dis tests for divmod2du and maddedu |
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2022-10-22 |
Luke Kenneth Casso... | argh, extremely annoying: 4-operand dsld/dsrd is not... |
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2022-10-22 |
Luke Kenneth Casso... | remove redundant case_dsrd3 |
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2022-10-22 |
Luke Kenneth Casso... | bigint shuffle |
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2022-10-22 |
Jacob Lifshay | fix get_masked_reg and add test |
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2022-10-22 |
Jacob Lifshay | format code removing unused imports |
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2022-10-21 |
Luke Kenneth Casso... | code-comments |
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2022-10-21 |
Luke Kenneth Casso... | add 2nd outer loop, CTR 2 rounds, in chacha20 test |
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2022-10-21 |
Luke Kenneth Casso... | move chacha20 to separate test, set/get masked regs... |
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2022-10-21 |
Luke Kenneth Casso... | move HASK, ROTL32, ROTL64, MASK32, into helper class |
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2022-10-20 |
Luke Kenneth Casso... | comments |
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2022-10-20 |
Luke Kenneth Casso... | add first chacha20 round test |
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2022-10-19 |
Dmitry Selyutin | sv_binutils_fptrans: fix registers generation |
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2022-10-19 |
Luke Kenneth Casso... | TODO, sort out remap indices order |
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2022-10-18 |
Jacob Lifshay | add test for scalar sv.maddedu |
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2022-10-18 |
Jacob Lifshay | add missing files to .gitignore |
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2022-10-16 |
Luke Kenneth Casso... | debug print correction |
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2022-10-16 |
Luke Kenneth Casso... | sigh, have to use yield from on get_out_map() |
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2022-10-16 |
Luke Kenneth Casso... | rewrite get_idx_out2 in ISACaller to split out |
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2022-10-16 |
Luke Kenneth Casso... | rewrite get_idx_out in ISACaller to split out |
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2022-10-16 |
Luke Kenneth Casso... | add unit test showing two svindex calls, found bugs, |
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2022-10-16 |
Luke Kenneth Casso... | code-shuffle, rework get_idx_in() to separate out the... |
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2022-10-14 |
Dmitry Selyutin | sv_binutils_fptrans: fix opcodes mode |
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2022-10-14 |
Dmitry Selyutin | power_insn: really skip sv. entries for PPC database |
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2022-10-14 |
Dmitry Selyutin | sv_binutils_fptrans: generate all permutations |
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2022-10-14 |
Dmitry Selyutin | pysvp64asm: fix coding style |
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2022-10-14 |
Dmitry Selyutin | power_insn: skip sv. instructions in PPC database |
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2022-10-14 |
Dmitry Selyutin | power_insn: fix AA match |
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2022-10-14 |
Dmitry Selyutin | power_insn: do not allow default records |
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2022-10-14 |
Luke Kenneth Casso... | add max-with-getting-index-of vertical-first loop example |
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2022-10-14 |
Luke Kenneth Casso... | SVP64RMModeDecode detects Post-Inc LDST-imm mode |
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2022-10-14 |
Luke Kenneth Casso... | correct comments |
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2022-10-14 |
Luke Kenneth Casso... | add in zeroing on test strncpy |
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2022-10-14 |
Luke Kenneth Casso... | remove unneeded svstate from test |
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2022-10-14 |
Luke Kenneth Casso... | add strncpy example - 6 instructions |
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2022-10-14 |
Luke Kenneth Casso... | add sv.stwu/pi example in test_sv_load_store_postinc |
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2022-10-14 |
Luke Kenneth Casso... | add ld/st-immediate "post-inc" mode support. unit test... |
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2022-10-14 |
Luke Kenneth Casso... | add /pi to sv/trans/svp64.py and power_insns.py |
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2022-10-14 |
Luke Kenneth Casso... | add new LD-Immediate Post constants |
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2022-10-12 |
Luke Kenneth Casso... | add sv.divmod2du test, inverse of the sv.madded |
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