fix forgotten stuff from last commit
[openpower-isa.git] / src /
2023-05-04 Jacob Lifshayfix forgotten stuff from last commit
2023-05-04 Jacob Lifshayadd fcvt/fmv -- no tests yet
2023-05-04 Jacob Lifshaysupport calling functions with no args in pseudocode
2023-05-04 Jacob Lifshayshow actual mdwn source location in backtrace when...
2023-05-04 Jacob Lifshaymove Assign to parser class in prep for improving synta...
2023-05-04 Jacob Lifshaycomment fmin*/fmax* since they're being replaced with...
2023-05-04 Jacob Lifshayfix non-zero assembly operands being zero
2023-05-02 Luke Kenneth Casso... add links between decode and issue
2023-05-02 Luke Kenneth Casso... reserve writes in Issue Phase, add comment
2023-05-02 Luke Kenneth Casso... add Issue phase and writes/reads possible in CPU
2023-05-02 Luke Kenneth Casso... add Decode and CPU classes
2023-05-02 Luke Kenneth Casso... add quick preamble header
2023-05-02 Luke Kenneth Casso... update comments and correct retiring, remove registers...
2023-05-02 Luke Kenneth Casso... start on cycle-accurate model of inorder core
2023-04-30 Dmitry Selyutinpower_insn: forbid zero for non-zero operands
2023-04-30 Dmitry Selyutinpower_insn: drop registers remapping hack
2023-04-30 Dmitry Selyutinpower_insn: support int and index opcode methods
2023-04-28 Luke Kenneth Casso... reduce number of operands to ffmadds as well
2023-04-28 Jacob Lifshayprefix-sum remap works!
2023-04-28 Jacob Lifshaychange order to tuple in remap preduce tests/demos...
2023-04-28 Jacob Lifshayfix <u and >u with int arguments
2023-04-28 Luke Kenneth Casso... reduce fdmadds down to only 3 operands, RT-overwrite...
2023-04-27 Luke Kenneth Casso... add implicit rs detection for maddsubrs
2023-04-27 Luke Kenneth Casso... link in new parallel-prefix REMAP schedule
2023-04-27 Jacob Lifshayadd scan/prefix-sum support to copy of parallel-reduce...
2023-04-27 Jacob Lifshayformat remap_preduce_yield.py
2023-04-26 Dmitry Selyutinpower_insn: deprecate ff/pr common code nopr
2023-04-26 Dmitry Selyutinpower_insn: deprecate PR specifier
2023-04-26 Dmitry Selyutinpower_insn: deprecate normal PR mode
2023-04-26 Dmitry Selyutinpysvp64dis: deprecate pr tests
2023-04-26 Dmitry Selyutinpysvp64asm: deprecate pr tests
2023-04-26 Dmitry Selyutinpower_enums: sync forms
2023-04-25 Luke Kenneth Casso... check RC1, add data-dependent fail-first LD/ST test
2023-04-25 Jacob Lifshayreplace min/max[su][.] with minmax[.]
2023-04-25 Jacob Lifshayadd MM-form
2023-04-25 Jacob Lifshayfix bug where pseudo-code assignments modify more than...
2023-04-21 Jacob Lifshayrename/convert/merge XLCASTU/XLCASTS to EXTZXL/EXTSXL change-xlenification-bug-1064
2023-04-21 Jacob Lifshayadd EXTZ since it's in PowerISA v3.1B (see lbz for...
2023-04-20 Jacob Lifshayfix EXTSXL/XLCASTU/XLCASTS when inputs are python ints
2023-04-18 Jacob Lifshayadd shaddw
2023-04-10 Dmitry Selyutinsv_binutils: fix broken script
2023-04-06 Luke Kenneth Casso... add power_decode_svp64_rm.py capability for new LD...
2023-04-04 Luke Kenneth Casso... add quick test_pysvp64dis.py of LD/ST data-dependent...
2023-04-04 Luke Kenneth Casso... https://bugs.libre-soc.org/show_bug.cgi?id=1047
2023-04-04 Luke Kenneth Casso... whitespace cleanup (80 char per line hard limit)
2023-04-04 Luke Kenneth Casso... comment about massive unnecessary code-duplication...
2023-04-04 Luke Kenneth Casso... fix setvl unit test which happened to use deprecated
2023-03-30 Jacob Lifshayfix add-like CA/OV outputs
2023-03-30 Jacob Lifshayfix broken test case
2023-03-30 Jacob Lifshayadd addex to simulator
2023-03-30 Jacob Lifshayfix typo when getting pseudo-code output variables
2023-03-30 Jacob Lifshayswitch to testing Rc=1 variants
2023-03-30 Jacob Lifshayadd case_nego_
2023-03-30 Jacob Lifshayrename le -> lt since CR bits are lt, gt, eq, and so...
2023-03-29 Luke Kenneth Casso... remove DCT/iDCT redundant modes which require less...
2023-03-29 Jacob Lifshayadd test cases for ca/ov outputs of a bunch of add...
2023-03-28 Jacob Lifshayadd check against PIA's output downloaded from ftp...
2023-03-25 Luke Kenneth Casso... updated simplev setvl specification pseudocode: MAJOR...
2023-03-25 Luke Kenneth Casso... whitespace
2023-03-24 Luke Kenneth Casso... whoops added "CRB-Form" format not "CRB"
2023-03-20 Konstantinos Marga... Pass object code filename instead of actual data
2023-03-12 Luke Kenneth Casso... set MAXVL=VL=32 first, then set vertical-first separately
2023-03-12 Konstantinos Marga... used same input data as the actual C test
2023-03-12 Luke Kenneth Casso... change target registers in test_caller_svp64_chacha20...
2023-03-12 Luke Kenneth Casso... whoops use same temp reg for ctr
2023-03-12 Luke Kenneth Casso... parameterise svstep RT (set to 16 in chacha20 test)
2023-03-12 Luke Kenneth Casso... parameterising VL and SHAPE0-2 in chacha20 test
2023-03-12 Luke Kenneth Casso... parameterise the target block in chacha20 test,
2023-03-12 Luke Kenneth Casso... add print-out for chacha20 schedule
2023-01-24 Dmitry Selyutinpower_enums: enable Rc-aware dsld/dsrd
2023-01-23 Dmitry Selyutinsvp64_utf_8_validation.py: convert labels to addresses
2023-01-23 Dmitry Selyutinpower_insn: fix dst/src duplication detection
2023-01-22 Dmitry Selyutinpower_insn: canonicalize SVP64 insn name
2023-01-21 Dmitry Selyutinpower_insn: hack CR assembly
2023-01-20 Dmitry Selyutinpower_insn: override bogus FMA instructions
2023-01-20 Dmitry Selyutinpower_insn: refactor operands; simplify lookups
2023-01-19 Dmitry Selyutinpysvp64asm: drop obsolete code
2023-01-19 Dmitry Selyutinpower_insn: fix paired registers disassembly
2023-01-18 Dmitry Selyutinpower_insn: support legacy style
2023-01-18 Dmitry Selyutinpower_insn: major refactoring and cleanup
2023-01-18 Dmitry Selyutinpysvp64dis: do not create temporary bytes upon load
2023-01-18 Dmitry Selyutinpower_enums: support paired registers
2023-01-15 Dmitry Selyutinpower_fields: support assignment to same class instance
2023-01-15 Dmitry Selyutinpower_enums: fix CR register types
2023-01-15 Dmitry Selyutinpower_enums: fix RC1 predicates conversion
2023-01-15 Dmitry Selyutinpysvp64asm: avoid empty fields
2023-01-15 Dmitry Selyutinpower_insn: fix signed operands assembly
2023-01-15 Dmitry Selyutinpower_insn: fix arguments conversion
2023-01-15 Dmitry Selyutinpower_insn: fix specifiers errors
2023-01-15 Dmitry Selyutinpower_insn: common records lookup
2023-01-15 Dmitry Selyutinpower_insn: consider EXTS operand as signed
2023-01-15 Dmitry Selyutinpower_insn: discard SVP64 record for word instructions
2023-01-15 Dmitry Selyutinpower_insn: support pi/lf specifiers
2023-01-15 Dmitry Selyutinpower_insn: support ctr/cti specifiers
2023-01-15 Dmitry Selyutinpower_insn: support vs/vsi/vsb/vsbi specifiers
2023-01-15 Dmitry Selyutinpower_insn: support lru specifier
2023-01-15 Dmitry Selyutinpower_insn: support slu specifier
2023-01-15 Dmitry Selyutinpower_insn: support sl specifier
2023-01-15 Dmitry Selyutinpower_insn: support snz specifier
2023-01-15 Dmitry Selyutinpower_insn: support all specifier
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