Move "pending" set to C
[openpower-isa.git] / src /
2021-12-23 Mikolaj WielgusMove "pending" set to C
2021-12-22 Mikolaj WielgusMake _PySignalState CRTL-aware
2021-12-21 Luke Kenneth Casso... take a copy of the wb_get memory and then for each...
2021-12-21 Luke Kenneth Casso... ISACaller (actually RADIXMMU) only do virtual memory...
2021-12-20 Mikolaj WielgusGenerate variable declaration in some missing places
2021-12-20 Luke Kenneth Casso... create header/footer for crtl code-generation
2021-12-20 Luke Kenneth Casso... whoops forgot to trap if non-execute (instruction)...
2021-12-19 Luke Kenneth Casso... TODO notes for executing ISACaller Invalid Instruction...
2021-12-19 Luke Kenneth Casso... pass the mode (LOAD,EXECUTE,STORE) through ISACaller...
2021-12-19 Luke Kenneth Casso... add "stop at pc" argument to TestCase,
2021-12-19 Dmitry Selyutinsv/binutils.py: provide sketch sv_decode.vhdl converter
2021-12-19 Luke Kenneth Casso... save mmu simulation to different gtkwave file in TestRu...
2021-12-18 Luke Kenneth Casso... bit more verbose info about number of instructions run
2021-12-18 Luke Kenneth Casso... use new core domain variable in TestRunnerBase
2021-12-18 Luke Kenneth Casso... update comments in wb_get
2021-12-18 Luke Kenneth Casso... ooo annoying, it is actually icache.ibus
2021-12-18 Luke Kenneth Casso... whoops error in accessing icache.ibus which is an inter...
2021-12-17 Mikolaj WielgusCall the simulator-generated C using the CFFI
2021-12-16 Luke Kenneth Casso... start/stop wb_get in TestRunnerBase, otherwise it never...
2021-12-15 Luke Kenneth Casso... must read off of ibus in wb_get TestRunnerBase
2021-12-13 Tobias Platenadd namedtuple MSRSpec
2021-12-12 Luke Kenneth Casso... copy over fake OP_FETCH_FAILED and instruction on...
2021-12-12 Luke Kenneth Casso... enable mmu_cache_wb for wb_get mode in TestRunnerBase
2021-12-12 Luke Kenneth Casso... add pretty-print of MMU memory to be used for a TestRun...
2021-12-10 Jacob Lifshayadd ternlogi to SVP64Asm
2021-12-10 Jacob Lifshayformat code
2021-12-10 Jacob Lifshaychange ternlogi to not have Rc field
2021-12-09 Luke Kenneth Casso... add I-Cache wishbone bus to wb_get when MMU and ROM...
2021-12-09 Luke Kenneth Casso... add warning about creation of "-.csv" which indicates...
2021-12-09 Luke Kenneth Casso... add FAST SPRs temporarily to power_enums
2021-12-09 Jacob Lifshaymake ternlogi tests run
2021-12-09 Jacob Lifshayrename ternaryi to ternlogi
2021-12-09 Jacob Lifshayadd initial ternlogi pseudo-code
2021-12-08 Luke Kenneth Casso... add instr_fault to PowerDecoder2
2021-12-08 Luke Kenneth Casso... whitespace
2021-12-08 Luke Kenneth Casso... code-comments for LDSTException.instr_fault
2021-12-08 Luke Kenneth Casso... add an on_Display function which is being used by some...
2021-12-08 Luke Kenneth Casso... found a way to print out the names of the signals
2021-12-08 Luke Kenneth Casso... absolute import again
2021-12-08 Luke Kenneth Casso... use full-path imports (so we know where they come from)
2021-12-08 Mikolaj WielgusWIP: Output C instead of Python for Nmigen simulation
2021-12-08 Mikolaj WielgusSource Nmigen simulator from this repository
2021-12-07 Luke Kenneth Casso... whoops wrong number
2021-12-07 Luke Kenneth Casso... add OP_FETCH_FAILED micro-op
2021-12-07 Jacob Lifshayfix broken url
2021-12-05 Tobias Platenfix microwatt_mmu and and wishbone_memory output in...
2021-12-05 Luke Kenneth Casso... connect to dcache.bus standard interface when using...
2021-12-05 Luke Kenneth Casso... correct import of wb_get function
2021-12-04 Luke Kenneth Casso... add name parameter to wb_get
2021-12-04 Luke Kenneth Casso... add wb_get function for emulating wishbone interface
2021-12-04 Luke Kenneth Casso... raise a MemException in ISACaller RADIXMMU
2021-12-04 Luke Kenneth Casso... enable MMU in SimRunner if requested. now HDL and...
2021-12-04 Luke Kenneth Casso... test in SimState for access to RADIX memory, bypass...
2021-12-03 Luke Kenneth Casso... add a namedtuple LDSTExceptionTuple which allows obtaining
2021-12-03 Luke Kenneth Casso... add link to exceptions in gtkw traces
2021-12-02 Luke Kenneth Casso... regspec_decode_write now stores the decoded write info...
2021-12-02 Luke Kenneth Casso... specify length in RegDecodeInfo explicitly so that...
2021-12-02 Luke Kenneth Casso... use namedtuple in get_rdflags
2021-12-02 Luke Kenneth Casso... use namedtuple for regspec_decode
2021-12-02 Luke Kenneth Casso... add module to regspec_decode_* and get_rdflags
2021-12-02 Jacob Lifshayfix sv_analysis command, cuz script created by setup...
2021-12-02 Jacob Lifshayformat code
2021-12-01 Luke Kenneth Casso... fix expected state in hazard test
2021-12-01 Luke Kenneth Casso... fix expected state in hazard case_regression_1
2021-12-01 Luke Kenneth Casso... add a proper twin addi regression which tests Reservati...
2021-12-01 Luke Kenneth Casso... add regspec_decode which takes readmode arg and returns...
2021-11-30 Dmitry Selyutinsv_analysis: decouple declarations and definitions
2021-11-30 Dmitry Selyutinsv_analysis: use is instead of eq for enums
2021-11-30 Dmitry Selyutinsv_analysis: fix single-line binutils comments
2021-11-30 Luke Kenneth Casso... add randomised hazard test
2021-11-30 Luke Kenneth Casso... add two more hazard tests
2021-11-30 Luke Kenneth Casso... attempting to use PowerDecode2 in non-svp64 mode
2021-11-27 Dmitry Selyutinsv_analysis: decouple common disclaimer
2021-11-27 Dmitry Selyutinsv_analysis: introduce stub binutils format
2021-11-27 Dmitry Selyutinsv_analysis: support format argument
2021-11-27 Luke Kenneth Casso... add extra overlap hazard test
2021-11-26 R Veera KumarShorten expected state code for case_extsb using exts...
2021-11-26 R Veera KumarShorten expected state code for case_extsb in alu_cases...
2021-11-26 R Veera KumarShorten expected state code for case_rand in alu_cases...
2021-11-26 R Veera KumarShorten case_rand_imm alu test case code
2021-11-26 R Veera KumarMake carry_out32 variable boolean and expected state...
2021-11-25 R Veera KumarShortened code in case_addis_nonzero_r0 alu test case
2021-11-25 R Veera KumarCorrect add-equal operator in case_rand_imm
2021-11-25 R Veera KumarShort the code of case_rand_imm
2021-11-24 R Veera KumarFix line so that 80 characters per line is kept and...
2021-11-24 R Veera KumarAdd expected state to case_rand_imm in alu_cases unit...
2021-11-24 Luke Kenneth Casso... corrections to hazard overlap test
2021-11-24 Luke Kenneth Casso... add extra hazard unit tests
2021-11-24 Luke Kenneth Casso... tidyup on case_0_adde
2021-11-24 Luke Kenneth Casso... correct write-after-write hazard test (expected values)
2021-11-23 R Veera KumarAdd expected state to case_0_adde in alu_cases unit...
2021-11-23 Luke Kenneth Casso... add write-after-write hazard test for inorder core
2021-11-23 R Veera KumarAdd expected state to case_rand in alu_cases unit test
2021-11-23 R Veera KumarAdd expected state to case_addis_nonzero_r0 in alu_case...
2021-11-23 R Veera KumarAdd expected state to case_extsb in alu_cases unit...
2021-11-23 R Veera KumarAdd computed CR0 to expected version of case_adde_0
2021-11-22 Luke Kenneth Casso... add expected version of case_adde_0
2021-11-22 Luke Kenneth Casso... adding a couple more hazard avoidance cases
2021-11-22 R Veera KumarAdd expected state to case_cmpeqb in alu_cases unit...
2021-11-22 R Veera KumarAdd expected state to case_cmplw_microwatt_1 in alu_cas...
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