add svremap manual instruction (Primary Opcode 22, sandbox)
[openpower-isa.git] / src /
2021-07-05 Luke Kenneth Casso... add svremap manual instruction (Primary Opcode 22,...
2021-07-05 Luke Kenneth Casso... add SVSHAPE class, starting to add to ISACaller
2021-07-05 Luke Kenneth Casso... add function to turn permute into an order list
2021-07-05 Luke Kenneth Casso... update SVREMAP to match spec
2021-07-01 Luke Kenneth Casso... add temporary SV pseudocode
2021-07-01 Luke Kenneth Casso... add TEMPORARY svremap form and instruction
2021-06-29 Luke Kenneth Casso... re-enable accidentally-disabled sv ld/st tests
2021-06-28 Luke Kenneth Casso... add extra offset for FRB, for FFT Cooley-Tukey twin...
2021-06-27 Luke Kenneth Casso... add new SVP64 FFT twin multiply-and-accumulate unit...
2021-06-27 Luke Kenneth Casso... add new (experimental) ffmadds and ffmsubs, for FFT...
2021-06-27 Luke Kenneth Casso... override logic for getting FRS in SVP64 FFT mode
2021-06-27 Luke Kenneth Casso... add FRS decode (2nd output) for SVP64 FFT FP mul-add...
2021-06-27 Luke Kenneth Casso... change name to OP_FP_MADD to identify fmadd (etc)
2021-06-27 Luke Kenneth Casso... comments on SVP64 LD/ST Mode detection
2021-06-27 Luke Kenneth Casso... add SVP64 FFT mode to PowerDecoder, add CSV entries
2021-06-26 Luke Kenneth Casso... add LD bit-reversed unit test
2021-06-26 Luke Kenneth Casso... comment out l*br pseudo-ops from power_enums.py
2021-06-26 Luke Kenneth Casso... use If Elif in power_decoder conditions, a lot easier...
2021-06-26 Luke Kenneth Casso... move D const update to after picking up main input...
2021-06-25 Luke Kenneth Casso... identify SVP64 LD bit-reverse pattern as pseudo-assembler
2021-06-25 Luke Kenneth Casso... only set conditions in PowerDecoder2 for svp64 mode
2021-06-25 Luke Kenneth Casso... update sv_analysis.py to match new CONDITIONs field...
2021-06-25 Luke Kenneth Casso... rename svp64 bit-reversed LD instructions to not confli...
2021-06-24 Luke Kenneth Casso... allow default decoder to be created with no col/row...
2021-06-24 Luke Kenneth Casso... add in Power Decoder conditions to select SVP64 bit...
2021-06-24 Luke Kenneth Casso... add "conditions" for PowerDecoder, basic test
2021-06-24 Luke Kenneth Casso... remove svp64 ld/st decoder tree
2021-06-24 Luke Kenneth Casso... must pass in conditions into Sub-decoders
2021-06-24 Luke Kenneth Casso... search for CSV "Conditions", set to static (disabled...
2021-06-24 Luke Kenneth Casso... add PowerDecoder condition switches (untested, doesnt...
2021-06-24 Luke Kenneth Casso... was going to set 2nd decoder up through MUX but now...
2021-06-24 Luke Kenneth Casso... whoops fix rounding error in mapreduce unit test
2021-06-24 Luke Kenneth Casso... only add svdecldst in PowerDecoder2 or LDST PowerDecode...
2021-06-24 Luke Kenneth Casso... use PowerOp copy of PowerDecodeSubset in get_op
2021-06-24 Luke Kenneth Casso... add "user_svp64_ldst_dec" flag to PowerDecodeSubset
2021-06-24 Luke Kenneth Casso... use new PowerOp.like function in PowerDecoder, fix...
2021-06-24 Luke Kenneth Casso... use get_op on "internal_op" instead of self.dec.op...
2021-06-24 Luke Kenneth Casso... do shorter-path detection of SVP64 LD/ST bitreverse...
2021-06-24 Luke Kenneth Casso... tidy up PowerOp and rename svp64 ldst decoder creater
2021-06-24 Luke Kenneth Casso... add comment about perfcounters
2021-06-23 Luke Kenneth Casso... get op always using function PowerDecoder.op_get
2021-06-23 Luke Kenneth Casso... add PowerOp.like function to be able to duplicate a...
2021-06-23 Luke Kenneth Casso... add SVP64 alternative LDST decoder (unused so far)
2021-06-23 Luke Kenneth Casso... only add SVP64 bitreverse mode for LDs at the moment...
2021-06-23 Luke Kenneth Casso... add SVP64 LD/ST "bitrev" alternative CSV
2021-06-23 Luke Kenneth Casso... add sv bitrev "major" CSV table
2021-06-23 Luke Kenneth Casso... add start of bit-reverse mode for LD/ST to SVP64 encode...
2021-06-23 Luke Kenneth Casso... add mul-add to list of instructions
2021-06-23 Luke Kenneth Casso... add ASCII art example to int predicated SVP64
2021-06-23 Luke Kenneth Casso... add VL and srcstep to ISACaller namespace
2021-06-23 Luke Kenneth Casso... add SHL64 helper function
2021-06-23 Luke Kenneth Casso... add bitrev to pywriter autogenerator
2021-06-23 Luke Kenneth Casso... add bitrev function to be used in LD-ST-bitrev FFT/DCT
2021-06-23 Luke Kenneth Casso... better ways to do sign-inversion (without multiply...
2021-06-23 Luke Kenneth Casso... add sign-inversion argument to FPMUL/DIV helpers
2021-06-19 Luke Kenneth Casso... increase number of registers to 128 in pypowersim
2021-06-19 Luke Kenneth Casso... set regfile in ISACaller equal to length of initial...
2021-06-19 Luke Kenneth Casso... add mapreduce "reverse gear" unit tests
2021-06-19 Luke Kenneth Casso... add mapreduce "reverse gear" to PowerDecoder2. gets...
2021-06-19 Luke Kenneth Casso... add decode of "reverse gear" in SVP64 reduce mode
2021-06-19 Luke Kenneth Casso... add "reverse-gear" mode to mapreduce in SVP64
2021-06-17 Luke Kenneth Casso... add SVP64REMAP Record
2021-06-17 Luke Kenneth Casso... shuffle comments
2021-06-16 Luke Kenneth Casso... sorted out order of FPMULADD32 helper, only have roundi...
2021-06-16 Luke Kenneth Casso... fix fmadds/fmsubs FPMULADD32 helper
2021-06-16 Luke Kenneth Casso... reorder arguments to FPMULADD32 to match pseudocode
2021-06-16 Luke Kenneth Casso... ad fnmadd and fnmsubs to ISA pseudocode
2021-06-15 Luke Kenneth Casso... whoops forgot import
2021-06-15 Luke Kenneth Casso... whoops still using DOUBLE(SINGLE(x)) rather than DOUBLE...
2021-06-15 Luke Kenneth Casso... fix sv_analysis.py for 3R-1W-CRo case, add fmadds/fmsub...
2021-06-15 Luke Kenneth Casso... add fmadds and fmsubs to Power ISA pseudo-code, add...
2021-06-15 Luke Kenneth Casso... add comments into mapreduce example
2021-06-14 Luke Kenneth Casso... sigh bug in setvl, temporarily setting to 7 not 8
2021-06-14 Luke Kenneth Casso... recognise setvl instruction during SVP64 translation
2021-06-14 Luke Kenneth Casso... whoops forgot format-to-format conversion
2021-06-14 Luke Kenneth Casso... series of text macro formats to look for: x.v, x.s (x)
2021-06-14 Luke Kenneth Casso... add basic "macro" (.set) support to SVP64Asm
2021-06-09 Luke Kenneth Casso... add some more comments in the mapreduce svp64 examples...
2021-06-09 Luke Kenneth Casso... add sv.fmuls/mr - mapreduce - FP multiply-single test
2021-06-09 Luke Kenneth Casso... add first scalar mapreduce SVP64 example
2021-06-09 Luke Kenneth Casso... add what might turn out to be only what is needed to...
2021-06-08 Luke Kenneth Casso... whoops, carry-over during rounding picks MSB not LSB
2021-06-08 Luke Kenneth Casso... whoops copy sign over on zero
2021-06-08 Luke Kenneth Casso... exponent bitwidth in DOUBLE2SINGLE needs to be 11 bits...
2021-06-08 Luke Kenneth Casso... use new auto-generated DOUBLE2SINGLE from isafunctions...
2021-06-08 Luke Kenneth Casso... add detection of function parameters in parser
2021-06-08 Luke Kenneth Casso... add better debug logs and asserts for SelectableInt...
2021-06-08 Luke Kenneth Casso... add support in pyparser for negative numbers
2021-06-03 Luke Kenneth Casso... whoops, in1_isvec and dec_bi are optional
2021-06-02 Luke Kenneth Casso... fmuls test showing rounding error against qemu
2021-06-02 Luke Kenneth Casso... found FP single-conversion error, from the pseudocode...
2021-06-02 Luke Kenneth Casso... add commented-out debug prints
2021-06-02 Luke Kenneth Casso... whoops sorting SPRs, stop that for now
2021-06-02 Luke Kenneth Casso... get qemu FP regs correctly
2021-06-02 Luke Kenneth Casso... FP basic qemu sim, testing fadds loads and stores
2021-06-02 Luke Kenneth Casso... appears that the FP operation takes place at full 64...
2021-06-01 Luke Kenneth Casso... whoops missing argument
2021-06-01 Luke Kenneth Casso... move spot-check mem compare to a function
2021-06-01 Luke Kenneth Casso... check both LD and ST in qemu compare
2021-06-01 Luke Kenneth Casso... bizarre, GPR 3 is set by qemu to non-zero at startup.
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