power_fields: avoid unknown attributes
[openpower-isa.git] / src /
2023-01-15 Dmitry Selyutinpower_fields: avoid unknown attributes
2023-01-15 Dmitry Selyutinpower_insn: fix combined zz disassembly
2023-01-15 Dmitry Selyutinpower_insn: refactor w/sw/dw specifiers
2023-01-15 Dmitry Selyutinpower_insn: support zz/sz/dz specifiers
2023-01-15 Dmitry Selyutinpower_enums: unify predicates classes
2023-01-15 Dmitry Selyutinpower_enums: deprecate CRType enum
2023-01-15 Dmitry Selyutinpower_enums: clean code
2023-01-15 Dmitry Selyutinpower_enums: support 8/16/32 in SVP64Width
2023-01-15 Dmitry Selyutinpower_insn: switch to SVP64SubVL enum
2023-01-15 Dmitry Selyutinpower_enums: support subvl conversions
2023-01-15 Dmitry Selyutinpower_insn: validate predicates masks
2023-01-15 Dmitry Selyutinpower_enums: support predicate type property
2023-01-15 Dmitry Selyutinpower_insn: introduce validation stubs
2023-01-15 Dmitry Selyutinpower_insn: support predicates masks
2023-01-15 Dmitry Selyutinpower_insn: support failfirst/predresult
2023-01-15 Dmitry Selyutinpower_enums: support predicates
2023-01-15 Dmitry Selyutinpower_insn: support subvector length specifiers
2023-01-15 Dmitry Selyutinpower_insn: support width specifier
2023-01-15 Dmitry Selyutinpower_insn: fix Rc record property
2023-01-15 Dmitry Selyutinpysvp64asm: allow insndb-based assembly
2023-01-15 Dmitry Selyutinpower_enums: clean CR definitions
2023-01-15 Dmitry Selyutinpower_fields: support field bits assignment
2023-01-15 Dmitry Selyutinpower_insn: support empty arguments
2023-01-15 Dmitry Selyutinpower_insn: support CR operands disassembly
2023-01-15 Dmitry Selyutinpower_insn: fix opcodes generation (again)
2023-01-15 Dmitry Selyutinpower_insn: simplify spans and bytes conversion
2023-01-15 Dmitry Selyutinpower_insn: fix operands iteration
2023-01-15 Dmitry Selyutinpower_insn: support CR operands assembly
2023-01-15 Dmitry Selyutinpower_insn: refactor extandable operands assembly
2023-01-15 Dmitry Selyutinpower_insn: remap GPR and FPR operands
2023-01-15 Dmitry Selyutinpower_insn: unify GPR and FPR assembly
2023-01-15 Dmitry Selyutinpower_insn: provide SVP64 assembly stub
2023-01-15 Dmitry Selyutinpysvp64asm: deprecate custom_insn helper
2023-01-15 Dmitry Selyutinpower_insn: discard overlaps for dynamic operands
2023-01-15 Dmitry Selyutinpower_insn: fix DOperandDX span
2023-01-15 Dmitry Selyutinpower_insn: fix XO static operand
2023-01-15 Dmitry Selyutinpower_insn: hide records repr from operands
2023-01-15 Dmitry Selyutinpower_insn: sort opcodes by sections
2023-01-15 Dmitry Selyutinpower_insn: fix repr for opcode mask and value
2023-01-15 Dmitry Selyutinpower_insn: support tables priorities
2023-01-15 Dmitry Selyutinpower_insn: provide operands helpers
2023-01-15 Dmitry Selyutinpower_insn: cache operands
2023-01-15 Dmitry Selyutinpower_insn: deprecate operand record argument
2023-01-15 Dmitry Selyutinpower_insn: simplify word instruction assembly
2023-01-15 Dmitry Selyutinpower_insn: introduce PO and XO static operands
2023-01-15 Dmitry Selyutinpower_insn: introduce record operands helpers
2023-01-15 Dmitry Selyutinpower_insn: convert spans into properties
2023-01-15 Dmitry Selyutinpower_insn: bind records to operands
2023-01-15 Dmitry Selyutinpower_insn: postpone operands initialization
2023-01-15 Dmitry Selyutinpower_insn: ensure operands are always dataclasses
2023-01-15 Dmitry Selyutinpower_insn: provide basics for insndb assembly
2023-01-15 Dmitry Selyutinpower_insn: return None for unknown insn names
2023-01-15 Dmitry Selyutinpower_insn: introduce signed immediate operand class
2023-01-15 Dmitry Selyutinpower_insn: rename register operand class
2023-01-15 Dmitry Selyutinpower_insn: clean and simplify EXTS operands
2023-01-15 Dmitry Selyutinpower_insn: support FPR operands assembly
2023-01-15 Dmitry Selyutinpower_insn: support GPR operands
2023-01-15 Dmitry Selyutinpower_insn: support non-zero operands
2023-01-15 Dmitry Selyutinpower_insn: allow sign only for SignedOperand
2023-01-15 Dmitry Selyutinpower_insn: add support for a trivial assembly
2023-01-01 Luke Kenneth Casso... correct name for Mem test function
2023-01-01 Luke Kenneth Casso... ascii dump on xchacha20 to compare against x86 version
2023-01-01 Luke Kenneth Casso... enable misaligned Mem in ISACaller by default
2023-01-01 Cesar StraussHandle newer nMigen adding a "bench" top-level root...
2022-12-30 Luke Kenneth Casso... corrections to boundary-wrapped store, and add misalign...
2022-12-30 Luke Kenneth Casso... add rollover mem test, store "rolls over" a 64-bit...
2022-12-30 Luke Kenneth Casso... add misaligned mem test
2022-12-30 Luke Kenneth Casso... add misaligned mem test
2022-12-30 Luke Kenneth Casso... add unit test for Mem class, need to add misaligned...
2022-12-29 Luke Kenneth Casso... print out memory exception details, on unaligned
2022-11-11 Jacob Lifshayadd maddedus
2022-11-11 Jacob Lifshayfix case_sv_bigint_shift_left_then_back
2022-11-11 Jacob Lifshayfix bug in parser when concatenating stuff that isn...
2022-11-01 Dmitry Selyutintests/bigint: provide shadd/shadduw tests
2022-11-01 Dmitry Selyutinselectable_int: support variable concatenation
2022-10-29 Luke Kenneth Casso... add dsld. (Rc=1) test, make overflow acceptable to...
2022-10-28 Jacob Lifshayadd tests for carry/overflow calculation of addmeo...
2022-10-28 Jacob Lifshayformat code
2022-10-28 Luke Kenneth Casso... fix dsld pseudocode to use ROTL64 instead of ROTL128
2022-10-28 Luke Kenneth Casso... add test showing that dsld and dsrd are not quite inverses
2022-10-28 Jacob Lifshayfix bigint shift tests
2022-10-28 Luke Kenneth Casso... fix dsrd, ROTL128 use 128-n not 64-n,
2022-10-28 Luke Kenneth Casso... fix dsrd pseudocode for new 3-in 2-out
2022-10-28 Luke Kenneth Casso... sort out dsld pseudocode, creating mask is tricky
2022-10-28 Luke Kenneth Casso... endeavouring to implement shift-carry-dsld
2022-10-28 Luke Kenneth Casso... restore Z23 shadd/shadduw
2022-10-28 Luke Kenneth Casso... redo the 3-in 1-out move of dsld/dsrd to EXT04 VA2...
2022-10-27 Luke Kenneth Casso... add test for identifying [expr] * name in parser
2022-10-27 Dmitry Selyutinpower_enums: support shadd/shadduw instructions
2022-10-27 Dmitry Selyutinisa/caller.py: support shadd/shadduw instructions
2022-10-25 Dmitry Selyutinpysvp64asm: support shadd/shadduw instructions
2022-10-25 Dmitry Selyutinpysvp64asm: introduce more flexible Z23 wrapper
2022-10-25 Dmitry Selyutintest_pysvp64dis: test shadd/shadduw instructions
2022-10-25 Dmitry Selyutinminor_4.csv: support shadd/shadduw instructions
2022-10-24 Luke Kenneth Casso... add maxs. combined with cmp capability
2022-10-23 Luke Kenneth Casso... use svshape2 instead of svindex for the 4th shape
2022-10-22 Luke Kenneth Casso... add extra pysvp64dis tests for divmod2du and maddedu
2022-10-22 Luke Kenneth Casso... argh, extremely annoying: 4-operand dsld/dsrd is not...
2022-10-22 Luke Kenneth Casso... remove redundant case_dsrd3
2022-10-22 Luke Kenneth Casso... bigint shuffle
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