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targets: add versa_ecp5 with sdram (ecp5 soc hat) at 25MHz/no pll
[litex.git]
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test
/
test_code_8b10b.py
2018-02-23
Florent Kermarrec
replace litex.gen imports with migen imports
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2017-04-24
Florent Kermarrec
add test directory with test_code_8b10b.py (from misoc)
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