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targets: add versa_ecp5 with sdram (ecp5 soc hat) at 25MHz/no pll
[litex.git]
/
test
/
test_targets.py
2018-09-24
Florent Kermarrec
test/test_targets: test simple design with all platforms
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2018-09-23
Florent Kermarrec
test/test_targets: update and reorganize targets
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2018-02-23
Florent Kermarrec
replace litex.gen imports with migen imports
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2017-04-24
Florent Kermarrec
test/test_targets: check top.v generation
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2017-04-24
Florent Kermarrec
test: add basic test_targets.py
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