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Prepare for new DDR PHY
[litex.git]
/
top.py
2012-02-19
Sebastien Bourdeauducq
Prepare for new DDR PHY
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2012-02-18
Sebastien Bourdeauducq
Send SDRAM initialization sequence and answer PHY read...
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2012-02-17
Sebastien Bourdeauducq
DFI injector (untested)
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2012-02-17
Sebastien Bourdeauducq
Map DDR PHY controls in CSR
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2012-02-17
Sebastien Bourdeauducq
Connect DDR PHY
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2012-02-16
Sebastien Bourdeauducq
Generate all clocks for the DDR PHY
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2012-02-13
Sebastien Bourdeauducq
Include Wishbone to ASMI bridge
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2012-02-06
Sebastien Bourdeauducq
sram: fix sub-word write
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2012-02-06
Sebastien Bourdeauducq
top: connect UART IRQ
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2012-02-05
Sebastien Bourdeauducq
Memory map
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2012-01-27
Sebastien Bourdeauducq
Add on-chip SRAM
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2012-01-21
Sebastien Bourdeauducq
Use meaningful class names
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2012-01-20
Sebastien Bourdeauducq
Use new verilog.convert API
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2012-01-13
Sebastien Bourdeauducq
convtools -> tools
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2012-01-05
Sebastien Bourdeauducq
Convert -> convert
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2011-12-17
Sebastien Bourdeauducq
uart: new design using FHDL and bank (TX only, incomplete)
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2011-12-17
Sebastien Bourdeauducq
Multiply system clock
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2011-12-16
Sebastien Bourdeauducq
Proper reset generation
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2011-12-16
Sebastien Bourdeauducq
Pay a bit more attention to PEP8
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2011-12-13
Sebastien Bourdeauducq
Initial import
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