framebuffer: disable debugger by default
[litex.git] / verilog / s6ddrphy /
2012-03-14 Sebastien Bourdeauducqasmicon: skeleton
2012-02-24 Sebastien Bourdeauducqddrphy: working on hardware, simulation a bit messed up
2012-02-24 Sebastien Bourdeauducqddrphy: request wrdata_en/rddata_en at the same time...
2012-02-24 Sebastien Bourdeauducqddrphy: reads OK, write data coming out 1/2 cycle too...
2012-02-24 Sebastien Bourdeauducqddrphy: partly working
2012-02-21 Sebastien Bourdeauducqs6ddrphy: read path OK in simulation
2012-02-20 Sebastien Bourdeauducqs6ddrphy: write path OK in simulation
2012-02-20 Sebastien Bourdeauducqs6ddrphy: generate DQ/DQS/DM OE
2012-02-20 Sebastien Bourdeauducqs6ddrphy: DQ/DQS/DM SERDES
2012-02-19 Sebastien Bourdeauducqs6ddrphy: clock, address and command
2012-02-19 Sebastien BourdeauducqPrepare for new DDR PHY
2012-02-17 Sebastien Bourdeauducqs6ddrphy: use single-ended DQS
2012-02-14 Sebastien Bourdeauducqs6ddrphy: prepare quilt