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top: use two slots for the framebuffer ASMI port
[litex.git]
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2012-07-07
Sebastien Bourdeauducq
framebuffer: fix FIFO read clocking
tree
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commitdiff
2012-07-01
Sebastien Bourdeauducq
framebuffer: FIFO
tree
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commitdiff
2012-06-17
Sebastien Bourdeauducq
VGA framebuffer connections
tree
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commitdiff
2012-05-24
Sebastien Bourdeauducq
Remove some boilerplate
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commitdiff
2012-05-19
Sebastien Bourdeauducq
Add Ethernet MAC
tree
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commitdiff
2012-03-14
Sebastien Bourdeauducq
asmicon: skeleton
tree
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commitdiff
2012-02-24
Sebastien Bourdeauducq
ddrphy: working on hardware, simulation a bit messed up
tree
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commitdiff
2012-02-24
Sebastien Bourdeauducq
ddrphy: request wrdata_en/rddata_en at the same time...
tree
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commitdiff
2012-02-24
Sebastien Bourdeauducq
ddrphy: reads OK, write data coming out 1/2 cycle too...
tree
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commitdiff
2012-02-24
Sebastien Bourdeauducq
ddrphy: partly working
tree
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commitdiff
2012-02-21
Sebastien Bourdeauducq
s6ddrphy: read path OK in simulation
tree
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commitdiff
2012-02-20
Sebastien Bourdeauducq
s6ddrphy: write path OK in simulation
tree
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commitdiff
2012-02-20
Sebastien Bourdeauducq
s6ddrphy: generate DQ/DQS/DM OE
tree
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commitdiff
2012-02-20
Sebastien Bourdeauducq
s6ddrphy: DQ/DQS/DM SERDES
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commitdiff
2012-02-19
Sebastien Bourdeauducq
s6ddrphy: clock, address and command
tree
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commitdiff
2012-02-19
Sebastien Bourdeauducq
Prepare for new DDR PHY
tree
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commitdiff
2012-02-17
Sebastien Bourdeauducq
s6ddrphy: use single-ended DQS
tree
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commitdiff
2012-02-16
Sebastien Bourdeauducq
Generate all clocks for the DDR PHY
tree
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commitdiff
2012-02-14
Sebastien Bourdeauducq
s6ddrphy: prepare quilt
tree
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commitdiff
2012-02-06
Sebastien Bourdeauducq
LM32: make IP read-only and interrupt lines level-sensitive
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commitdiff
2011-12-17
Sebastien Bourdeauducq
uart: new design using FHDL and bank (TX only, incomplete)
tree
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commitdiff
2011-12-17
Sebastien Bourdeauducq
32-device, 8-bit CSR bus
tree
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commitdiff
2011-12-16
Sebastien Bourdeauducq
Proper reset generation
tree
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commitdiff
2011-12-13
Sebastien Bourdeauducq
Initial import
tree
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commitdiff