projects
/
litex.git
/ history
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
first ⋅ prev ⋅ next
lm32: remove unneeded parameter in lm32_dp_ram
[litex.git]
/
verilog
/
2012-11-14
Michael Walle
lm32: remove unneeded parameter in lm32_dp_ram
tree
|
commitdiff
2012-11-14
Michael Walle
lm32: rename mem array in lm32_dp_ram
tree
|
commitdiff
2012-11-14
Michael Walle
lm32: replace clogb2 by builtin $clog2
tree
|
commitdiff
2012-09-10
Sebastien Bourdeauducq
Define clock domains instead of passing extra clocks...
tree
|
commitdiff
2012-07-07
Sebastien Bourdeauducq
framebuffer: fix FIFO read clocking
tree
|
commitdiff
2012-07-01
Sebastien Bourdeauducq
framebuffer: FIFO
tree
|
commitdiff
2012-06-17
Sebastien Bourdeauducq
VGA framebuffer connections
tree
|
commitdiff
2012-05-24
Sebastien Bourdeauducq
Remove some boilerplate
tree
|
commitdiff
2012-05-19
Sebastien Bourdeauducq
Add Ethernet MAC
tree
|
commitdiff
2012-03-14
Sebastien Bourdeauducq
asmicon: skeleton
tree
|
commitdiff
2012-02-24
Sebastien Bourdeauducq
ddrphy: working on hardware, simulation a bit messed up
tree
|
commitdiff
2012-02-24
Sebastien Bourdeauducq
ddrphy: request wrdata_en/rddata_en at the same time...
tree
|
commitdiff
2012-02-24
Sebastien Bourdeauducq
ddrphy: reads OK, write data coming out 1/2 cycle too...
tree
|
commitdiff
2012-02-24
Sebastien Bourdeauducq
ddrphy: partly working
tree
|
commitdiff
2012-02-21
Sebastien Bourdeauducq
s6ddrphy: read path OK in simulation
tree
|
commitdiff
2012-02-20
Sebastien Bourdeauducq
s6ddrphy: write path OK in simulation
tree
|
commitdiff
2012-02-20
Sebastien Bourdeauducq
s6ddrphy: generate DQ/DQS/DM OE
tree
|
commitdiff
2012-02-20
Sebastien Bourdeauducq
s6ddrphy: DQ/DQS/DM SERDES
tree
|
commitdiff
2012-02-19
Sebastien Bourdeauducq
s6ddrphy: clock, address and command
tree
|
commitdiff
2012-02-19
Sebastien Bourdeauducq
Prepare for new DDR PHY
tree
|
commitdiff
2012-02-17
Sebastien Bourdeauducq
s6ddrphy: use single-ended DQS
tree
|
commitdiff
2012-02-16
Sebastien Bourdeauducq
Generate all clocks for the DDR PHY
tree
|
commitdiff
2012-02-14
Sebastien Bourdeauducq
s6ddrphy: prepare quilt
tree
|
commitdiff
2012-02-06
Sebastien Bourdeauducq
LM32: make IP read-only and interrupt lines level-sensitive
tree
|
commitdiff
2011-12-17
Sebastien Bourdeauducq
uart: new design using FHDL and bank (TX only, incomplete)
tree
|
commitdiff
2011-12-17
Sebastien Bourdeauducq
32-device, 8-bit CSR bus
tree
|
commitdiff
2011-12-16
Sebastien Bourdeauducq
Proper reset generation
tree
|
commitdiff
2011-12-13
Sebastien Bourdeauducq
Initial import
tree
|
commitdiff