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software/include/base/stdint.h: add INT32_C
[litex.git]
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verilog
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2012-12-01
Sebastien Bourdeauducq
Merge branch 'master' of github.com:milkymist/milkymist-ng
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commitdiff
2012-11-30
Michael Walle
lm32: fix watchpoints
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commitdiff
2012-11-14
Michael Walle
lm32: replace $clog2 with macro
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commitdiff
2012-11-14
Sebastien Bourdeauducq
lm32: split lm32_include.v
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commitdiff
2012-11-14
Michael Walle
lm32: fix documentation style
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commitdiff
2012-11-14
Michael Walle
lm32: remove unneeded parameter in lm32_dp_ram
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commitdiff
2012-11-14
Michael Walle
lm32: rename mem array in lm32_dp_ram
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commitdiff
2012-11-14
Michael Walle
lm32: replace clogb2 by builtin $clog2
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commitdiff
2012-09-10
Sebastien Bourdeauducq
Define clock domains instead of passing extra clocks...
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commitdiff
2012-07-07
Sebastien Bourdeauducq
framebuffer: fix FIFO read clocking
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commitdiff
2012-07-01
Sebastien Bourdeauducq
framebuffer: FIFO
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commitdiff
2012-06-17
Sebastien Bourdeauducq
VGA framebuffer connections
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commitdiff
2012-05-24
Sebastien Bourdeauducq
Remove some boilerplate
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commitdiff
2012-05-19
Sebastien Bourdeauducq
Add Ethernet MAC
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commitdiff
2012-03-14
Sebastien Bourdeauducq
asmicon: skeleton
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commitdiff
2012-02-24
Sebastien Bourdeauducq
ddrphy: working on hardware, simulation a bit messed up
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commitdiff
2012-02-24
Sebastien Bourdeauducq
ddrphy: request wrdata_en/rddata_en at the same time...
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commitdiff
2012-02-24
Sebastien Bourdeauducq
ddrphy: reads OK, write data coming out 1/2 cycle too...
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commitdiff
2012-02-24
Sebastien Bourdeauducq
ddrphy: partly working
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commitdiff
2012-02-21
Sebastien Bourdeauducq
s6ddrphy: read path OK in simulation
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commitdiff
2012-02-20
Sebastien Bourdeauducq
s6ddrphy: write path OK in simulation
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commitdiff
2012-02-20
Sebastien Bourdeauducq
s6ddrphy: generate DQ/DQS/DM OE
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commitdiff
2012-02-20
Sebastien Bourdeauducq
s6ddrphy: DQ/DQS/DM SERDES
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commitdiff
2012-02-19
Sebastien Bourdeauducq
s6ddrphy: clock, address and command
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commitdiff
2012-02-19
Sebastien Bourdeauducq
Prepare for new DDR PHY
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commitdiff
2012-02-17
Sebastien Bourdeauducq
s6ddrphy: use single-ended DQS
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commitdiff
2012-02-16
Sebastien Bourdeauducq
Generate all clocks for the DDR PHY
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commitdiff
2012-02-14
Sebastien Bourdeauducq
s6ddrphy: prepare quilt
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commitdiff
2012-02-06
Sebastien Bourdeauducq
LM32: make IP read-only and interrupt lines level-sensitive
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commitdiff
2011-12-17
Sebastien Bourdeauducq
uart: new design using FHDL and bank (TX only, incomplete)
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commitdiff
2011-12-17
Sebastien Bourdeauducq
32-device, 8-bit CSR bus
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commitdiff
2011-12-16
Sebastien Bourdeauducq
Proper reset generation
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commitdiff
2011-12-13
Sebastien Bourdeauducq
Initial import
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commitdiff