mesa.git
13 years agost/egl: add android backend
Chia-I Wu [Thu, 18 Aug 2011 02:28:29 +0000 (10:28 +0800)]
st/egl: add android backend

Both HW and SW rendering are supported for Android.  For SW rendering,
we use the generic gralloc lock/unlock for mapping and unmapping color
buffers (in winsys/android).

For HW rendering, we need to know the real type of color buffers.  This
backend works with drm_gralloc, where a color buffer is backed by a GEM
object.

13 years agowinsys/android: new SW winsys for Android
Chia-I Wu [Thu, 18 Aug 2011 02:17:10 +0000 (10:17 +0800)]
winsys/android: new SW winsys for Android

On Android, color buffers are passed between server and clients as
opaque buffer_handle_t.  This winsys makes use of gralloc, which
provides a generic way to map and unmap buffer_handle_t for CPU access.

13 years agoegl: add Android-specific extensions
Chia-I Wu [Fri, 1 Oct 2010 19:27:42 +0000 (15:27 -0400)]
egl: add Android-specific extensions

Add EGL_ANDROID_image_native_buffer and EGL_ANDROID_swap_rectangle.
There is no spec for them though.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Chad Versace <chad@chad-versace.us>
13 years agoegl: add _EGL_PLATFORM_ANDROID
Chia-I Wu [Mon, 11 Oct 2010 08:09:52 +0000 (16:09 +0800)]
egl: add _EGL_PLATFORM_ANDROID

This is Android Gingerbread platform.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Chad Versace <chad@chad-versace.us>
13 years agomesa: android has no log2f nor ffs
Chia-I Wu [Fri, 5 Aug 2011 03:54:05 +0000 (12:54 +0900)]
mesa: android has no log2f nor ffs

Define log2f(v) to be logf(v) / M_LN2 and ffs to __builtin_ffs.

Reviewed-by: Chad Versace <chad@chad-versace.us>
13 years agoralloc: include limits.h for SIZE_MAX on Android
Chia-I Wu [Fri, 5 Aug 2011 03:52:49 +0000 (12:52 +0900)]
ralloc: include limits.h for SIZE_MAX on Android

Android does not define SIZE_MAX in stdint.h.  We have to include
limits.h for it.

Reviewed-by: Chad Versace <chad@chad-versace.us>
13 years agogallium: add PIPE_OS_ANDROID support
Chia-I Wu [Fri, 5 Aug 2011 03:50:12 +0000 (12:50 +0900)]
gallium: add PIPE_OS_ANDROID support

Android uses Linux kernel and its own C runtime.  It resembles
PIPE_OS_LINUX a lot with some minor exceptions.

Reviewed-by: Brian Paul <brianp@vmware.com>
13 years agoglsl: remove an unnecessary header include
Chia-I Wu [Mon, 1 Aug 2011 02:14:18 +0000 (11:14 +0900)]
glsl: remove an unnecessary header include

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad@chad-versace.us>
13 years agomesa: fix !FEATURE_GL build
Chia-I Wu [Fri, 8 Apr 2011 14:50:43 +0000 (22:50 +0800)]
mesa: fix !FEATURE_GL build

Move vbo_exec_FlushVertices_internal out of FEATURE_beginend.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Chad Versace <chad@chad-versace.us>
13 years agoi965/gen7: Use align1 mode to set URB_WRITE_HWORD channel enables.
Kenneth Graunke [Thu, 18 Aug 2011 09:15:56 +0000 (02:15 -0700)]
i965/gen7: Use align1 mode to set URB_WRITE_HWORD channel enables.

Makes the new vertex shader backend work on Ivybridge.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
13 years agoi965/fs: Don't double-convert integer/boolean uniforms.
Kenneth Graunke [Thu, 11 Aug 2011 23:42:01 +0000 (16:42 -0700)]
i965/fs: Don't double-convert integer/boolean uniforms.

When ctx->Const.NativeIntegers is set, Core Mesa loads integer/boolean
uniforms directly, rather than loading the floating point equivalent.
So, when that's set, we don't need to perform any conversions.

Unfortunately, we can't properly support native integers with the old
vertex shader backend, so this patch leaves them disabled for now.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
13 years agomesa, glsl_to_tgsi: Add new gl_context::NativeIntegers flag.
Kenneth Graunke [Mon, 15 Aug 2011 21:18:16 +0000 (14:18 -0700)]
mesa, glsl_to_tgsi: Add new gl_context::NativeIntegers flag.

Previously, native integer support was based on whether the driver
advertised GLSL 1.30 or not.  However, drivers that natively support
integers may wish to do so for older GLSL versions as well.  Adding this
new opt-in flag allows them to do so.

Currently disabled by default on all drivers, which was the existing
behavior (no drivers currently implement GLSL 1.30).

Fixes piglit tests on i965 with INTEL_GLSL_VERSION=130 set:
- spec/glsl-1.10/fs-uniform-int-110.shader_test
- spec/glsl-1.30/fs-uniform-int-130.shader_test
(it was doubly converting the data)

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
13 years agoir_to_mesa: Remove incorrect usage of the 'struct' keyword on classes.
Kenneth Graunke [Thu, 18 Aug 2011 21:08:06 +0000 (14:08 -0700)]
ir_to_mesa: Remove incorrect usage of the 'struct' keyword on classes.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
13 years agoi965/fs: Change incorrect use of 'struct fs_reg' to simply 'fs_reg'.
Kenneth Graunke [Thu, 18 Aug 2011 21:05:11 +0000 (14:05 -0700)]
i965/fs: Change incorrect use of 'struct fs_reg' to simply 'fs_reg'.

It's actually a class.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
13 years agoglsl: Remove unused variable.
Kenneth Graunke [Thu, 18 Aug 2011 21:03:26 +0000 (14:03 -0700)]
glsl: Remove unused variable.

13 years agoi965/vs: Implement proper register allocation instead of 1:1 mapping.
Eric Anholt [Tue, 16 Aug 2011 22:28:53 +0000 (15:28 -0700)]
i965/vs: Implement proper register allocation instead of 1:1 mapping.

Fixes vs-atan-* and several others.  This is not the real solution we
eventually want, which will pack floats, vec2s, and vec3s into vec4
registers, but this code should provide the framework for that.

13 years agoi965/vs: Add simple dead code elimination.
Eric Anholt [Wed, 17 Aug 2011 17:50:17 +0000 (10:50 -0700)]
i965/vs: Add simple dead code elimination.

This is copied right from the fragment shader.  It is needed for real
register allocation to work correctly.

13 years agoi965/vs: Copy the live intervals calculation over from the FS.
Eric Anholt [Tue, 16 Aug 2011 22:09:48 +0000 (15:09 -0700)]
i965/vs: Copy the live intervals calculation over from the FS.

This is a rather pessimistic calculation, since it doesn't distinguish
individual channels of a vec4, or elements of an array, but should be
a minimum start for register allocation.

13 years agoi965/vs: Remove stale comment about compressed instructions.
Eric Anholt [Tue, 16 Aug 2011 21:18:51 +0000 (14:18 -0700)]
i965/vs: Remove stale comment about compressed instructions.

This was copy'n'paste from the fragment shader, and didn't make sense
here.

13 years agor600g: don't allocate separate depth and stencil for transfer textures on EG
Marek Olšák [Fri, 19 Aug 2011 20:57:56 +0000 (22:57 +0200)]
r600g: don't allocate separate depth and stencil for transfer textures on EG

The state tracker expects depth and stencil pixels interleaved.
Evergreen can bind an interleaved depth-stencil resource as a colorbuffer,
but not as a zbuffer.

The hardware can do the interleaving for us when decompressing.

13 years agor600g: finally enable float depth buffers on evergreen
Marek Olšák [Fri, 19 Aug 2011 20:43:08 +0000 (22:43 +0200)]
r600g: finally enable float depth buffers on evergreen

13 years agor600g: rename resource -> view in create_sampler_view
Marek Olšák [Fri, 19 Aug 2011 20:27:00 +0000 (22:27 +0200)]
r600g: rename resource -> view in create_sampler_view

The sampler view is not a resource.
Also remove the unused desc variable.

13 years agor600g: hack around a problem with texture alignment
Marek Olšák [Fri, 19 Aug 2011 19:48:12 +0000 (21:48 +0200)]
r600g: hack around a problem with texture alignment

13 years agor600g: simplify the conditionals determining array mode
Marek Olšák [Fri, 19 Aug 2011 17:26:08 +0000 (19:26 +0200)]
r600g: simplify the conditionals determining array mode

13 years agor600g: put depth and stencil into one backing buffer
Marek Olšák [Fri, 19 Aug 2011 17:21:40 +0000 (19:21 +0200)]
r600g: put depth and stencil into one backing buffer

For DRI2 sharing.

13 years agor600g: fix depth-stencil on evergreen
Marek Olšák [Thu, 18 Aug 2011 23:07:46 +0000 (01:07 +0200)]
r600g: fix depth-stencil on evergreen

Such that it actually works in apps which use both.

A separate buffer is allocated for stencil. The only exception is
the window-system-provided depth-stencil buffer, where depth and stencil
share the same buffer.

This fixes:
- fbo-depthstencil-GL_DEPTH24_STENCIL8-clear
- fbo-depthstencil-GL_DEPTH24_STENCIL8-drawpixels-FLOAT-and-USHORT
- fbo-depthstencil-GL_DEPTH24_STENCIL8-readpixels-24_8
- fbo-depthstencil-GL_DEPTH24_STENCIL8-readpixels-FLOAT-and-USHORT

13 years agomesa: handle array textures in GenerateMipmap(), FramebufferTexture1/2D()
Brian Paul [Thu, 18 Aug 2011 21:59:33 +0000 (15:59 -0600)]
mesa: handle array textures in GenerateMipmap(), FramebufferTexture1/2D()

This was an unfinished to-do item before.
With this patch and the two preceeding patches, piglit's
fbo-generatemipmap-array test runs and passes instead of generating
a GL error and dying on an assertion.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
13 years agometa: use fallback mipmap generation for 1D/2D texture arrays
Brian Paul [Thu, 18 Aug 2011 21:58:00 +0000 (15:58 -0600)]
meta: use fallback mipmap generation for 1D/2D texture arrays

We could do 1D/2D arrays with textured quad rendering, but it'll take
some work (as with 3D textures).

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
13 years agomesa: set Q=1 for OPCODE_TEX execution
Brian Paul [Thu, 18 Aug 2011 21:54:53 +0000 (15:54 -0600)]
mesa: set Q=1 for OPCODE_TEX execution

Q should not be significant for OPCODE_TEX, but it winds up getting
passed to the compute_lambda() function.  Make sure it's 1.0 to
prevent garbage values, which is effectively what we get when the
swizzle is coord.xyzz (which is what GLSL gives us).

Part of the fix for piglit's fbo-generatemipmap-array test.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
13 years agomesa: restructure error checking in _mesa_FramebufferTexture1D/2DEXT()
Brian Paul [Thu, 18 Aug 2011 20:35:27 +0000 (14:35 -0600)]
mesa: restructure error checking in _mesa_FramebufferTexture1D/2DEXT()

In anticipation of adding more texture targets.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
13 years agomesa: Declare _mesa_meta_begin()/end() as public
Chad Versace [Fri, 12 Aug 2011 23:50:27 +0000 (16:50 -0700)]
mesa: Declare _mesa_meta_begin()/end() as public

Declare _mesa_meta_begin()/end() in meta.h so that drivers can write
custom meta-ops (such as HiZ resolves for i965).

This necessitates moving the the META_* macros into meta.h. To prevent
naming collisions, this commit renames each macro to be MESA_META_*.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Chad Versace <chad@chad-versace.us>
13 years agonv50: fix potential null deref in insn modifer optimization pass
Christoph Bumiller [Fri, 19 Aug 2011 14:57:30 +0000 (16:57 +0200)]
nv50: fix potential null deref in insn modifer optimization pass

Bug introduced in 34980cd153050111edc545545ddff11f5b68347e.

13 years agoglx: use a block to fix declarations after code warning
Brian Paul [Fri, 19 Aug 2011 14:36:22 +0000 (08:36 -0600)]
glx: use a block to fix declarations after code warning

13 years agor600g: fix a possible crash in r600_adjust_gprs
Marek Olšák [Thu, 18 Aug 2011 20:59:22 +0000 (22:59 +0200)]
r600g: fix a possible crash in r600_adjust_gprs

13 years agomesa: fix incorrect error code in _mesa_FramebufferTexture1D/3DEXT()
Brian Paul [Thu, 18 Aug 2011 17:51:48 +0000 (11:51 -0600)]
mesa: fix incorrect error code in _mesa_FramebufferTexture1D/3DEXT()

The spec says GL_INVALID_OPERATION is generated when texture!=0 and
textarget is not a legal value.  We had this right for the 2D function.

13 years agoglapi: update .gitignore for generated ES dispatch headers
Paul Berry [Tue, 16 Aug 2011 17:23:52 +0000 (10:23 -0700)]
glapi: update .gitignore for generated ES dispatch headers

Commit 6eff33dc (glapi: generate ES dispatch headers from core mesa)
replaced the autogenerated files
src/mapi/es1api/main/{dispatch,remap_helper}.h with new autogenerated
files src/mesa/main/api_exec_es{1,2}_{dispatch,remap_helper}.h.  This
patch updates the .gitignore files to properly ignore the new
autogenerated files, and stop ignoring the old autogenerated files.

Reviewed-by: Chia-I Wu <olv@lunarg.com>
13 years agollvmpipe: Don't build lp_test_arit on MSVC.
José Fonseca [Thu, 18 Aug 2011 17:04:44 +0000 (18:04 +0100)]
llvmpipe: Don't build lp_test_arit on MSVC.

Several issues due to expf/logf/etc either not being declared,
or being defined as a macro.

13 years agollvmpipe: snprintf->util_snprintf.
José Fonseca [Thu, 18 Aug 2011 16:58:02 +0000 (17:58 +0100)]
llvmpipe: snprintf->util_snprintf.

For MSVC.

13 years agollvmpipe: Add u_math.h include.
José Fonseca [Thu, 18 Aug 2011 15:06:00 +0000 (16:06 +0100)]
llvmpipe: Add u_math.h include.

Necessary on platforms with incomplete math.h

13 years agoscons: Add support for LLVM-2.9 on Windows.
José Fonseca [Thu, 18 Aug 2011 15:00:03 +0000 (16:00 +0100)]
scons: Add support for LLVM-2.9 on Windows.

MinGW & MSVC, although I've only tested the former.

13 years agoglx: Don't flush twice if we fallback to dri2CopySubBuffer
Kristian Høgsberg [Thu, 18 Aug 2011 12:46:02 +0000 (08:46 -0400)]
glx: Don't flush twice if we fallback to dri2CopySubBuffer

The flush extensions flush call indicates end of frame and should only
be called once per frame.  However, in the dri2SwapBuffer fallback
path, we call flush and then call dri2CopySubBuffer, which also calls
flush.  Refactor the code to only call flush once.

13 years agor600g: implement NV_primitive_restart functionality (v2)
Marek Olšák [Tue, 16 Aug 2011 07:47:16 +0000 (09:47 +0200)]
r600g: implement NV_primitive_restart functionality (v2)

Needed for GL3.

v2: evergreen support

I don't set PA_SU_SC_MODE_CNTL.MULTI_PRIM_IB_ENA.
piglit/primitive-restart does pass though. Tested on RV730 and EG-REDWOOD.

13 years agor600g: fix scons build
Marek Olšák [Wed, 17 Aug 2011 20:53:10 +0000 (22:53 +0200)]
r600g: fix scons build

13 years agoi965/fs: Fix 32-bit integer multiplication.
Eric Anholt [Tue, 16 Aug 2011 05:36:18 +0000 (22:36 -0700)]
i965/fs: Fix 32-bit integer multiplication.

The MUL opcode does a 16bit * 32bit multiply, and we need to do the
MACH to get the top 16bit * 32bit added in.

Fixes fs-op-mult-int-*, fs-op-mult-ivec*

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
13 years agonv50: don't drop flags definition when merging SAT with ADD/MAD
Christoph Bumiller [Wed, 17 Aug 2011 18:38:40 +0000 (20:38 +0200)]
nv50: don't drop flags definition when merging SAT with ADD/MAD

13 years agost/mesa: fix incorrect loop over instruction src regs
Brian Paul [Tue, 16 Aug 2011 22:30:52 +0000 (16:30 -0600)]
st/mesa: fix incorrect loop over instruction src regs

The array of src regs is of size 3, not 4.

13 years agost/dri: Indent driconf options
Lauri Kasanen [Fri, 1 Jul 2011 09:57:06 +0000 (12:57 +0300)]
st/dri: Indent driconf options

13 years agoxmlpool.h: fix a typo
Lauri Kasanen [Fri, 1 Jul 2011 10:01:00 +0000 (13:01 +0300)]
xmlpool.h: fix a typo

13 years agoxmlconfig: Make the error message more informative
Lauri Kasanen [Fri, 1 Jul 2011 10:49:18 +0000 (13:49 +0300)]
xmlconfig: Make the error message more informative

13 years agomesa: Bump instruction execution limit to 65536
Ian Romanick [Thu, 4 Aug 2011 00:12:29 +0000 (17:12 -0700)]
mesa: Bump instruction execution limit to 65536

Shader Model 3.0[1] requires that shaders be able to execute at least
65536 instructions.  Bump Mesa maxExec to that limit.  This allows
several vertex shaders in the OpenGL ES 2.0 conformance test suite to
run to completion.

1: http://en.wikipedia.org/wiki/High_Level_Shader_Language

Reviewed-by: Eric Anholt <eric@anholt.net>
13 years agomesa: Add partial constant propagation pass for Mesa IR
Ian Romanick [Thu, 10 Feb 2011 23:48:27 +0000 (15:48 -0800)]
mesa: Add partial constant propagation pass for Mesa IR

This cleans up some code generated by the IR-to-Mesa pass for i915.
In particular, some shaders involving arrays of constant matrices
result in really bad code.

v2: Silence several warnings from merging the gl_constant_value work.
Fix DP[23] folding.  Add support for a bunch more opcodes that appear
in piglit runs on i915.

Reviewed-by: Eric Anholt <eric@anholt.net>
13 years agoir_to_mesa: Emit a MAD(b, -a, b) for !a && b
Ian Romanick [Tue, 2 Aug 2011 19:17:20 +0000 (12:17 -0700)]
ir_to_mesa: Emit a MAD(b, -a, b) for !a && b

!a && b occurs frequently when nexted if-statements have been
flattened.  It should also be possible use a MAD for (a && b) || c,
though that would require a MAD_SAT.

Reviewed-by: Eric Anholt <eric@anholt.net>
13 years agoir_to_mesa: Implement ir_binop_all_equal using DP4 w/SGE
Ian Romanick [Wed, 3 Aug 2011 22:42:05 +0000 (15:42 -0700)]
ir_to_mesa: Implement ir_binop_all_equal using DP4 w/SGE

The operation ir_binop_all_equal is !(a.x != b.x || a.y != b.y || a.z
!= b.z || a.w != b.w).  Logical-or is implemented using addition
(followed by clampling to [0,1]) on values of 0.0 and 1.0.  Replacing
the logical-or operators with addition gives !bool((int(a.x != b.x) +
int(a.y == b.y) + int(a.z == b.z) + int(a.w == b.w)).  This can be
implemented using a dot-product with a vector of all 1.0.  After the
dot-product, the value will be an integer on the range [0,4].

Previously a SEQ instruction was used to clamp the resulting logic
value to [0,1] and invert the result.  Using an SGE instruction on the
negation of the dot-product result has the same effect.  Many older
shader architectures do not support the SEQ instruction.  It must be
emulated using two SGE instructions and a MUL.  On these
architectures, the single SGE saves two instructions.

Reviewed-by: Eric Anholt <eric@anholt.net>
13 years agoir_to_mesa: Implement ir_binop_any_nequal using DP4 w/saturate or DP4 w/SLT
Ian Romanick [Wed, 3 Aug 2011 22:35:01 +0000 (15:35 -0700)]
ir_to_mesa: Implement ir_binop_any_nequal using DP4 w/saturate or DP4 w/SLT

The operation ir_binop_any_nequal is (a.x != b.x) || (a.y != b.y) ||
(a.z != b.z) || (a.w != b.w), and that is the same as any(bvec4(a.x !=
b.x, a.y != b.y, a.z != b.z, a.w != b.w)).  Implement the any() part
the same way the regular ir_unop_any is implemented.

Reviewed-by: Eric Anholt <eric@anholt.net>
13 years agoir_to_mesa: Implement ir_unop_any using DP4 w/saturate or DP4 w/SLT
Ian Romanick [Wed, 3 Aug 2011 22:27:43 +0000 (15:27 -0700)]
ir_to_mesa: Implement ir_unop_any using DP4 w/saturate or DP4 w/SLT

This is just like the ir_binop_logic_or case.  The operation
ir_unop_any is (a.x || a.y || a.z || a.w).  Logical-or is implemented
using addition (followed by clampling to [0,1]) on values of 0.0 and
1.0.  Replacing the logical-or operators with addition gives (a.x +
a.y + a.z + a.w).  This can be implemented using a dot-product with a
vector of all 1.0.

Previously a SNE instruction was used to clamp the resulting logic
value to [0,1].  In a fragment shader, using a saturate on the
dot-product has the same effect.  Adding the saturate to the
dot-product is free, so (at least) one instruction is saved.

In a vertex shader, using an SLT on the negation of the dot-product
result has the same effect.  Many older shader architectures do not
support the SNE instruction.  It must be emulated using two SLT
instructions and an ADD.  On these architectures, the single SLT saves
two instructions.

Reviewed-by: Eric Anholt <eric@anholt.net>
13 years agoir_to_mesa: Make ir_to_mesa_visitor::emit_dp return the instruction
Ian Romanick [Sat, 30 Jul 2011 17:45:35 +0000 (10:45 -0700)]
ir_to_mesa: Make ir_to_mesa_visitor::emit_dp return the instruction

Reviewed-by: Eric Anholt <eric@anholt.net>
13 years agoir_to_mesa: Implement ir_binop_logic_or using an add w/saturate or add w/SLT
Ian Romanick [Sat, 30 Jul 2011 17:49:49 +0000 (10:49 -0700)]
ir_to_mesa: Implement ir_binop_logic_or using an add w/saturate or add w/SLT

Logical-or is implemented using addition (followed by clampling to
[0,1]) on values of 0.0 and 1.0.  Replacing the logical-or operators
with addition gives a + b which has a result on the range [0, 2].

Previously a SNE instruction was used to clamp the resulting logic
value to [0,1].  In a fragment shader, using a saturate on the add has
the same effect.  Adding the saturate to the add is free, so (at
least) one instruction is saved.

In a vertex shader, using an SLT on the negation of the add result has
the same effect.  Many older shader architectures do not support the
SNE instruction.  It must be emulated using two SLT instructions and
an ADD.  On these architectures, the single SLT saves two
instructions.

Reviewed-by: Eric Anholt <eric@anholt.net>
13 years agoir_to_mesa: Implement ir_unop_logic_not using 1-x
Ian Romanick [Sat, 30 Jul 2011 17:48:10 +0000 (10:48 -0700)]
ir_to_mesa: Implement ir_unop_logic_not using 1-x

Since our logic values are 0.0 (false) and 1.0 (true), 1.0 - x
accurately implements logical not.

Reviewed-by: Eric Anholt <eric@anholt.net>
13 years agomesa: Add Android to list of platforms that define fpclassify()
Chad Versace [Mon, 15 Aug 2011 20:29:15 +0000 (13:29 -0700)]
mesa: Add Android to list of platforms that define fpclassify()

This is a fix for the Android build.

Signed-off-by: Chad Versace <chad@chad-versace.us>
13 years agomesa: Fix Android build by #ifdef'ing out locale support
Chad Versace [Mon, 15 Aug 2011 20:26:21 +0000 (13:26 -0700)]
mesa: Fix Android build by #ifdef'ing out locale support

Bionic does not support locales. This commit #ifdef's out the locale usage
in _mesa_strtof().

Signed-off-by: Chad Versace <chad@chad-versace.us>
13 years agomesa: Remove use of fpu_control.h
Chad Versace [Mon, 15 Aug 2011 17:58:25 +0000 (10:58 -0700)]
mesa: Remove use of fpu_control.h

Remove the inclusion of fpu_control.h from compiler.h.  Since Bionic lacks
fpu_control.h, this fixes the Android build.

Also remove the sole use of the fpu_control bits, which was in debug.c.
Those were brianp's debug bits, and he approved of their removal.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad@chad-versace.us>
13 years agoi965/vs: Fix multiplies to actually do 32-bit multiplies.
Eric Anholt [Tue, 16 Aug 2011 04:02:10 +0000 (21:02 -0700)]
i965/vs: Fix multiplies to actually do 32-bit multiplies.

Fixes vs-op-mult-int-int and friends.

13 years agoi965/vs: Add support for conversion of FIXED_HW_REG src_reg to/from dst_reg.
Eric Anholt [Tue, 16 Aug 2011 03:59:24 +0000 (20:59 -0700)]
i965/vs: Add support for conversion of FIXED_HW_REG src_reg to/from dst_reg.

This was quietly occurring in some emit code I produced, and failed.

13 years agoi965/vs: Fix memory leak of ralloc context for the visitor.
Eric Anholt [Tue, 16 Aug 2011 03:43:42 +0000 (20:43 -0700)]
i965/vs: Fix memory leak of ralloc context for the visitor.

13 years agoi965/vs: Fix condition code for scalar expression all_equals.
Eric Anholt [Tue, 16 Aug 2011 03:13:53 +0000 (20:13 -0700)]
i965/vs: Fix condition code for scalar expression all_equals.

Fixes vs-op-eq-bool-bool.

13 years agoi965/vs: Don't assertion fail on vertex texturing.
Eric Anholt [Fri, 12 Aug 2011 12:32:25 +0000 (05:32 -0700)]
i965/vs: Don't assertion fail on vertex texturing.

The linker will reject the program, but we need to survive until then.
Fixes abort in glsl1-2D Texture lookup with explicit lod (Vertex
shader)

13 years agoi965/gen6: Force WHILE exec size to 8.
Eric Anholt [Fri, 12 Aug 2011 12:28:53 +0000 (05:28 -0700)]
i965/gen6: Force WHILE exec size to 8.

We can't just look at the instruction that happens to appear at the
start of the loop, because it might be some other exec size and cause
us to only loop on the first N channels.  We always want 8 in our
current code (since 16 doesn't work so we don't do 16-wide fragment in
that case).

Fixes loop-03.vert, which was triggering the assertions.

13 years agoi965/vs: Remove remaining use of foreach_iter.
Eric Anholt [Fri, 12 Aug 2011 12:15:50 +0000 (05:15 -0700)]
i965/vs: Remove remaining use of foreach_iter.

13 years agoi965/vs: Fix abs/negate handling on attributes.
Eric Anholt [Thu, 11 Aug 2011 23:27:41 +0000 (16:27 -0700)]
i965/vs: Fix abs/negate handling on attributes.

Fixes glsl-vs-neg-attribute and glsl-vs-abs-attribute.

13 years agoi965/vs: Avoid generating a MOV for most ir_assignment handling.
Eric Anholt [Thu, 11 Aug 2011 15:09:10 +0000 (08:09 -0700)]
i965/vs: Avoid generating a MOV for most ir_assignment handling.

Removes an average of 11.5% of instructions in 54% of vertex shaders
in shader-db.

13 years agoi965/vs: Run the shader backend at link time and return compile failures.
Eric Anholt [Thu, 11 Aug 2011 16:52:08 +0000 (09:52 -0700)]
i965/vs: Run the shader backend at link time and return compile failures.

Link failure is something that shouldn't happen, but we sometimes want
it during development.  The precompile also allows analysis of shader
codegen with shader-db.

13 years agoi965: Fix assertion failure on a loop consisting of while (true) { break }.
Eric Anholt [Tue, 16 Aug 2011 01:40:14 +0000 (18:40 -0700)]
i965: Fix assertion failure on a loop consisting of while (true) { break }.

On enabling the precompile step in the VS, we tripped over this
assertion failure in glsl-link-bug-30552.

13 years agoi965/vs: Fix the trivial register allocator's failure path.
Eric Anholt [Thu, 11 Aug 2011 16:17:18 +0000 (09:17 -0700)]
i965/vs: Fix the trivial register allocator's failure path.

13 years agoi965/vs: Add support for if(any(bvec)) on gen6.
Eric Anholt [Wed, 10 Aug 2011 21:13:23 +0000 (14:13 -0700)]
i965/vs: Add support for if(any(bvec)) on gen6.

13 years agoi965/vs: Add support for GL_FIXED attributes.
Eric Anholt [Wed, 10 Aug 2011 18:38:42 +0000 (11:38 -0700)]
i965/vs: Add support for GL_FIXED attributes.

Fixes arb_es2_compatibility-fixed-type

13 years agoi965/vs: Clamp vertex color outputs when required by ARB_color_buffer_float.
Eric Anholt [Tue, 9 Aug 2011 22:19:26 +0000 (15:19 -0700)]
i965/vs: Clamp vertex color outputs when required by ARB_color_buffer_float.

Fixes glsl-vs-vertex-color.

13 years agoi965/vs: Fix access of attribute arrays.
Eric Anholt [Tue, 9 Aug 2011 22:08:47 +0000 (15:08 -0700)]
i965/vs: Fix access of attribute arrays.

By leaving out the column index, we were reading an unallocated
attribute on glsl-mat-attribute.

13 years agoi965/vs: Fix builtin uniform setup.
Eric Anholt [Tue, 9 Aug 2011 21:49:29 +0000 (14:49 -0700)]
i965/vs: Fix builtin uniform setup.

I want to intelligently pack them at some point, but for now we have
the params set up in groups of 4.  Fixes glsl-vs-normalscale.

13 years agoi965/vs: Add support for loops.
Eric Anholt [Tue, 9 Aug 2011 21:35:38 +0000 (14:35 -0700)]
i965/vs: Add support for loops.

This is copied from brw_fs.cpp, instead of doing the temporary IR
generation that ir_to_mesa does.  Fixes glsl-vs-loop and friends.

13 years agoi965/vs: Add support for ir_binop_pow.
Eric Anholt [Tue, 9 Aug 2011 19:30:41 +0000 (12:30 -0700)]
i965/vs: Add support for ir_binop_pow.

Fixes vs-pow-float-float.

13 years agoi965/vs: Respect the gen6 limitation that math opcodes can't be align16.
Eric Anholt [Tue, 9 Aug 2011 18:00:28 +0000 (11:00 -0700)]
i965/vs: Respect the gen6 limitation that math opcodes can't be align16.

Fixes vs-acos-vec3 and friends.

13 years agoi965/vs: Fix implementation of ir_unop_any.
Eric Anholt [Tue, 9 Aug 2011 17:57:09 +0000 (10:57 -0700)]
i965/vs: Fix implementation of ir_unop_any.

We were inheriting whatever previous predicate existed.

13 years agoi965/vs: Slightly improve the trivial reg allocator to skip unused regs.
Eric Anholt [Mon, 8 Aug 2011 22:56:11 +0000 (15:56 -0700)]
i965/vs: Slightly improve the trivial reg allocator to skip unused regs.

This fixes most of the regressions in the vs array test set from the
varying array indexing work, since the giant array that was originally
allocated in virtual GRF space never gets used and is only ever
read/stored from scratch space.

13 years agoi965: Add gen6 disassembly for DP render cache messages.
Eric Anholt [Mon, 8 Aug 2011 00:09:12 +0000 (17:09 -0700)]
i965: Add gen6 disassembly for DP render cache messages.

13 years agoi965/vs: Enable variable array indexing in the VS.
Eric Anholt [Sun, 7 Aug 2011 20:38:50 +0000 (13:38 -0700)]
i965/vs: Enable variable array indexing in the VS.

13 years agoi965/vs: Add support for scratch read/write codegen.
Eric Anholt [Sun, 7 Aug 2011 20:36:11 +0000 (13:36 -0700)]
i965/vs: Add support for scratch read/write codegen.

13 years agoi965: Make some EU emit code for DP read/write messages non-static.
Eric Anholt [Sun, 7 Aug 2011 20:16:06 +0000 (13:16 -0700)]
i965: Make some EU emit code for DP read/write messages non-static.

We keep building these strange interfaces for DP read/write where
there's a helper function with some partially-specific,
partially-general controls, which is used in exactly one place in code
generation.  Making these public will let us set up those instructions
in the one place they're to be generated.

13 years agoi965/vs: Move virtual GRFs with array accesses to them to scratch space.
Eric Anholt [Sun, 7 Aug 2011 19:15:26 +0000 (12:15 -0700)]
i965/vs: Move virtual GRFs with array accesses to them to scratch space.

13 years agoi965/vs: Reserve MRF 14/15 for array loads/register unspilling.
Eric Anholt [Sun, 7 Aug 2011 22:21:25 +0000 (15:21 -0700)]
i965/vs: Reserve MRF 14/15 for array loads/register unspilling.

13 years agoi965/vs: Track the variable index of array accesses.
Eric Anholt [Sun, 7 Aug 2011 17:59:39 +0000 (10:59 -0700)]
i965/vs: Track the variable index of array accesses.

This isn't used currently, as we lower all array accesses.

13 years agoi965: Add remaining scratch space setup emit to unit states.
Eric Anholt [Sun, 7 Aug 2011 17:47:54 +0000 (10:47 -0700)]
i965: Add remaining scratch space setup emit to unit states.

13 years agoi965: Set up allocation of a VS scratch space if required.
Eric Anholt [Sun, 7 Aug 2011 17:44:15 +0000 (10:44 -0700)]
i965: Set up allocation of a VS scratch space if required.

13 years agoi965: Remove dead brw->wm.max_threads field.
Eric Anholt [Sun, 7 Aug 2011 17:43:49 +0000 (10:43 -0700)]
i965: Remove dead brw->wm.max_threads field.

13 years agoi965/vs: Add support for VUEs larger than a single URB write.
Eric Anholt [Sat, 6 Aug 2011 04:53:00 +0000 (21:53 -0700)]
i965/vs: Add support for VUEs larger than a single URB write.

Fixes glsl-max-varyings.

13 years agoi965/vs: Avoid generating extra moves when setting up large ir_constants.
Eric Anholt [Sat, 6 Aug 2011 04:22:36 +0000 (21:22 -0700)]
i965/vs: Avoid generating extra moves when setting up large ir_constants.

We were also screwing up the types in the process, and just not
emitting moves was easier.

13 years agoi965/vs: Fix types of varying outputs.
Eric Anholt [Sat, 6 Aug 2011 03:54:25 +0000 (20:54 -0700)]
i965/vs: Fix types of varying outputs.

For structs/arrays/matrices, they were ending up as uint because we
forgot to set them.  All varyings in GLSL 1.20 are of base type float,
so just force the matter here (which gets inherited at
emit_urb_writes() time).

Fixes vs-varying-array-mat2-col-rd.

13 years agoi965/vs: Handle assignment of structures/arrays/matrices better.
Eric Anholt [Sat, 6 Aug 2011 03:46:03 +0000 (20:46 -0700)]
i965/vs: Handle assignment of structures/arrays/matrices better.

This gets the right types on the instructions, as well as emitting
minimal swizzles/writemasks.

13 years agoi965/vs: Don't forget to set up assignment condition code for arrays/structs.
Eric Anholt [Sat, 6 Aug 2011 03:26:48 +0000 (20:26 -0700)]
i965/vs: Don't forget to set up assignment condition code for arrays/structs.

Fixes vs-uniform-array-mat2-index-col-rd.

13 years agoi965/vs: Apply the gen6 math workaround for math1 instructions.
Eric Anholt [Sat, 6 Aug 2011 03:16:21 +0000 (20:16 -0700)]
i965/vs: Apply the gen6 math workaround for math1 instructions.

Fixes glsl-vs-masked-cos.

13 years agoi965/vs: Add support for if(any_nequal()) and if(all_equal()) on gen6.
Eric Anholt [Sat, 6 Aug 2011 03:03:31 +0000 (20:03 -0700)]
i965/vs: Add support for if(any_nequal()) and if(all_equal()) on gen6.

Fixes vs-temp-array-mat2-col-rd.shader_test.