Marek Olšák [Wed, 23 Nov 2016 01:41:14 +0000 (02:41 +0100)]
radeonsi/gfx9: don't generate LS and ES states
these shaders don't exist on GFX9
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 15 Oct 2016 12:38:59 +0000 (14:38 +0200)]
radeonsi/gfx9: SPI_SHADER_USER_DATA changes
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 23 Nov 2016 17:42:53 +0000 (18:42 +0100)]
winsys/amdgpu: set/get BO tiling flags for GFX9
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 27 Oct 2016 15:33:42 +0000 (17:33 +0200)]
radeonsi/gfx9: handle pitch and offset overrides for texture_from_handle
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 6 Nov 2016 14:46:26 +0000 (15:46 +0100)]
radeonsi/gfx9: set/validate GFX9 BO metadata
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 15 Feb 2017 23:11:58 +0000 (00:11 +0100)]
radeonsi/gfx9: add radeon_surf.gfx9.surf_offset
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 15 Oct 2016 13:27:57 +0000 (15:27 +0200)]
radeonsi/gfx9: don't write mipmap level offsets to BO metadata
GFX9 doesn't have (usable) mipmap offsets.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 15 Oct 2016 14:21:20 +0000 (16:21 +0200)]
radeonsi/gfx9: flush CB & DB caches with an EOP TS event
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 15 Oct 2016 14:09:26 +0000 (16:09 +0200)]
radeonsi/gfx9: use ACQUIRE_MEM
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 6 Nov 2016 19:22:12 +0000 (20:22 +0100)]
radeonsi/gfx9: only use CE RAM for most-used descriptors
because the CE RAM size decreased to 4 KB.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 6 Nov 2016 18:27:09 +0000 (19:27 +0100)]
radeonsi/gfx9: emit FLUSH_DFSM where required
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 6 Nov 2016 18:25:12 +0000 (19:25 +0100)]
radeonsi/gfx9: emit BREAK_BATCH in emit_framebuffer_state
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 30 Jan 2017 23:56:34 +0000 (00:56 +0100)]
radeonsi/gfx9: fix MIP0_WIDTH & MIP0_HEIGHT for compressed texture blits
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 31 Jan 2017 20:02:19 +0000 (21:02 +0100)]
radeonsi/gfx9: fix textureSize/imageSize for 1D textures
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 24 Jan 2017 20:39:42 +0000 (21:39 +0100)]
radeonsi/gfx9: add a workaround for 1D depth textures
The same workaround is used by Vulkan.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 31 Jan 2017 21:56:38 +0000 (22:56 +0100)]
radeonsi/gfx9: enable clamping for Z UNORM formats promoted to Z32F
so that shaders don't have to do it.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 15 Oct 2016 13:27:18 +0000 (15:27 +0200)]
radeonsi/gfx9: image descriptor changes in mutable fields
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 15 Oct 2016 13:25:44 +0000 (15:25 +0200)]
radeonsi/gfx9: FMASK image descriptor changes
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 15 Oct 2016 13:24:45 +0000 (15:24 +0200)]
radeonsi/gfx9: image descriptor changes in immutable fields
The border color swizzle logic was copied from Vulkan. It doesn't make any
sense to me, but it passes all piglits except the stencil ones.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 15 Oct 2016 13:22:34 +0000 (15:22 +0200)]
radeonsi/gfx9: DB changes
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 15 Oct 2016 13:09:47 +0000 (15:09 +0200)]
radeonsi/gfx9: CB changes
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 27 Oct 2016 21:48:44 +0000 (23:48 +0200)]
radeonsi/gfx9: do DCC clears on non-mipmapped textures only
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 27 Oct 2016 18:45:15 +0000 (20:45 +0200)]
radeonsi/gfx9: update can_sample_z/s flags
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 27 Oct 2016 18:25:37 +0000 (20:25 +0200)]
radeonsi/gfx9: pass correct parameters to buffer_get_handle
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 26 Oct 2016 22:13:50 +0000 (00:13 +0200)]
radeonsi/gfx9: update si_set_optimal_micro_tile_mode
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 6 Nov 2016 21:31:49 +0000 (22:31 +0100)]
radeonsi/gfx9: don't check array_mode for allowing TC-compatible HTILE
GFX9 supports this with all modes except linear.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 24 Oct 2016 00:34:04 +0000 (02:34 +0200)]
radeonsi/gfx9: update HTILE/CMASK/FMASK allocators
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 26 Oct 2016 14:44:06 +0000 (16:44 +0200)]
radeonsi/gfx9: stub testdma - array_mode_to_string
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 6 Nov 2016 15:40:28 +0000 (16:40 +0100)]
radeonsi/gfx9: update r600_print_texture_info
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 6 Nov 2016 13:51:57 +0000 (14:51 +0100)]
gallium/radeon: move pre-GFX9 radeon_bo_metadata.* to u.legacy.*
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 12 Jan 2017 01:47:05 +0000 (02:47 +0100)]
winsys/amdgpu: set num_tile_pipes, pipe_interleave_bytes for GFX9
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 24 Oct 2016 10:30:17 +0000 (12:30 +0200)]
winsys/amdgpu: wire up new addrlib for GFX9
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 21 Oct 2016 11:31:40 +0000 (13:31 +0200)]
winsys/amdgpu: update amdgpu_addr_create for GFX9
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 20 Oct 2016 20:14:04 +0000 (22:14 +0200)]
winsys/amdgpu: rename GFX6 surface functions
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 23 Oct 2016 14:45:14 +0000 (16:45 +0200)]
gallium/radeon: add GFX9 surface info to radeon_surf
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 23 Oct 2016 11:08:46 +0000 (13:08 +0200)]
gallium/radeon: move pre-GFX9 radeon_surf.* members to radeon_surf.u.legacy.*
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 15 Oct 2016 13:06:01 +0000 (15:06 +0200)]
radeonsi/gfx9: allow Z16_UNORM for TC-compatible HTILE
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 15 Oct 2016 13:00:33 +0000 (15:00 +0200)]
radeonsi/gfx9: draw changes
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 7 Feb 2017 22:45:47 +0000 (23:45 +0100)]
radeonsi/gfx9: pad shader binaries by 128 bytes
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 15 Oct 2016 12:51:06 +0000 (14:51 +0200)]
radeonsi/gfx9: trivial shader and ring changes
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 15 Oct 2016 12:49:19 +0000 (14:49 +0200)]
radeonsi/gfx9: sampler state changes
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 9 Jan 2017 15:32:12 +0000 (16:32 +0100)]
radeonsi/gfx9: add a scissor bug workaround
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 15 Oct 2016 12:47:44 +0000 (14:47 +0200)]
radeonsi/gfx9: rasterizer changes
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 1 Feb 2017 01:00:05 +0000 (02:00 +0100)]
radeonsi/gfx9: disable the 2-bit format fetch fix
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 1 Feb 2017 01:16:46 +0000 (02:16 +0100)]
radeonsi/gfx9: set NUM_RECORDS correctly
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 15 Oct 2016 12:21:59 +0000 (14:21 +0200)]
radeonsi/gfx9: ELEMENT_SIZE change
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 15 Oct 2016 12:28:01 +0000 (14:28 +0200)]
radeonsi/gfx9: enable ETC2
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 6 Nov 2016 19:08:24 +0000 (20:08 +0100)]
radeonsi/gfx9: disable RB+ on Vega10
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 15 Oct 2016 12:43:32 +0000 (14:43 +0200)]
radeonsi/gfx9: init_config changes
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 8 Dec 2016 15:54:24 +0000 (16:54 +0100)]
radeonsi/gfx9: don't set PA_SC_RASTER_CONFIG*
The registers don't exist on GFX9.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 15 Oct 2016 12:25:40 +0000 (14:25 +0200)]
radeonsi/gfx9: Gather4 no longer needs the workaround
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 15 Oct 2016 12:20:03 +0000 (14:20 +0200)]
radeonsi/gfx9: CP DMA changes
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 15 Oct 2016 12:04:27 +0000 (14:04 +0200)]
radeonsi/gfx9: query changes - EVENT_WRITE and SET_PREDICATION
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 15 Oct 2016 12:01:39 +0000 (14:01 +0200)]
radeonsi/gfx9: EVENT_WRITE_EOP -> RELEASE_MEM
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 15 Oct 2016 12:23:26 +0000 (14:23 +0200)]
radeonsi/gfx9: INDIRECT_BUFFER change
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 10 Feb 2017 00:40:13 +0000 (01:40 +0100)]
radeonsi/gfx9: enable SDMA buffer copying & clearing
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 15 Oct 2016 12:17:56 +0000 (14:17 +0200)]
radeonsi/gfx9: handle GFX9 in a few places
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 15 Oct 2016 12:22:40 +0000 (14:22 +0200)]
radeonsi/gfx9: don't read back non-existent SRBM registers
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 6 Oct 2016 18:24:45 +0000 (20:24 +0200)]
radeonsi/gfx9: add IB parser support
Both GFX6 and GFX9 fields are printed next to each other in parsed IBs.
The Python script parses both headers like one stream and tries to merge
all definitions.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 14 Dec 2016 17:35:12 +0000 (18:35 +0100)]
radeonsi/gfx9: set the LLVM processor, require LLVM 5.0
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 15 Oct 2016 11:57:59 +0000 (13:57 +0200)]
radeonsi/gfx9: add GFX9 and VEGA10 enums
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 15 Oct 2016 11:38:45 +0000 (13:38 +0200)]
amd: GFX9 packet changes
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 28 Oct 2016 00:33:25 +0000 (02:33 +0200)]
amd: define event types for GFX9
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 30 Sep 2016 23:53:05 +0000 (01:53 +0200)]
amd: add texture format definitions for GFX9
the DATA_FORMAT and NUM_FORMAT fields are the same, but some of the enums
differ, thus add GFX6 and GFX9 suffixes, so that the IB parser can show
enums for both.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 30 Aug 2016 21:42:29 +0000 (23:42 +0200)]
amd: resolve remaining definition conflicts with gfx9d.h
Add _GFX6 and _GFX9 suffixes to conflicting definitions.
sid.h and gfx9d.h can now be included in the same file.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 30 Aug 2016 21:37:13 +0000 (23:37 +0200)]
amd: normalize register definition formatting
This resolves trivial conflicts with gfx9d.h caused by different formatting.
Some fields are also renamed.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 30 Aug 2016 20:32:34 +0000 (22:32 +0200)]
amd: import GFX9 register definitions
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 15 Oct 2016 13:16:05 +0000 (15:16 +0200)]
radeonsi: code shuffling in si_init_depth_surface
use fewer local variables, re-order the assignments, so that the GFX9 diff
is smaller here.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 14 Mar 2017 21:32:25 +0000 (22:32 +0100)]
amd/addrlib: silence warnings
Nicolai Hähnle [Thu, 6 Oct 2016 16:55:25 +0000 (18:55 +0200)]
amd/addrlib: import gfx9 support
Kevin Furrow [Wed, 5 Oct 2016 13:07:01 +0000 (09:07 -0400)]
amd/addrlib: Not all ETC2 formats are 128bpp... add new ETC2 formats to differentiate between 64 and 128bpp formats.
Kevin Furrow [Sat, 1 Oct 2016 17:39:20 +0000 (13:39 -0400)]
amd/addrlib: Fix selection of swizzle modes for 3D compressed images.
Kevin Furrow [Fri, 16 Sep 2016 12:48:54 +0000 (08:48 -0400)]
amd/addrlib: Add support for ETC2 and ASTC formats.
Joe Ma [Fri, 2 Sep 2016 06:13:40 +0000 (02:13 -0400)]
amd/addrlib: Bump version to 6.02
Frans Gu [Thu, 7 Jul 2016 11:08:16 +0000 (07:08 -0400)]
amd/addrlib: Adjust slie size after pitch and actual height adjustment
Frans Gu [Fri, 1 Jul 2016 08:54:44 +0000 (04:54 -0400)]
amd/addrlib: Apply input pitch after internal pitch aligning
Nicolai Hähnle [Wed, 20 Jul 2016 08:56:35 +0000 (10:56 +0200)]
amdgpu/addrlib: Bump version to 6.01
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Nicolai Hähnle [Wed, 20 Jul 2016 08:33:44 +0000 (10:33 +0200)]
amdgpu/addrlib: Seperate 2 dcc related workarounds by different flags
1) dccCompatible for padding MSAA surface to support fast clear
2) dccPipeWorkaround for padding surface to support dcc
Nicolai Hähnle [Wed, 20 Jul 2016 08:51:50 +0000 (10:51 +0200)]
amdgpu/addrlib: Fix the issue that tcCompatible HTILE slice size is not calculated correctly
Nicolai Hähnle [Wed, 20 Jul 2016 08:34:41 +0000 (10:34 +0200)]
amdgpu/addrlib: Add a new output flag to notify client that the returned tile index is for PRT on SI
If this flag is set for mip0, client should set prt flag for sub mips,
so that address lib can select the correct tile index for sub mips.
Xavi Zhang [Tue, 1 Mar 2016 08:40:15 +0000 (03:40 -0500)]
amdgpu/addrlib: add matchStencilTileCfg and tcCompatible fixes
The usage should be client first call AddrComputeSurfaceInfo() on
depth surface with flag "matchStencilTilecfg", AddrLib will use
2DThin1 tile index for depth as much as possible and do not down grade
unless alignment requirement cannot be met.
1. If there is a matched 2DThin1 tile index for stencil which make
sure they will share same tile config parameters, then return the
stencil 2DThin1 tile index as well.
2. If using 2DThin1 tile mode cannot make sure such thing happen, and
TcCompatible flag was set, then ignore this flag then try 2DThin1 tile
mode for depth and stencil again.
3. If 2DThin1 tile mode cannot make sure depth and stencil to have
same tile config parameters, then down grade depth surface tile mode
to 1DThin1.
4. If depth surface's tile mode was 1DThin1, then return 1DThin1 tile
index for stencil.
5. If depth surface's tile mode is PRT, then return invalid tile index
to stencil since their tile config parameters will never be met.
Client driver then check the returned tile index of stencil -- if it
is not invalid tile index, then call AddrComputeSurfaceInfo() on
stencil surface with the returned stencil tile index to get full
output information. Please note, client needs to set flag
"useTileIndex" when AddrLib get created.
Frans Gu [Fri, 4 Mar 2016 10:04:23 +0000 (05:04 -0500)]
amdgpu/addrlib: Adjust bank equation bit order based on macro tile aspect ratio settings
By this way, we can have valid equation for 2D_THIN1 tile mode.
Add flag "preferEquation" to return equation index without adjusting
input tile mode.
Frans Gu [Thu, 10 Mar 2016 07:24:00 +0000 (02:24 -0500)]
amdgpu/addrlib: do some tile mode conversions to display surface
Xavi Zhang [Mon, 29 Feb 2016 06:36:08 +0000 (01:36 -0500)]
amdgpu/addrlib: Check prt flag for PRT_THIN1 extra padding for DCC.
Frans Gu [Tue, 18 Aug 2015 03:56:23 +0000 (23:56 -0400)]
amdgpu/addrlib: Add new flags minimizePadding and maxBaseAlign
1) minimizePadding - Use 1D tile mode if padded size of 2D is bigger
than 1D
2) maxBaseAlign - Force PRT tile mode if macro block size is bigger than
requested alignment.
Also, related changes to tile mode optimization for needEquation.
Xavi Zhang [Fri, 26 Feb 2016 07:49:28 +0000 (02:49 -0500)]
amdgpu/addrlib: Always returns pixelPitch in original pixels
Sabre Shao [Thu, 25 Feb 2016 10:30:33 +0000 (05:30 -0500)]
amdgpu/addrlib: fix crash on allocation failure
Frans Gu [Tue, 23 Feb 2016 03:05:19 +0000 (22:05 -0500)]
amdgpu/addrlib: Add flag to report if a surface can have dcc ram
Roy Zhan [Sun, 10 Jan 2016 12:56:11 +0000 (07:56 -0500)]
amdgpu/addrlib: support non-power2 height alignment (for linear surface)
Frans Gu [Thu, 22 Oct 2015 06:11:51 +0000 (02:11 -0400)]
amdgpu/addrlib: Fix family setting for VI and CZ ASICs
Nicolai Hähnle [Wed, 20 Jul 2016 19:31:24 +0000 (21:31 +0200)]
amdgpu/addrlib: style cleanup
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Nicolai Hähnle [Wed, 20 Jul 2016 19:30:56 +0000 (21:30 +0200)]
amdgpu/addrlib: Pad pitch to multiples of 256 for DCC surface on Fiji
The change also modifies function CiLib::HwlPadDimensions to report
adjusted pitch alignment.
Xavi Zhang [Fri, 21 Aug 2015 10:25:12 +0000 (06:25 -0400)]
amdgpu/addrlib: Fix number of //
Find ^/{80,99}$ and replace them to 100 "/"
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Nicolai Hähnle [Wed, 20 Jul 2016 19:13:41 +0000 (21:13 +0200)]
amdgpu/addrlib: Cleanup.
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Xavi Zhang [Thu, 20 Aug 2015 07:59:01 +0000 (03:59 -0400)]
amdgpu/addrlib: Use namespaces
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Kevin Zhao [Tue, 18 Aug 2015 04:17:31 +0000 (00:17 -0400)]
amdgpu/addrlib: Adjust 99 "*" to 100 "*" alignment
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Frans Gu [Fri, 14 Aug 2015 10:03:24 +0000 (06:03 -0400)]
amdgpu/addrlib: Add a new tile mode ADDR_TM_UNKNOWN
This can be used by address lib client to ask address lib to select
tile mode.
Xavi Zhang [Sun, 28 Jun 2015 05:02:59 +0000 (01:02 -0400)]
amdgpu/addrlib: Stylish cleanup.
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Roy Zhan [Tue, 9 Jun 2015 08:46:59 +0000 (04:46 -0400)]
amdgpu/addrlib: Disable tcComaptible when depth surface is not macro tiled
Experiment show 1D tiling + TcCompatible cannot work together.
Xavi Zhang [Tue, 12 May 2015 08:26:59 +0000 (04:26 -0400)]
amdgpu/addrlib: fix pixel index calculation of thick micro tiling