mesa.git
8 years agonir/builder: Add a helper for inserting jump instructions
Jason Ekstrand [Sun, 14 Feb 2016 01:14:27 +0000 (17:14 -0800)]
nir/builder: Add a helper for inserting jump instructions

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
8 years agonir/cf: Make extracting or re-inserting nothing a no-op
Jason Ekstrand [Thu, 24 Dec 2015 02:10:08 +0000 (18:10 -0800)]
nir/cf: Make extracting or re-inserting nothing a no-op

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
8 years agonir: Add a function for comparing cursors
Jason Ekstrand [Sat, 26 Dec 2015 18:32:10 +0000 (10:32 -0800)]
nir: Add a function for comparing cursors

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
8 years agonir/cf: Handle relinking top-level blocks
Jason Ekstrand [Fri, 18 Dec 2015 19:27:00 +0000 (11:27 -0800)]
nir/cf: Handle relinking top-level blocks

This can happen if a function ends in a return instruction and you remove
the return.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
8 years agonir: Add a pass to repair SSA form
Jason Ekstrand [Sat, 13 Feb 2016 05:52:46 +0000 (21:52 -0800)]
nir: Add a pass to repair SSA form

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
8 years agonir/vars_to_ssa: Use the new nir_phi_builder helper
Jason Ekstrand [Sat, 13 Feb 2016 05:48:26 +0000 (21:48 -0800)]
nir/vars_to_ssa: Use the new nir_phi_builder helper

The efficiency should be approximately the same.  We do a little more work
per phi node because we have to sort the predecessors.  However, we no
longer have to walk the blocks a second time to pop things off the stack.
The bigger advantage, however, is that we can now re-use the phi placement
and per-block SSA value tracking in other passes.

As a side-benifit, the phi builder actually handles unreachable blocks
correctly.  The original vars_to_ssa code, because of the way it iterated
the blocks and added phi sources, didn't add sources corresponding to
predecessors of unreachable blocks.  The new strategy employed by the phi
builder creates a phi source for each predecessor and should correctly
handle unreachable blocks by setting those sources to SSA undefs.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
8 years agonir/dominance: Handle unreachable blocks
Jason Ekstrand [Tue, 29 Dec 2015 23:25:43 +0000 (15:25 -0800)]
nir/dominance: Handle unreachable blocks

Previously, nir_dominance.c didn't properly handle unreachable blocks.
This can happen if, for instance, you have something like this:

loop {
   if (...) {
      break;
   } else {
      break;
   }
}

In this case, the block right after the if statement will be unreachable.
This commit makes two changes to handle this.  First, it removes an assert
and allows block->imm_dom to be null if the block is unreachable.  Second,
it properly skips unreachable blocks in calc_dom_frontier_cb.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
8 years agonir: Add a phi node placement helper
Jason Ekstrand [Sat, 13 Feb 2016 05:41:42 +0000 (21:41 -0800)]
nir: Add a phi node placement helper

Right now, we have phi placement code in two places and there are other
places where it would be nice to be able to do this analysis.  Instead of
repeating it all over the place, this commit adds a helper for placing all
of the needed phi nodes for a value.

v2: Add better documentation

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
8 years agoutil/bitset: Allow iterating over const bitsets
Jason Ekstrand [Sun, 17 Jan 2016 00:42:06 +0000 (16:42 -0800)]
util/bitset: Allow iterating over const bitsets

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
8 years agottn: remove stray global from header
Rob Clark [Thu, 24 Mar 2016 19:44:35 +0000 (15:44 -0400)]
ttn: remove stray global from header

Signed-off-by: Rob Clark <robclark@freedesktop.org>
8 years agonv50/ir: silence unhandled TGSI_PROPERTY_NEXT_SHADER info
Samuel Pitoiset [Wed, 23 Mar 2016 22:29:20 +0000 (23:29 +0100)]
nv50/ir: silence unhandled TGSI_PROPERTY_NEXT_SHADER info

radeonsi uses this property to make the best decision about which
shader to compile, but this is not currently used by our codegen.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agomesa: Handle negative length in glPushDebugGroup().
Kenneth Graunke [Thu, 24 Mar 2016 06:46:12 +0000 (23:46 -0700)]
mesa: Handle negative length in glPushDebugGroup().

The KHR_debug spec doesn't actually say we should handle this, but that
is most likely an oversight - it says to check against strlen and
generate errors if length is negative.  It appears they just forgot to
explicitly spell out that we should then proceed to actually handle it.

Fixes crashes from uncaught std::string exceptions in many
dEQP-GLES31.functional.debug.error_filters.* tests.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
8 years agomesa: Make glDebugMessageInsert deal with negative length for all types.
Kenneth Graunke [Thu, 24 Mar 2016 06:35:40 +0000 (23:35 -0700)]
mesa: Make glDebugMessageInsert deal with negative length for all types.

From the KHR_debug spec, section 5.5.5 (Externally Generated Messages):

   "If <length> is negative, it is implied that <buf> contains a null
    terminated string. The error INVALID_VALUE will be generated if the
    number of characters in <buf>, excluding the null terminator when
    <length> is negative, is not less than the value of
    MAX_DEBUG_MESSAGE_LENGTH."

This indicates that length should be set to strlen for all types, not
just GL_DEBUG_TYPE_MARKER.  We want it to be after validate_length()
so we still generate appropriate errors.

Fixes crashes from uncaught std::string exceptions in many
dEQP-GLES31.functional.debug.error_filters.* tests.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
8 years agomesa: Include null terminator in GL_DEBUG_NEXT_LOGGED_MESSAGE_LENGTH.
Kenneth Graunke [Thu, 24 Mar 2016 04:38:42 +0000 (21:38 -0700)]
mesa: Include null terminator in GL_DEBUG_NEXT_LOGGED_MESSAGE_LENGTH.

From the KHR_debug spec:
"Applications can query the number of messages currently in the log by
 obtaining the value of DEBUG_LOGGED_MESSAGES, and the string length
 (including its null terminator) of the oldest message in the log
 through the value of DEBUG_NEXT_LOGGED_MESSAGE_LENGTH."

Because we weren't including the null terminator, many dEQP tests
called glGetDebugMessageLog with a bufSize parameter that was 1 too
small, and unable to contain the message, so we skipped returning it,
failing many cases.

Fixes 298 dEQP-GLES31.functional.debug.* tests.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Stephane Marchesin <stephane.marchesin@gmail.com>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
8 years agost/mesa: use RGBA instead of BGRA for SRGB_ALPHA
Nicolai Hähnle [Wed, 23 Mar 2016 20:22:16 +0000 (15:22 -0500)]
st/mesa: use RGBA instead of BGRA for SRGB_ALPHA

This fixes a regression introduced by commit a8eea696 "st/mesa: honour sized
internal formats in st_choose_format (v2)".

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94657
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94671
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoradeonsi: silence a coverity warning
Nicolai Hähnle [Wed, 23 Mar 2016 16:58:28 +0000 (11:58 -0500)]
radeonsi: silence a coverity warning

The following Coverity warning

5378      tmpl.fetch_args = atomic_fetch_args;
5379      tmpl.emit = atomic_emit;
>>>     CID 1357115:  Uninitialized variables  (UNINIT)
>>>     Using uninitialized value "tmpl". Field "tmpl.intr_name" is uninitialized.
5380      bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
5381      bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";

... is a false positive, but what the hell. This change should "fix" it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agomesa: replace gl_context->Multisample._Enabled with _mesa_is_multisample_enabled.
Bas Nieuwenhuizen [Thu, 24 Mar 2016 14:30:09 +0000 (08:30 -0600)]
mesa: replace gl_context->Multisample._Enabled with _mesa_is_multisample_enabled.

This removes any dependency on driver validation of the number of
framebuffer samples.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Brian Paul <brianp@vmware.com>
8 years agonir: fix dangling ssadef->name ptrs
Rob Clark [Tue, 22 Mar 2016 19:02:42 +0000 (15:02 -0400)]
nir: fix dangling ssadef->name ptrs

In many places, the convention is to pass an existing ssadef name ptr
when construction/initializing a new nir_ssa_def.  But that goes badly
(as noticed by garbage in nir_print output) when the original string
gets freed.

Just use ralloc_strdup() instead, and add ralloc_free() in the two
places that would care (not that the strings wouldn't eventually get
freed anyways).

Also fixup the nir_search code which was directly setting ssadef->name
to use the parent instruction as memctx.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
8 years agoglsl: Add propagate_invariance to the other makefile
Jason Ekstrand [Thu, 24 Mar 2016 04:04:18 +0000 (21:04 -0700)]
glsl: Add propagate_invariance to the other makefile

This fixes the scons build

8 years agonir/glsl: Propagate invariant into NIR alu ops
Jason Ekstrand [Thu, 17 Mar 2016 22:20:20 +0000 (15:20 -0700)]
nir/glsl: Propagate invariant into NIR alu ops

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
8 years agoglsl/rebalance_tree: Don't handle invariant or precise trees
Jason Ekstrand [Thu, 17 Mar 2016 21:44:57 +0000 (14:44 -0700)]
glsl/rebalance_tree: Don't handle invariant or precise trees

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
8 years agoglsl/opt_algebraic: Don't handle invariant or precise trees
Jason Ekstrand [Thu, 17 Mar 2016 21:41:14 +0000 (14:41 -0700)]
glsl/opt_algebraic: Don't handle invariant or precise trees

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
8 years agoglsl: Add a pass to propagate the "invariant" and "precise" qualifiers
Jason Ekstrand [Thu, 17 Mar 2016 20:58:40 +0000 (13:58 -0700)]
glsl: Add a pass to propagate the "invariant" and "precise" qualifiers

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
8 years agonir/alu_to_scalar: Propagate the "exact" bit
Jason Ekstrand [Thu, 17 Mar 2016 23:13:40 +0000 (16:13 -0700)]
nir/alu_to_scalar: Propagate the "exact" bit

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
8 years agoi965/peephole_ffma: Don't fuse exact adds
Jason Ekstrand [Thu, 17 Mar 2016 20:39:07 +0000 (13:39 -0700)]
i965/peephole_ffma: Don't fuse exact adds

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
8 years agonir/cse: Properly handle nir_ssa_def.exact
Jason Ekstrand [Thu, 17 Mar 2016 18:38:54 +0000 (11:38 -0700)]
nir/cse: Properly handle nir_ssa_def.exact

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
8 years agonir/algebraic: Flag inexact optimizations
Jason Ekstrand [Thu, 17 Mar 2016 18:31:48 +0000 (11:31 -0700)]
nir/algebraic: Flag inexact optimizations

Many of our optimizations, while great for cutting shaders down to size,
aren't really precision-safe.  This commit tries to flag all of the
inexact floating-point optimizations so they don't get run on values that
are flagged "exact".  It's a bit conservative and maybe flags some safe
optimizations as unsafe but that's better than missing one.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
8 years agonir/algebraic: Fix fmin detection to match the spec
Jason Ekstrand [Wed, 23 Mar 2016 21:30:29 +0000 (14:30 -0700)]
nir/algebraic: Fix fmin detection to match the spec

The previous transformation got the arguments to fmin backwards.  When NaNs
are involved, the GLSL min/max aren't commutative so it matters.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
8 years agonir/algebraic: Get rid of an invlid fxor optimization
Jason Ekstrand [Wed, 23 Mar 2016 21:25:56 +0000 (14:25 -0700)]
nir/algebraic: Get rid of an invlid fxor optimization

The fxor opcode is required to return 1.0f or 0.0f but the input variable
may not be 1.0f or 0.0f.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
8 years agonir/algebraic: Allow for flagging operations as being inexact
Jason Ekstrand [Thu, 17 Mar 2016 18:04:49 +0000 (11:04 -0700)]
nir/algebraic: Allow for flagging operations as being inexact

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
8 years agonir/search: Propagate exactness into newly created expressions
Jason Ekstrand [Thu, 17 Mar 2016 22:20:34 +0000 (15:20 -0700)]
nir/search: Propagate exactness into newly created expressions

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
8 years agonir/builder: Add a flag for setting exact
Jason Ekstrand [Thu, 17 Mar 2016 22:54:26 +0000 (15:54 -0700)]
nir/builder: Add a flag for setting exact

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
8 years agonir: Add an "exact" bit to nir_alu_instr
Jason Ekstrand [Thu, 17 Mar 2016 17:50:27 +0000 (10:50 -0700)]
nir: Add an "exact" bit to nir_alu_instr

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
8 years agonir/clone: Export nir_variable_clone
Jason Ekstrand [Wed, 23 Mar 2016 22:05:55 +0000 (15:05 -0700)]
nir/clone: Export nir_variable_clone

Reviewed-by: Rob Clark <robclark@gmail.com>
8 years agonir/clone: Expose nir_constant_clone
Jason Ekstrand [Thu, 31 Dec 2015 02:44:19 +0000 (18:44 -0800)]
nir/clone: Expose nir_constant_clone

Reviewed-by: Rob Clark <robclark@gmail.com>
8 years agonir: Fix whitespace
Jason Ekstrand [Wed, 23 Mar 2016 21:57:57 +0000 (14:57 -0700)]
nir: Fix whitespace

Reviewed-by: Rob Clark <robclark@gmail.com>
8 years agodocs: use latest libDRM version
Brian Paul [Wed, 23 Mar 2016 18:55:45 +0000 (12:55 -0600)]
docs: use latest libDRM version

Signed-off-by: Brian Paul <brianp@vmware.com>
8 years agocompiler/glsl: allow sequence op as a const expr in gles 1.0
Lars Hamre [Wed, 23 Mar 2016 14:14:23 +0000 (10:14 -0400)]
compiler/glsl: allow sequence op as a const expr in gles 1.0

Allow the sequence operator to be a constant expression in GLSL ES
versions prior to GLSL ES 3.0

Fixes the following piglit test:
/all/spec/glsl-es-1.0/compiler/array-sized-by-sequence-in-parenthesis.vert

This is similar to the logic from process_initializer() which performs
the same check for constant variable initialization with sequence
operators.

v2: Fixed regression pointed out by Eduardo Lima Mitev

Signed-off-by: Lars Hamre <chemecse@gmail.com>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
8 years agoradeonsi: fix out-of-bounds indexing of shader images
Nicolai Hähnle [Mon, 21 Mar 2016 19:50:50 +0000 (14:50 -0500)]
radeonsi: fix out-of-bounds indexing of shader images

Results are undefined but may not crash. Without this change, out-of-bounds
indexing can lead to VM faults and GPU hangs.

Constant buffers, samplers, and possibly others will eventually need similar
treatment to support GL_ARB_robust_buffer_access_behavior.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
8 years agoradeonsi: cache flush/invalidation for missing PIPE_BARRIER_*_BUFFER bits (v2)
Nicolai Hähnle [Thu, 17 Mar 2016 01:47:47 +0000 (20:47 -0500)]
radeonsi: cache flush/invalidation for missing PIPE_BARRIER_*_BUFFER bits (v2)

This fixes arb_shader_image_load_store-host-mem-barrier.

v2: flush TC L2 for index buffers on <= CIK (Marek)

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agost/mesa: add missing MemoryBarrier bits and some explanations
Nicolai Hähnle [Fri, 18 Mar 2016 00:49:26 +0000 (19:49 -0500)]
st/mesa: add missing MemoryBarrier bits and some explanations

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agogallium: add PIPE_BARRIER_STREAMOUT_BUFFER
Nicolai Hähnle [Fri, 18 Mar 2016 00:49:03 +0000 (19:49 -0500)]
gallium: add PIPE_BARRIER_STREAMOUT_BUFFER

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoradeonsi: fix 2D array MSAA failures since image support landed
Marek Olšák [Tue, 22 Mar 2016 17:26:53 +0000 (18:26 +0100)]
radeonsi: fix 2D array MSAA failures since image support landed

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
8 years agoi965/fs: Don't constant-fold RCP
Jason Ekstrand [Thu, 17 Mar 2016 02:31:02 +0000 (19:31 -0700)]
i965/fs: Don't constant-fold RCP

No shader-db changes on Broadwell

Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agoi965: Remove the RCP+RSQ algebraic optimizations
Jason Ekstrand [Wed, 16 Mar 2016 23:06:10 +0000 (16:06 -0700)]
i965: Remove the RCP+RSQ algebraic optimizations

NIR already has this optimization and it can do much better than the little
peephole in the backend.

No shader-db change on Haswell or Broadwell.

Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agonir: Don't abs slt and friends
Ian Romanick [Wed, 2 Mar 2016 21:47:56 +0000 (13:47 -0800)]
nir: Don't abs slt and friends

No shader-db changes, but this is symmetric with the previous commit.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agonir: Don't abs the result of b2f or b2i
Ian Romanick [Wed, 2 Mar 2016 21:46:50 +0000 (13:46 -0800)]
nir: Don't abs the result of b2f or b2i

In the results below, 2 SIMD16 shaders in Trine are lost.

G4X
total instructions in shared programs: 4012279 -> 4011108 (-0.03%)
instructions in affected programs: 116776 -> 115605 (-1.00%)
helped: 339
HURT: 0

total cycles in shared programs: 84315862 -> 84313584 (-0.00%)
cycles in affected programs: 1767232 -> 1764954 (-0.13%)
helped: 274
HURT: 81

Ironlake
total instructions in shared programs: 6399073 -> 6396998 (-0.03%)
instructions in affected programs: 218050 -> 215975 (-0.95%)
helped: 600
HURT: 0

total cycles in shared programs: 128892088 -> 128888810 (-0.00%)
cycles in affected programs: 2867452 -> 2864174 (-0.11%)
helped: 422
HURT: 137

Sandy Bridge
total instructions in shared programs: 8462174 -> 8460759 (-0.02%)
instructions in affected programs: 178529 -> 177114 (-0.79%)
helped: 596
HURT: 0

total cycles in shared programs: 117542276 -> 117534098 (-0.01%)
cycles in affected programs: 1239166 -> 1230988 (-0.66%)
helped: 369
HURT: 150

Ivy Bridge
total instructions in shared programs: 7775131 -> 7773410 (-0.02%)
instructions in affected programs: 162903 -> 161182 (-1.06%)
helped: 590
HURT: 0

total cycles in shared programs: 65759882 -> 65747268 (-0.02%)
cycles in affected programs: 1004354 -> 991740 (-1.26%)
helped: 467
HURT: 141

Haswell
total instructions in shared programs: 7107786 -> 7106327 (-0.02%)
instructions in affected programs: 140954 -> 139495 (-1.04%)
helped: 590
HURT: 0

total cycles in shared programs: 64668028 -> 64655322 (-0.02%)
cycles in affected programs: 967080 -> 954374 (-1.31%)
helped: 452
HURT: 149

LOST:   2
GAINED: 0

Broadwell
total instructions in shared programs: 8980029 -> 8978287 (-0.02%)
instructions in affected programs: 197232 -> 195490 (-0.88%)
helped: 715
HURT: 0

total cycles in shared programs: 70070448 -> 70055970 (-0.02%)
cycles in affected programs: 975724 -> 961246 (-1.48%)
helped: 471
HURT: 111

LOST:   2
GAINED: 0

Skylake
total instructions in shared programs: 9115178 -> 9113436 (-0.02%)
instructions in affected programs: 203012 -> 201270 (-0.86%)
helped: 715
HURT: 0

total cycles in shared programs: 68848660 -> 68834004 (-0.02%)
cycles in affected programs: 993888 -> 979232 (-1.47%)
helped: 473
HURT: 116

LOST:   2
GAINED: 0

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agonir: Simplify 0 < fabs(a)
Ian Romanick [Wed, 2 Mar 2016 23:36:14 +0000 (15:36 -0800)]
nir: Simplify 0 < fabs(a)

Sandy Bridge / Ivy Bridge / Haswell
total instructions in shared programs: 8462180 -> 8462174 (-0.00%)
instructions in affected programs: 564 -> 558 (-1.06%)
helped: 6
HURT: 0

total cycles in shared programs: 117542462 -> 117542276 (-0.00%)
cycles in affected programs: 9768 -> 9582 (-1.90%)
helped: 12
HURT: 0

Broadwell / Skylake
total instructions in shared programs: 8980833 -> 8980826 (-0.00%)
instructions in affected programs: 626 -> 619 (-1.12%)
helped: 7
HURT: 0

total cycles in shared programs: 70077900 -> 70077714 (-0.00%)
cycles in affected programs: 9378 -> 9192 (-1.98%)
helped: 12
HURT: 0

G45 and Ironlake showed no change.

v2: Modify the comments to look more like a proof.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agonir: Simplify 0 >= b2f(a)
Ian Romanick [Wed, 2 Mar 2016 23:18:34 +0000 (15:18 -0800)]
nir: Simplify 0 >= b2f(a)

This also prevented some regressions with other patches in my local
tree.

Broadwell / Skylake
total instructions in shared programs: 8980835 -> 8980833 (-0.00%)
instructions in affected programs: 45 -> 43 (-4.44%)
helped: 1
HURT: 0

total cycles in shared programs: 70077904 -> 70077900 (-0.00%)
cycles in affected programs: 122 -> 118 (-3.28%)
helped: 1
HURT: 0

No changes on earlier platforms.

v2: Modify the comments to look more like a proof.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agonir: Simplify i2b with negated or abs operand
Ian Romanick [Wed, 2 Mar 2016 02:59:57 +0000 (18:59 -0800)]
nir: Simplify i2b with negated or abs operand

This enables removing ssa_201 and ssa_202 in sequences like:

                 vec1 ssa_200 = flt ssa_199, ssa_194
                 vec1 ssa_201 = b2i ssa_200
                 vec1 ssa_202 = i2b -ssa_201

shader-db results:

Sandy Bridge
total instructions in shared programs: 8462257 -> 8462180 (-0.00%)
instructions in affected programs: 3846 -> 3769 (-2.00%)
helped: 35
HURT: 0

total cycles in shared programs: 117542934 -> 117542462 (-0.00%)
cycles in affected programs: 20072 -> 19600 (-2.35%)
helped: 20
HURT: 1

Ivy Bridge
total instructions in shared programs: 7775252 -> 7775137 (-0.00%)
instructions in affected programs: 3645 -> 3530 (-3.16%)
helped: 35
HURT: 0

total cycles in shared programs: 65760522 -> 65760068 (-0.00%)
cycles in affected programs: 21082 -> 20628 (-2.15%)
helped: 25
HURT: 2

Haswell
total instructions in shared programs: 7108666 -> 7108589 (-0.00%)
instructions in affected programs: 3253 -> 3176 (-2.37%)
helped: 35
HURT: 0

total cycles in shared programs: 64675726 -> 64675272 (-0.00%)
cycles in affected programs: 21034 -> 20580 (-2.16%)
helped: 26
HURT: 1

Broadwell / Skylake
total instructions in shared programs: 8980912 -> 8980835 (-0.00%)
instructions in affected programs: 3223 -> 3146 (-2.39%)
helped: 35
HURT: 0

total cycles in shared programs: 70077926 -> 70077904 (-0.00%)
cycles in affected programs: 21886 -> 21864 (-0.10%)
helped: 21
HURT: 6

G45 and Ironlake showed no change.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Suggested-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agonir: Lower flrp with Boolean interpolator to bcsel
Ian Romanick [Mon, 7 Mar 2016 21:09:30 +0000 (13:09 -0800)]
nir: Lower flrp with Boolean interpolator to bcsel

On Intel platforms that don't set lower_flrp, using bcsel instead of
flrp seems to be a small amount worse.  On those platforms, the use of
flrp, bcsel, and multiply of b2f is still an active area of research.
In review, Matt suggested this is because bcsel turns into CMP+SEL, and
because of the flag register we can't schedule instructions well.

shader-db results:

G4X / Ironlake
total instructions in shared programs: 4016538 -> 4012279 (-0.11%)
instructions in affected programs: 161556 -> 157297 (-2.64%)
helped: 1077
HURT: 1

total cycles in shared programs: 84328296 -> 84315862 (-0.01%)
cycles in affected programs: 4174570 -> 4162136 (-0.30%)
helped: 926
HURT: 53

Unsurprisingly, no changes on later platforms.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agoi965: Have NIR lower flrp on pre-GEN6 vec4 backend
Ian Romanick [Mon, 7 Mar 2016 18:55:21 +0000 (10:55 -0800)]
i965: Have NIR lower flrp on pre-GEN6 vec4 backend

Previously we were doing the lowering by hand in vec4_visitor::emit_lrp.
By doing it in NIR, we have the opportunity for NIR to do additional
optimization of the expanded code.

This also enables optimizations added by the next commit.

shader-db results:

G4X / Ironlake
total instructions in shared programs: 4024401 -> 4016538 (-0.20%)
instructions in affected programs: 447686 -> 439823 (-1.76%)
helped: 2623
HURT: 0

total cycles in shared programs: 84375846 -> 84328296 (-0.06%)
cycles in affected programs: 16964960 -> 16917410 (-0.28%)
helped: 2556
HURT: 41

Unsurprisingly, no changes on later platforms.

v2: Formatting and comment changes suggested by Matt.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agoswrast: fix discarded const warning in s_texture.c
Brian Paul [Tue, 22 Mar 2016 14:35:25 +0000 (08:35 -0600)]
swrast: fix discarded const warning in s_texture.c

Signed-off-by: Brian Paul <brianp@vmware.com>
8 years agoi965: fix invalid memory write
Marc-André Lureau [Fri, 18 Mar 2016 19:01:07 +0000 (20:01 +0100)]
i965: fix invalid memory write

I noticed some heap corruption running virgl tests, and valgrind
helped me to track it down to the following error:

==29272== Invalid write of size 4
==29272==    at 0x90283D4: push_loop_stack (brw_eu_emit.c:1307)
==29272==    by 0x9029A7D: brw_DO (brw_eu_emit.c:1750)
==29272==    by 0x90554B0: fs_generator::generate_code(cfg_t const*, int) (brw_fs_generator.cpp:1999)
==29272==    by 0x904491F: brw_compile_fs (brw_fs.cpp:5685)
==29272==    by 0x8FC5DC5: brw_codegen_wm_prog (brw_wm.c:137)
==29272==    by 0x8FC7663: brw_fs_precompile (brw_wm.c:638)
==29272==    by 0x8FA4040: brw_shader_precompile(gl_context*, gl_shader_program*) (brw_link.cpp:51)
==29272==    by 0x8FA4A9A: brw_link_shader (brw_link.cpp:260)
==29272==    by 0x8DEF751: _mesa_glsl_link_shader (ir_to_mesa.cpp:3006)
==29272==    by 0x8C84325: _mesa_link_program (shaderapi.c:1042)
==29272==    by 0x8C851D7: _mesa_LinkProgram (shaderapi.c:1515)
==29272==    by 0x4E4B8E8: add_shader_program (vrend_renderer.c:880)
==29272==  Address 0xf2f3cb0 is 0 bytes after a block of size 112 alloc'd
==29272==    at 0x4C2AA98: calloc (vg_replace_malloc.c:711)
==29272==    by 0x8ED11F7: ralloc_size (ralloc.c:113)
==29272==    by 0x8ED1282: rzalloc_size (ralloc.c:134)
==29272==    by 0x8ED14C0: rzalloc_array_size (ralloc.c:196)
==29272==    by 0x9019C7B: brw_init_codegen (brw_eu.c:291)
==29272==    by 0x904F565: fs_generator::fs_generator(brw_compiler const*, void*, void*, void const*, brw_stage_prog_data*, unsigned int, bool, gl_shader_stage) (brw_fs_generator.cpp:124)
==29272==    by 0x9044883: brw_compile_fs (brw_fs.cpp:5675)
==29272==    by 0x8FC5DC5: brw_codegen_wm_prog (brw_wm.c:137)
==29272==    by 0x8FC7663: brw_fs_precompile (brw_wm.c:638)
==29272==    by 0x8FA4040: brw_shader_precompile(gl_context*, gl_shader_program*) (brw_link.cpp:51)
==29272==    by 0x8FA4A9A: brw_link_shader (brw_link.cpp:260)
==29272==    by 0x8DEF751: _mesa_glsl_link_shader (ir_to_mesa.cpp:3006)

if_depth_in_loop is an array of size p->loop_stack_array_size, and
push_loop_stack() will access if_depth_in_loop[p->loop_stack_depth+1],
thus the condition to grow the array should be
p->loop_stack_array_size <= (p->loop_stack_depth + 1) (it's currently
off by 2...)

This can be reproduced by running the following test with virgl test
server:
LIBGL_ALWAYS_SOFTWARE=y GALLIUM_DRIVER=virpipe bin/shader_runner
./tests/shaders/glsl-fs-unroll-explosion.shader_test -auto

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agotgsi: drop unused set_exec/kill_mask interfaces.
Dave Airlie [Tue, 22 Mar 2016 00:28:44 +0000 (10:28 +1000)]
tgsi: drop unused set_exec/kill_mask interfaces.

These don't get used and haven't been in git history from what I can
see, so drop them.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
8 years agodocs/relnotes: update ARB_internalformat_query2 status.
Dave Airlie [Mon, 21 Mar 2016 23:53:47 +0000 (09:53 +1000)]
docs/relnotes: update ARB_internalformat_query2 status.

Signed-off-by: Dave Airlie <Airlied@redhat.com>
8 years agost/mesa: add support for internalformat query2.
Dave Airlie [Fri, 4 Mar 2016 02:33:46 +0000 (12:33 +1000)]
st/mesa: add support for internalformat query2.

Add code to handle GL_INTERNALFORMAT_PREFERRED.
Add code to deal with GL_RENDERBUFFER being passes into ChooseTextureFormat.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
8 years agoi965: Fix assert conditions for src/dst x/y offsets
Anuj Phogat [Fri, 11 Mar 2016 23:24:36 +0000 (15:24 -0800)]
i965: Fix assert conditions for src/dst x/y offsets

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoswrast: Move assert for 'slice' in to check_map_teximage
Anuj Phogat [Mon, 14 Mar 2016 17:25:50 +0000 (10:25 -0700)]
swrast: Move assert for 'slice' in to check_map_teximage

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
8 years agor600/sb: Do not distribute neg in expr_handler::fold_assoc() when folding multiplicat...
xavier [Wed, 9 Mar 2016 08:58:48 +0000 (09:58 +0100)]
r600/sb: Do not distribute neg in expr_handler::fold_assoc() when folding multiplications.

Previously it was doing this transformation for a Trine 3 shader:
     MUL     R6.x.12,    R13.x.23, 0.5|3f000000
-    MULADD     R4.x.12,    -R6.x.12, 2|40000000, 1|3f800000
+    MULADD     R4.x.12,    -R13.x.23, -1|bf800000, 1|3f800000

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94412
Signed-off-by: Xavier Bouchoux <xavierb@gmail.com>
Cc: "11.0 11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
8 years agonvc0: make sure to delete samplers used by compute shaders
Samuel Pitoiset [Mon, 21 Mar 2016 12:15:44 +0000 (13:15 +0100)]
nvc0: make sure to delete samplers used by compute shaders

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
8 years agoi965/blorp: Make BlitFramebuffer() do sRGB encoding in ES 3.x.
Kenneth Graunke [Thu, 17 Mar 2016 03:19:50 +0000 (20:19 -0700)]
i965/blorp: Make BlitFramebuffer() do sRGB encoding in ES 3.x.

According to the ES 3.0 and GL 4.4 specifications, glBlitFramebuffer
is supposed to perform sRGB decoding and encoding whenever sRGB formats
are in use.  The ES 3.0 specification is completely clear, and has
always stated this.

However, the GL specification has changed behavior in 4.1, 4.2, and
4.4.  The original behavior stated that no sRGB encoding should occur.
The 4.4 behavior matches ES 3.0's wording.  However, implementing the
new behavior appears to break applications such as Left 4 Dead 2.

This patch changes Meta to apply the ES 3.x rules in ES 3.x, but
leaves OpenGL alone for now, to avoid breaking applications.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
8 years agoi965/blorp: Refactor sRGB encoding/decoding.
Kenneth Graunke [Thu, 17 Mar 2016 03:15:52 +0000 (20:15 -0700)]
i965/blorp: Refactor sRGB encoding/decoding.

Because the rules for sRGB are so insane, we change brw_blorp_miptrees
to take decode_srgb and encode_srgb flags, which control linearization
of the source and destination separately.

This should make it easy to implement whatever crazy combination of
rules people throw at us.  For now, it should be equivalent.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
8 years agometa: Make BlitFramebuffer() do sRGB encoding in ES 3.x.
Kenneth Graunke [Tue, 8 Mar 2016 08:34:14 +0000 (00:34 -0800)]
meta: Make BlitFramebuffer() do sRGB encoding in ES 3.x.

According to the ES 3.0 and GL 4.4 specifications, glBlitFramebuffer
is supposed to perform sRGB decoding and encoding whenever sRGB formats
are in use.  The ES 3.0 specification is completely clear, and has
always stated this.

However, the GL specification has changed behavior in 4.1, 4.2, and
4.4.  The original behavior stated that no sRGB encoding should occur.
The 4.4 behavior matches ES 3.0's wording.  However, implementing the
new behavior appears to break applications such as Left 4 Dead 2.

This patch changes Meta to apply the ES 3.x rules in ES 3.x, but
leaves OpenGL alone for now, to avoid breaking applications.

Meta implements several other functions in terms of BlitFramebuffer,
and many of those explicitly do not perform sRGB encoding.  So, this
patch explicitly disables sRGB encoding in those other functions,
preserving the existing (correct) behavior.

If you're from the future and are reading this, hi!  Welcome to
the "fun" of debugging sRGB problems!  Best of luck!

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
8 years agodocs: mark GL_ARB_shader_image_load_store/_size as done for radeonsi
Nicolai Hähnle [Tue, 15 Mar 2016 18:08:21 +0000 (13:08 -0500)]
docs: mark GL_ARB_shader_image_load_store/_size as done for radeonsi

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoradeonsi: Set PIPE_SHADER_CAP_MAX_SHADER_IMAGES
Edward O'Callaghan [Sun, 10 Jan 2016 13:50:32 +0000 (00:50 +1100)]
radeonsi: Set PIPE_SHADER_CAP_MAX_SHADER_IMAGES

This enables ARB_shader_image_load_store and ARB_shader_image_size.

Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
[allow the same number of images for all shader stages and require LLVM 3.9]

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoradeonsi: disable early Z if the fragment shader writes to memory
Nicolai Hähnle [Wed, 16 Mar 2016 01:58:12 +0000 (20:58 -0500)]
radeonsi: disable early Z if the fragment shader writes to memory

Empirically, both the EXEC_ON_* flags and LATE_Z are necessary.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agotgsi/scan: add writes_memory to flag presence of stores or atomics
Nicolai Hähnle [Wed, 16 Mar 2016 01:54:30 +0000 (20:54 -0500)]
tgsi/scan: add writes_memory to flag presence of stores or atomics

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoradeonsi: force the DCC enable bit off in image descriptors for writing (v2)
Nicolai Hähnle [Sun, 13 Mar 2016 19:44:46 +0000 (14:44 -0500)]
radeonsi: force the DCC enable bit off in image descriptors for writing (v2)

This avoids a lockup at least on Tonga.

v2: only force DCC off on VI+ (Marek)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoradeonsi: implement MemoryBarrier (v2)
Nicolai Hähnle [Sun, 13 Mar 2016 16:37:27 +0000 (11:37 -0500)]
radeonsi: implement MemoryBarrier (v2)

v2: invalidate both constant and VMEM/TC L1 for constant buffers (Marek)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoradeonsi: implement volatile memory access
Nicolai Hähnle [Mon, 14 Mar 2016 15:22:21 +0000 (10:22 -0500)]
radeonsi: implement volatile memory access

Prevent loads from being re-ordered or coalesced.

Atomics don't need special handling by definition, and stores don't need
special handling because LLVM is unable to detect dead image or buffer
stores.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoradeonsi: implement coherent memory access (v2)
Nicolai Hähnle [Sun, 13 Mar 2016 02:32:34 +0000 (21:32 -0500)]
radeonsi: implement coherent memory access (v2)

v2: set glc=1 for volatile also on buffers

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoradeonsi: Lower TGSI_OPCODE_MEMBAR down to LLVM op
Nicolai Hähnle [Thu, 10 Mar 2016 23:12:44 +0000 (18:12 -0500)]
radeonsi: Lower TGSI_OPCODE_MEMBAR down to LLVM op

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoradeonsi: Lower TGSI_OPCODE_ATOM* down to LLVM op
Nicolai Hähnle [Fri, 12 Feb 2016 01:54:25 +0000 (20:54 -0500)]
radeonsi: Lower TGSI_OPCODE_ATOM* down to LLVM op

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoradeonsi: Lower TGSI_OPCODE_STORE down to LLVM op
Nicolai Hähnle [Tue, 9 Feb 2016 16:51:31 +0000 (11:51 -0500)]
radeonsi: Lower TGSI_OPCODE_STORE down to LLVM op

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoradeonsi: Lower TGSI_OPCODE_LOAD down to LLVM op (v3)
Nicolai Hähnle [Tue, 9 Feb 2016 15:59:14 +0000 (10:59 -0500)]
radeonsi: Lower TGSI_OPCODE_LOAD down to LLVM op (v3)

v2: new signature style for buffer intrinsics (offsets)
v3: new signature style for llvm.amdgcn.buffer.load.format (overloaded return)

Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v2)
8 years agoradeonsi: extract the LLVM type name construction into its own function
Nicolai Hähnle [Tue, 9 Feb 2016 20:01:35 +0000 (15:01 -0500)]
radeonsi: extract the LLVM type name construction into its own function

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoradeonsi: Lower TGSI_OPCODE_RESQ down to LLVM op
Nicolai Hähnle [Sun, 7 Feb 2016 23:41:09 +0000 (18:41 -0500)]
radeonsi: Lower TGSI_OPCODE_RESQ down to LLVM op

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoradeonsi: extract TXQ buffer size computation into its own function
Nicolai Hähnle [Sun, 7 Feb 2016 22:34:57 +0000 (17:34 -0500)]
radeonsi: extract TXQ buffer size computation into its own function

This will allow it to be reused for RESQ.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoradeonsi: decompress shader images
Nicolai Hähnle [Mon, 8 Feb 2016 03:30:46 +0000 (22:30 -0500)]
radeonsi: decompress shader images

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoradeonsi: update shader image descriptor for invalidated buffer
Nicolai Hähnle [Wed, 16 Mar 2016 03:01:39 +0000 (22:01 -0500)]
radeonsi: update shader image descriptor for invalidated buffer

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoradeonsi: implement set_shader_images (v2)
Nicolai Hähnle [Sat, 6 Feb 2016 23:32:13 +0000 (18:32 -0500)]
radeonsi: implement set_shader_images (v2)

Whether DCC is disabled depends on the access flags with which the image
is bound: image_load supports DCC, but store and atomic don't.

v2: remove an unnecessary masking of images->desc.enabled_mask

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agogallium/radeon: make r600_texture_disable_dcc externally accessible
Nicolai Hähnle [Sat, 12 Mar 2016 00:39:18 +0000 (19:39 -0500)]
gallium/radeon: make r600_texture_disable_dcc externally accessible

We will need it in radeonsi for shader images.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agotgsi/scan: track which shader images are really buffers
Nicolai Hähnle [Sun, 13 Mar 2016 20:06:15 +0000 (15:06 -0500)]
tgsi/scan: track which shader images are really buffers

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agotgsi/scan: add images_writemask
Nicolai Hähnle [Sun, 13 Mar 2016 20:00:40 +0000 (15:00 -0500)]
tgsi/scan: add images_writemask

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agost/mesa: translate additional flags in MemoryBarrier
Nicolai Hähnle [Sun, 13 Mar 2016 16:37:10 +0000 (11:37 -0500)]
st/mesa: translate additional flags in MemoryBarrier

Re-order flags in the order in which they appear in the OpenGL spec in the
description of MemoryBarrier().

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agogallium: add additional PIPE_BARRIER_* bits
Nicolai Hähnle [Sun, 13 Mar 2016 16:36:53 +0000 (11:36 -0500)]
gallium: add additional PIPE_BARRIER_* bits

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agosvga: add svga_winsys_context::pipe_debug_callback pointer
Brian Paul [Wed, 24 Feb 2016 01:02:11 +0000 (18:02 -0700)]
svga: add svga_winsys_context::pipe_debug_callback pointer

The svga winsys modules can use this to send debug messages to the
state tracker and Mesa.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
8 years agosvga: Fix the index buffer rebind regression
Charmaine Lee [Tue, 26 Jan 2016 19:12:09 +0000 (11:12 -0800)]
svga: Fix the index buffer rebind regression

The index buffer handle saved in the hw_state structure could
be invalid after the index buffer is destroyed. Instead of
rebinding the index buffer using the saved index buffer handle,
we will reset the index buffer handle in the hw_state structure
to force resending of the index buffer.

Fixes bug 1593320

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
8 years agosvga: rebind stream output targets
Charmaine Lee [Wed, 20 Jan 2016 18:35:56 +0000 (10:35 -0800)]
svga: rebind stream output targets

To ensure stream output target surfaces are available for the draw commands,
we need to rebind the current stream output targets at the first draw in the
command buffer.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
8 years agosvga: rebind index buffer
Charmaine Lee [Wed, 20 Jan 2016 04:25:39 +0000 (20:25 -0800)]
svga: rebind index buffer

Similar to other resources, current index buffer needs to be
rebound at the first draw of the current command buffer to make
sure the buffer is available for the draw command.

Fixes bug 1587263.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
8 years agosvga: minor formatting fix, comment addition
Brian Paul [Mon, 21 Mar 2016 19:23:04 +0000 (13:23 -0600)]
svga: minor formatting fix, comment addition

To sync with our internal tree.

Signed-off-by: Brian Paul <brianp@vmware.com>
8 years agosvga: optimize constant buffer uploads
Charmaine Lee [Fri, 11 Mar 2016 22:54:36 +0000 (14:54 -0800)]
svga: optimize constant buffer uploads

When a constant buffer slot is allocated in the upload buffer,
the allocated slot size is always in multiple of 256. But the actual buffer
size might not be in multiple of 256. This causes a gap between
the ending offset of a slot and the starting offset of the next slot.
The gap will prevent the two slots to be updated in a single update command.
In order to maximize the chance of merging the contiguous dirty ranges,
when a slot is to be allocated in the constant upload buffer,
specify a buffer size in multiple of 256.

There is about 10% performance improvement with Lightsmark2008 and
30% with Cinebench R11.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
8 years agosvga: add a few more resource updates HUD query
Charmaine Lee [Fri, 11 Mar 2016 22:33:39 +0000 (14:33 -0800)]
svga: add a few more resource updates HUD query

This patch adds the following HUD queries:
.num-resource-updates  -- number of resource update. Commands include
                          UPDATE_SUBRESOURCE, UPDATE_GB_IMAGE.
.num-buffer-uploads    -- number of buffer uploads.
.num-const-buf-updates -- number of set constant buffer.
.num-const-updates     -- number of set shader constant.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
8 years agosvga: add new num-readbacks HUD query
Charmaine Lee [Thu, 10 Mar 2016 18:57:24 +0000 (10:57 -0800)]
svga: add new num-readbacks HUD query

To find out how many image readback command is issued.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
8 years agosvga: use shader sampler view declarations
Brian Paul [Fri, 18 Mar 2016 15:55:57 +0000 (09:55 -0600)]
svga: use shader sampler view declarations

Previously, we looked at the bound textures (via the pipe_sampler_views)
to determine texture dimensions (1D/2D/3D/etc) and datatype (float vs.
int).  But this could fail in out of memory conditions.  If we failed to
allocate a texture and didn't create a pipe_sampler_view, we'd default
to using 0 (PIPE_BUFFER) as the texture type.  This led to device errors
because of inconsistent shader code.

This change relies on all TGSI shaders having an SVIEW declaration for
each SAMP declaration.  The previous patch series does that.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
8 years agogallium/tests: declare sampler views in shaders
Brian Paul [Fri, 18 Mar 2016 20:20:44 +0000 (14:20 -0600)]
gallium/tests: declare sampler views in shaders

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
8 years agogallium/util: declare sampler view in util_make_fs_blit_msaa_depthstencil()
Brian Paul [Fri, 18 Mar 2016 20:20:27 +0000 (14:20 -0600)]
gallium/util: declare sampler view in util_make_fs_blit_msaa_depthstencil()

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
8 years agopostprocess: declare sampler views in shaders
Brian Paul [Fri, 18 Mar 2016 20:20:01 +0000 (14:20 -0600)]
postprocess: declare sampler views in shaders

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
8 years agohud: add sampler view declaration in text fragment shader
Brian Paul [Fri, 18 Mar 2016 20:07:47 +0000 (14:07 -0600)]
hud: add sampler view declaration in text fragment shader

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>