Luke Kenneth Casson Leighton [Fri, 22 Apr 2022 15:12:39 +0000 (16:12 +0100)]
read 2nd word of signature
Luke Kenneth Casson Leighton [Fri, 22 Apr 2022 14:29:59 +0000 (15:29 +0100)]
move hyperram to 0x0000_00000 and 0x2000_0000
to start memory range 0-64mbytes
also document the startup process for arty a7-100t which is a bit arcane
Luke Kenneth Casson Leighton [Fri, 22 Apr 2022 12:49:01 +0000 (13:49 +0100)]
add second hyperram module, for arty-a7,
which does not break things
Luke Kenneth Casson Leighton [Sat, 16 Apr 2022 20:23:38 +0000 (21:23 +0100)]
put versa_ecp5 back to synchronous at 50 mhz to test sync dram
Luke Kenneth Casson Leighton [Sat, 16 Apr 2022 18:56:15 +0000 (19:56 +0100)]
remove stall from WBASyncBridges on master side
leave them on slave side and fake them up (stb&~ack)
Luke Kenneth Casson Leighton [Sat, 16 Apr 2022 16:27:52 +0000 (17:27 +0100)]
get runsimsoc2.sh running again, test asynchronous wb bridge,
found bug in WBAsyncBridge (in soc) where ack signal was not wired up.
v simple
Luke Kenneth Casson Leighton [Sat, 16 Apr 2022 15:38:40 +0000 (16:38 +0100)]
attempting to get VERSA_ECP5 and Icarus Sim to work with ASync Bridge
Luke Kenneth Casson Leighton [Sat, 16 Apr 2022 12:31:55 +0000 (13:31 +0100)]
add in extra delay-for-core in ECP5CRG
actually, it is a separate delay for everything-else-except-the-init domain
which is run at a really slow 25 mhz
Tobias Platen [Sat, 16 Apr 2022 07:44:03 +0000 (09:44 +0200)]
orangecrab: set clock frequency, remove ignored iostandard
Luke Kenneth Casson Leighton [Fri, 15 Apr 2022 22:54:10 +0000 (23:54 +0100)]
comment about UARTResource for orangecrab
Tobias Platen [Fri, 15 Apr 2022 19:38:53 +0000 (21:38 +0200)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/ls2
Tobias Platen [Fri, 15 Apr 2022 19:38:14 +0000 (21:38 +0200)]
add orangecrab uart and toolchain
Luke Kenneth Casson Leighton [Fri, 15 Apr 2022 17:32:56 +0000 (18:32 +0100)]
checking simulation of Async DDR3
Luke Kenneth Casson Leighton [Fri, 15 Apr 2022 16:48:09 +0000 (17:48 +0100)]
work-in-progress
asynchronous DRAM wishbone bridge which is optional when
dram_clk is not requested
Luke Kenneth Casson Leighton [Fri, 15 Apr 2022 15:48:43 +0000 (16:48 +0100)]
reorg of the ECP5 Clock-Reset to be able to add
a 2nd clock (DRAM)
Tobias Platen [Fri, 15 Apr 2022 16:44:27 +0000 (18:44 +0200)]
whitespace
Tobias Platen [Fri, 15 Apr 2022 16:03:57 +0000 (18:03 +0200)]
add orangecrab to list of supported boards
Luke Kenneth Casson Leighton [Thu, 14 Apr 2022 18:45:41 +0000 (19:45 +0100)]
reduce versa_ecp5 clock freq to 50 mhz, reduce bit-width of XICS addressing
Luke Kenneth Casson Leighton [Thu, 14 Apr 2022 15:38:54 +0000 (16:38 +0100)]
add default args in DDR3SoC
Luke Kenneth Casson Leighton [Thu, 14 Apr 2022 15:26:48 +0000 (16:26 +0100)]
put fw_addr back to 0xff00_0000, xics.bin test passed
Luke Kenneth Casson Leighton [Thu, 14 Apr 2022 15:23:31 +0000 (16:23 +0100)]
move firmware to address 0x0 to test microwatt xics.bin
Luke Kenneth Casson Leighton [Thu, 14 Apr 2022 15:16:37 +0000 (16:16 +0100)]
wrap QSPI exploration in SYSCON check for QSPI
Luke Kenneth Casson Leighton [Thu, 14 Apr 2022 14:16:06 +0000 (15:16 +0100)]
add DELAYG to icarus sim
Luke Kenneth Casson Leighton [Thu, 14 Apr 2022 13:42:45 +0000 (14:42 +0100)]
bleh. add XICS_ICS and XICS_ICP but the patch is
a little bigger than expected.
note that a bug ECP5CRG(clk_freq, dram_clk_freq=None, pod_bits=pod_bits)
is also fixed here (whoops)
firstly, the XICS ICP and ICS need adding. but, they are
using make_wb_layout not wishbone.Interface. therefore,
create a wishbone.Interface (sigh) and map the Signals across
one by one (just like with cvtuartbus)
secondly, the incoming IRQs are wired to GenericInterruptController
which is different from how Testissuer does it.
thirdly, eth_macs IRQ number is moved to 1 in order to match with
the Microwatt soc.vhdl
fourthly, uart_irq is set to 0
fifthly, UART16550 and EthMac needed to have their IRQLine
constructed *here* and passed in, otherwise the entire soc repo
becomes dependent on LambdaSoC just for that one import
sixthly, at the same time, DDRSoC has a uart_addr-0xc0002000 added
to match what soc.vhdl does
seventhly, eth0_cfg_addr is moved to 0xc000_c000 to get it out
of the way of XICS_ICP/ICS at 0xc000_4000 and 0xc000_5000
eigthly, xicx icp/ics are added at 0xc000_4000 and 0xc000_5000
totally broke the "one-purpose, one-commit" rule but not entirely
because after all this is "add XICS controller
Luke Kenneth Casson Leighton [Thu, 14 Apr 2022 12:13:23 +0000 (13:13 +0100)]
flash read-and-dump
Luke Kenneth Casson Leighton [Thu, 14 Apr 2022 11:03:12 +0000 (12:03 +0100)]
code-comments for when ASyncBridge is deployed
Luke Kenneth Casson Leighton [Thu, 14 Apr 2022 10:45:43 +0000 (11:45 +0100)]
add new dram_clk_freq argument which does nothing for now
leaves the dramsync/dramsync2x domains as "aliases" for sync/sync2x
but if set, it will create a *second* completely separate domain
at the requested frequency, along with a separate 2x that can then
be used on IOpads with "xdr=4" settings
Luke Kenneth Casson Leighton [Thu, 14 Apr 2022 10:35:30 +0000 (11:35 +0100)]
add an extra domain dramsync2x in preparation for
AsyncBridge
Luke Kenneth Casson Leighton [Thu, 14 Apr 2022 10:24:17 +0000 (11:24 +0100)]
add a dramsync2x domain as well
Luke Kenneth Casson Leighton [Thu, 14 Apr 2022 09:41:06 +0000 (10:41 +0100)]
move 2x-clock-and-dividing into separate function in ECP5 CRG
the reason for this is to make it easy to set up xdr=4x IOpads
which need a *pair* of domains in order to get the 4 phases:
double-freq and freq
Luke Kenneth Casson Leighton [Wed, 13 Apr 2022 12:52:07 +0000 (13:52 +0100)]
annoying, coldboot.bin getting too big to fit into 0x8000 SRAM
really need to increase SRAM size in ls2.py
Luke Kenneth Casson Leighton [Wed, 13 Apr 2022 10:11:57 +0000 (11:11 +0100)]
get microwatt-verilator sim running at different boot base
and confirm working with hello_world recompiled to a different coldboot
start address
Luke Kenneth Casson Leighton [Tue, 12 Apr 2022 13:47:55 +0000 (14:47 +0100)]
GAH jump to start of SPI Flash not the offset *in* SPI
Luke Kenneth Casson Leighton [Tue, 12 Apr 2022 13:22:33 +0000 (14:22 +0100)]
move flash-first-phase-initialisation to separate function
attempting to execute directly from flash by jumping to it
(after making it run a leeetle bit faster than 100 bytes/sec)
Luke Kenneth Casson Leighton [Tue, 12 Apr 2022 13:19:22 +0000 (14:19 +0100)]
make hello_world relocatable with BOOT_INIT_BASE define
Luke Kenneth Casson Leighton [Tue, 12 Apr 2022 11:47:28 +0000 (12:47 +0100)]
add comments on locations where async bridge needs to be added
Luke Kenneth Casson Leighton [Mon, 11 Apr 2022 22:32:27 +0000 (23:32 +0100)]
even more speedup possible on QSPI
Luke Kenneth Casson Leighton [Mon, 11 Apr 2022 22:18:35 +0000 (23:18 +0100)]
hack offset into boot address as well
Luke Kenneth Casson Leighton [Mon, 11 Apr 2022 21:11:50 +0000 (22:11 +0100)]
hmm go back to mtspr for now, also add explicit loading-offset of 0x600000
like there is in the microwatt-verilator work
Luke Kenneth Casson Leighton [Mon, 11 Apr 2022 17:54:32 +0000 (18:54 +0100)]
too big, shift down to 2MB offset
Luke Kenneth Casson Leighton [Mon, 11 Apr 2022 17:49:55 +0000 (18:49 +0100)]
fix coldboot to boot from return address
(head.S does mtctr %r3 then bctr)
move SPI offset to 6 mbytes
(make room in future for boot bitstream)
crank versa_ecp5 freq back to 55 mhz so as to re-activate DDR3
Luke Kenneth Casson Leighton [Mon, 11 Apr 2022 17:11:48 +0000 (18:11 +0100)]
hmm getting flags sorted out on coldboot link
Luke Kenneth Casson Leighton [Mon, 11 Apr 2022 15:54:16 +0000 (16:54 +0100)]
annoying, read from wrong offset in SPI FLASH
Luke Kenneth Casson Leighton [Mon, 11 Apr 2022 15:35:26 +0000 (16:35 +0100)]
make DRAM init conditional on whether it is detected through SYSCON
Luke Kenneth Casson Leighton [Mon, 11 Apr 2022 15:33:02 +0000 (16:33 +0100)]
put versa_ecp5 below 50 mhz as a bodge-way to stop it trying
to create a DDR3 peripheral. this then activates placing an SRAM (BRAM)
at 0x0000_0000 of size 0x8000 which can be used for a micro-test of
booting from QSPI.
and 0x8000 SRAM is much easier to simulate in icarus verilog
Luke Kenneth Casson Leighton [Mon, 11 Apr 2022 15:31:46 +0000 (16:31 +0100)]
set start to _start in hello_world lds script
this causes elf image to get the correct start (execution) address
Luke Kenneth Casson Leighton [Mon, 11 Apr 2022 14:29:06 +0000 (15:29 +0100)]
sigh dump memory *at* address, not address itself
also disable HAS_DRAM check so that copying to BRAM is also fine
Luke Kenneth Casson Leighton [Mon, 11 Apr 2022 13:38:25 +0000 (14:38 +0100)]
dump start of copied memory
Luke Kenneth Casson Leighton [Mon, 11 Apr 2022 13:19:21 +0000 (14:19 +0100)]
speed up QSPI by putting it into way-faster mode
Luke Kenneth Casson Leighton [Sun, 10 Apr 2022 18:26:04 +0000 (19:26 +0100)]
need to merge in tercel flash code
Luke Kenneth Casson Leighton [Sun, 10 Apr 2022 17:15:35 +0000 (18:15 +0100)]
Revert "Wire up missing CRG / DDR3 clock control / reset signals"
This reverts commit
19ed0026e91b2dd351fbd2d692fb2c6f45b42622.
Luke Kenneth Casson Leighton [Sun, 10 Apr 2022 17:15:15 +0000 (18:15 +0100)]
Revert "Put sysclk2x back under system reset control"
This reverts commit
793d05f2ef2e38891a4fb2ffbd6c77631fb86873.
Luke Kenneth Casson Leighton [Sun, 10 Apr 2022 16:30:04 +0000 (17:30 +0100)]
attempting to sort out what looks like a stack overflow
Raptor Engineering Development Team [Sun, 10 Apr 2022 02:15:35 +0000 (21:15 -0500)]
Put sysclk2x back under system reset control
Luke Kenneth Casson Leighton [Sat, 9 Apr 2022 22:06:09 +0000 (23:06 +0100)]
add QSPI dump back in (smaller one) to check it is working
Raptor Engineering Development Team [Sat, 9 Apr 2022 20:06:12 +0000 (15:06 -0500)]
Wire up missing CRG / DDR3 clock control / reset signals
Luke Kenneth Casson Leighton [Sat, 9 Apr 2022 14:21:52 +0000 (15:21 +0100)]
sigh use MEMORY_BASE which is at 0x0000_0000 and coincides with DRAM_BASE
Luke Kenneth Casson Leighton [Sat, 9 Apr 2022 13:02:01 +0000 (14:02 +0100)]
shuffle addresses around a bit
* firmware ROM is at 0xff00_0000
* DRAM is at 0x0000_0000
* for no real reason if DRAM is not present at 0x0 an SRAM is added
* set the default coldboot compile-start address at 0xff00_0000
Luke Kenneth Casson Leighton [Fri, 8 Apr 2022 20:34:08 +0000 (21:34 +0100)]
add DRAM offset into SYSCON and jump to DRAM if flash successfully
returns an offset after copy
Luke Kenneth Casson Leighton [Fri, 8 Apr 2022 20:09:20 +0000 (21:09 +0100)]
add ELF reading to coldboot.c, move spi address to 0xf000_000
and add spi read-offset to Microwatt SYSCON
Luke Kenneth Casson Leighton [Fri, 8 Apr 2022 17:46:12 +0000 (18:46 +0100)]
add read of SYSCON and entry for SPIFlash
Luke Kenneth Casson Leighton [Fri, 8 Apr 2022 14:53:29 +0000 (15:53 +0100)]
up the delay-time on ddr3 reset, put loop around dram init just for fun
Luke Kenneth Casson Leighton [Fri, 8 Apr 2022 11:54:05 +0000 (12:54 +0100)]
comment/80-char limit
Raptor Engineering Development Team [Thu, 7 Apr 2022 21:36:51 +0000 (16:36 -0500)]
Update coldboot DDR3 init firmware to work with latest gram changes
Raptor Engineering Development Team [Thu, 7 Apr 2022 21:33:51 +0000 (16:33 -0500)]
Add an asm dump with source to the coldboot makefile
Clean all files, including libgram files, when running
make clean
Raptor Engineering Development Team [Thu, 7 Apr 2022 21:33:18 +0000 (16:33 -0500)]
Enable DDR3 using a 50MHz clock on Versa 85
Raptor Engineering Development Team [Thu, 7 Apr 2022 21:32:53 +0000 (16:32 -0500)]
Move simulation HyperRAM pins off of DDR3 pins
Raptor Engineering Development Team [Thu, 7 Apr 2022 21:32:18 +0000 (16:32 -0500)]
Fix DRAM simulation commands
Luke Kenneth Casson Leighton [Wed, 6 Apr 2022 11:28:03 +0000 (12:28 +0100)]
add QSPI support to arty_a7
Luke Kenneth Casson Leighton [Mon, 4 Apr 2022 19:14:10 +0000 (20:14 +0100)]
allow setting individual directions on QSPI dq0-dq3
Luke Kenneth Casson Leighton [Mon, 4 Apr 2022 17:14:46 +0000 (18:14 +0100)]
write out firmware to correct location,
adapt to 64/32 bit output
Luke Kenneth Casson Leighton [Mon, 4 Apr 2022 17:09:26 +0000 (18:09 +0100)]
sigh put firmware.hex qspi file in correct place
Luke Kenneth Casson Leighton [Mon, 4 Apr 2022 17:08:59 +0000 (18:08 +0100)]
increase power-on-delay for icarus sim to allow reset to occur
Luke Kenneth Casson Leighton [Mon, 4 Apr 2022 16:25:44 +0000 (17:25 +0100)]
re-enable build of firmware in sim
Luke Kenneth Casson Leighton [Mon, 4 Apr 2022 16:11:46 +0000 (17:11 +0100)]
disable ethmac for now, pass firmware.hex to cypress qspi model
Luke Kenneth Casson Leighton [Sun, 3 Apr 2022 10:23:46 +0000 (11:23 +0100)]
redo start address of firmware so it can be specified -DBOOT_INIT_BASE
Raptor Engineering Development Team [Mon, 4 Apr 2022 16:06:51 +0000 (11:06 -0500)]
Fix SPI device simulation model MISO/MOSI wiring
Raptor Engineering Development Team [Sat, 2 Apr 2022 21:53:56 +0000 (16:53 -0500)]
Add 10/100 MAC pins for Versa boards and enable MAC
Tested to not interfere with main SoC in simulation,
not tested further at this point.
Luke Kenneth Casson Leighton [Thu, 31 Mar 2022 13:42:53 +0000 (14:42 +0100)]
reduce number of params obtained on QSPI for icarus sim
Luke Kenneth Casson Leighton [Thu, 31 Mar 2022 13:31:08 +0000 (14:31 +0100)]
got icarus verilog model of QSPI working and it returns the same
FFFFFFF
Luke Kenneth Casson Leighton [Thu, 31 Mar 2022 09:02:39 +0000 (10:02 +0100)]
whitespace cleanup
Raptor Engineering Development Team [Thu, 31 Mar 2022 07:39:31 +0000 (02:39 -0500)]
Fix Tercel QSPI master connections
Tested to work on Raptor Versa 85 custom board
in both word and byte mode.
Luke Kenneth Casson Leighton [Thu, 31 Mar 2022 01:31:37 +0000 (02:31 +0100)]
remove {err} feature from Tercel
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 19:43:58 +0000 (20:43 +0100)]
add err wishbone feature to Tercel
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 19:43:44 +0000 (20:43 +0100)]
add config-dump from SPI
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 19:40:27 +0000 (20:40 +0100)]
remove clk from spi_flash,
change cs_n to cs,
de-bork WB access with stall=cyc&~ack thing
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 12:45:51 +0000 (13:45 +0100)]
add qspi module to arty_a7
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 12:45:32 +0000 (13:45 +0100)]
quick-and-dirty QSPI read test
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 12:32:35 +0000 (13:32 +0100)]
use nmigen_boards naming conventions for SPIFlash
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 11:52:11 +0000 (12:52 +0100)]
update comments, link/setup of peripherals
(all done manually at the moment, TODO a dev-env-setup)
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 11:46:57 +0000 (12:46 +0100)]
add TODO comments about using platform.add_resources
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 11:00:54 +0000 (12:00 +0100)]
whitespace cleanup, 80 char limit
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 10:58:32 +0000 (11:58 +0100)]
add patch for n25q to fix model using fork/join, should be begin/end
Raptor Engineering Development Team [Tue, 29 Mar 2022 01:11:43 +0000 (20:11 -0500)]
Add initial integration for OpenCores 10/100 Ethernet MAC
Raptor Engineering Development Team [Mon, 28 Mar 2022 15:58:23 +0000 (10:58 -0500)]
Fix instructions in comment
Luke Kenneth Casson Leighton [Mon, 28 Mar 2022 14:16:45 +0000 (15:16 +0100)]
quick memory test increasing by power-2 each time shows all 32 mbytes of
hyperram ICs are accessible
Luke Kenneth Casson Leighton [Sun, 27 Mar 2022 15:32:15 +0000 (16:32 +0100)]
set reset from ResetSignal not straight to 1 for HyperRAM
put correct IOPad names into HyperRAMResource for arty a7
Luke Kenneth Casson Leighton [Sun, 27 Mar 2022 12:21:48 +0000 (13:21 +0100)]
try latency of 7 for winbond hyperram
Luke Kenneth Casson Leighton [Sun, 27 Mar 2022 12:21:25 +0000 (13:21 +0100)]
add link to Winbond HyperRAM model
Luke Kenneth Casson Leighton [Sun, 27 Mar 2022 11:07:50 +0000 (12:07 +0100)]
set upper CSns on HyperRAM to zero and set reset_n HI
fix CSn pin-pad names