mesa.git
6 years agost/mesa: Use Array._DrawVAO in st_atom_array.c.
Mathias Fröhlich [Sun, 1 Apr 2018 18:18:36 +0000 (20:18 +0200)]
st/mesa: Use Array._DrawVAO in st_atom_array.c.

Finally make use of the binding information in the VAO when
setting up arrays for draw.

v2: Emit less relocations also for interleaved userspace arrays.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
6 years agost/mesa: Make the input_to_index array available.
Mathias Fröhlich [Sun, 1 Apr 2018 18:18:36 +0000 (20:18 +0200)]
st/mesa: Make the input_to_index array available.

The input_to_index array is already available internally
when preparing vertex programs. Store the map in
struct st_vertex_program.
Also store the bitmask of mesa vertex processing inputs in
struct st_vp_variant.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
6 years agost/mesa: Use _DrawVAO for edgeflag enabled check.
Mathias Fröhlich [Sun, 1 Apr 2018 18:18:36 +0000 (20:18 +0200)]
st/mesa: Use _DrawVAO for edgeflag enabled check.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
6 years agomesa: Compute effective buffer bindings in the vao.
Mathias Fröhlich [Sun, 1 Apr 2018 18:18:36 +0000 (20:18 +0200)]
mesa: Compute effective buffer bindings in the vao.

Compute VAO buffer binding information past the position/generic0 mapping.
Scan for duplicate buffer bindings and collapse them into derived
effective buffer binding index and effective attribute mask variables.
Provide a set of helper functions to access the distilled
information in the VAO. All of them prefixed with _mesa_draw_...
to indicate that they are meant to query draw information.

v2: Also group user space arrays containing interleaved arrays.
    Add _Eff*Offset to be copied on attribute and binding copy.
    Update comments.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
6 years agovirgl: Add support for passing GL_ANY_SAMPLES_PASSED_CONSERVATIVE
Gert Wollny [Wed, 9 May 2018 14:51:49 +0000 (16:51 +0200)]
virgl: Add support for passing GL_ANY_SAMPLES_PASSED_CONSERVATIVE

This is needed for fixing CTS:
   dEQP-GLES3.functional.occlusion_query.conservative*

Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
6 years agor600: fix constant buffer bounds.
Dave Airlie [Wed, 9 May 2018 22:17:09 +0000 (23:17 +0100)]
r600: fix constant buffer bounds.

If you have an indirect access to a constant buffer on r600/eg
use a vertex fetch in the shader. However apps have expected
behaviour on those out of bounds accessess (even if illegal).

If the constants were being uploaded as part of a larger
upload buffer, we'd set the range of allowed access to a lot
larger than required so apps would get values back from
other parts of the upload buffer instead of the expected out
of bounds access.

This fixes rendering bugs in Trine and Witcher 1, thanks
to iive for nagging me effectively until I figured it out :-)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91808
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
6 years agoi965,anv: Set the CS stall bit on the ISP disable PIPE_CONTROL
Jason Ekstrand [Wed, 9 May 2018 22:06:13 +0000 (15:06 -0700)]
i965,anv: Set the CS stall bit on the ISP disable PIPE_CONTROL

From the bspec docs for "Indirect State Pointers Disable":

    "At the completion of the post-sync operation associated with this
    pipe control packet, the indirect state pointers in the hardware are
    considered invalid"

So the ISP disable is a post-sync type of operation which means that it
should be combined with a CS stall.  Without this, the simulator throws
an error.

Fixes: 766d801ca "anv: emit pixel scoreboard stall before ISP disable"
Fixes: f536097f6 "i965: require pixel scoreboard stall prior to ISP disable"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
6 years agoradv: handle arrays in the fmask descriptor.
Dave Airlie [Mon, 19 Mar 2018 07:13:46 +0000 (07:13 +0000)]
radv: handle arrays in the fmask descriptor.

This fixes the fmask descriptor generation to handle 2d ms arrays.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agogallium/tests: Fix assignment of EXTRA_DIST
Matt Turner [Wed, 9 May 2018 23:36:58 +0000 (16:36 -0700)]
gallium/tests: Fix assignment of EXTRA_DIST

Fixes: 6754c2e83d79 ("autotools: Include new meson files")
6 years agoconfigure.ac: Check for grep with AC_PROG_GREP
Matt Turner [Wed, 9 May 2018 23:32:12 +0000 (16:32 -0700)]
configure.ac: Check for grep with AC_PROG_GREP

Perhaps with a new version of autoconf, I began seeing:

| checking the name lister (/usr/bin/nm -B) interface... ./configure: line 6973: External.*some_variable: command not found
| BSD nm

This is because AC_PROG_NM expands to

...
if $GREP 'External.*some_variable' conftest.out > /dev/null; then
    lt_cv_nm_interface="MS dumpbin"
fi
...

I'm not sure if it's a bug in AC_PROG_NM that it doesn't call
AC_PROG_GREP, but it's easy enough for us to do it.

6 years agomain: fail texture_storage() call if the size is not okay
Xiong, James [Fri, 27 Apr 2018 15:34:47 +0000 (08:34 -0700)]
main: fail texture_storage() call if the size is not okay

Signed-off-by: Xiong, James <james.xiong@intel.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agomain: return 0 length when the queried program object's not linked
Xiong, James [Fri, 27 Apr 2018 01:39:57 +0000 (18:39 -0700)]
main: return 0 length when the queried program object's not linked

Signed-off-by: Xiong, James <james.xiong@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
6 years agoi965: Shut up unused variable warnings.
Kenneth Graunke [Wed, 9 May 2018 23:20:50 +0000 (16:20 -0700)]
i965: Shut up unused variable warnings.

These are only used in assertions.

6 years agosrc/intel/Makefile.vulkan.am: add missing MKDIR_GEN
Ross Burton [Wed, 9 May 2018 20:48:43 +0000 (21:48 +0100)]
src/intel/Makefile.vulkan.am: add missing MKDIR_GEN

Out of tree builds can try to write into a directory that doesn't exist yet:

| Traceback (most recent call last):
|   File "../../../mesa-18.0.2/src/intel/vulkan/anv_icd.py", line 46, in <module>
|     with open(args.out, 'w') as f:
| IOError: [Errno 2] No such file or directory: 'vulkan/intel_icd.x86_64.json'
| Makefile:4882: recipe for target 'vulkan/intel_icd.x86_64.json' failed

Add missing MKDIR_GEN calls to solve this.

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
6 years agomesa: fix error handling in get_framebuffer_parameteriv
Rhys Perry [Fri, 4 May 2018 22:27:51 +0000 (23:27 +0100)]
mesa: fix error handling in get_framebuffer_parameteriv

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
6 years agoanv: emit pixel scoreboard stall before ISP disable
Lionel Landwerlin [Tue, 8 May 2018 16:25:55 +0000 (17:25 +0100)]
anv: emit pixel scoreboard stall before ISP disable

We want to make sure that all indirect state data has been loaded into
the EUs before disable the pointers.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Fixes: 78c125af3904c ("anv/gen10: Ignore push constant packets during context restore.")
6 years agoi965: require pixel scoreboard stall prior to ISP disable
Lionel Landwerlin [Tue, 1 May 2018 11:32:45 +0000 (12:32 +0100)]
i965: require pixel scoreboard stall prior to ISP disable

Invalidating the indirect state pointers might affect a previously
scheduled & still running 3DPRIMITIVE (causing page fault). So stall
on pixel scoreboard before that.

v2: Fix compile issue :(

v3: Stall on pixel scoreboard

v4: Drop the post sync operation (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Fixes: ca19ee33d7d39 ("i965/gen10: Ignore push constant packets during context restore.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106243

6 years agointel/isl: Allow CCS_E on 1010102 formats
Jason Ekstrand [Fri, 26 Jan 2018 19:43:24 +0000 (11:43 -0800)]
intel/isl: Allow CCS_E on 1010102 formats

On CNL and above, CCS_E supports 1010102 formats and R11G11B10F.  We had
shut them off during early enabling because blorp_copy couldn't handle
them.  Now it can handle 1010102 formats so we can turn them back on.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/blorp: Allow CCS copies of 1010102 formats
Jason Ekstrand [Fri, 26 Jan 2018 19:42:35 +0000 (11:42 -0800)]
intel/blorp: Allow CCS copies of 1010102 formats

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/blorp: Add support for more format bitcasting
Jason Ekstrand [Fri, 26 Jan 2018 19:41:02 +0000 (11:41 -0800)]
intel/blorp: Add support for more format bitcasting

nir_format_bitcast_uint_vec_unmasked can only be used to cast between
formats with uniform channel sizes.  In particular, it cannot handle
10_10_10_2 formats.  By making use of the NIR helper for uint vector
casts, we should now be able to bitcast between any two uint formats so
long as their channels are in RGBA order (possibly with channels
missing).  In order to do this we need to rework the key a bit to pass
the actual formats instead of just the number of bits in each.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/blorp: Use nir_format_bitcast_uint_vec_unmasked
Jason Ekstrand [Fri, 26 Jan 2018 19:35:04 +0000 (11:35 -0800)]
intel/blorp: Use nir_format_bitcast_uint_vec_unmasked

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agonir/format_convert: Add code for bitcasting vectors
Jason Ekstrand [Fri, 26 Jan 2018 19:34:04 +0000 (11:34 -0800)]
nir/format_convert: Add code for bitcasting vectors

This is a fairly direct port from blorp.  The only real change is that
the nir_format_convert version doesn't assume that everything is a vec4.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/blorp: Use ISL instead of bitcast_color_value_to_uint
Jason Ekstrand [Fri, 26 Jan 2018 18:44:51 +0000 (10:44 -0800)]
intel/blorp: Use ISL instead of bitcast_color_value_to_uint

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/isl: Add format conversion code
Jason Ekstrand [Fri, 23 Jun 2017 01:45:24 +0000 (18:45 -0700)]
intel/isl: Add format conversion code

This adds helpers to ISL to convert an isl_color_value to and from
binary data encoded with a given isl_format.  The conversion is done
using ISL's built-in format introspection so it's fairly slow as format
conversions go but it should be fine for a single pixel value.  In
particular, we can use this to convert clear colors.

As a side-effect, we now rely on the sRGB helpers in libmesautil so we
need to tweak the build system a bit.  All prior uses of src/util in ISL
were header-only.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/isl/format: Get rid of the ALPHA colorspace
Jason Ekstrand [Fri, 23 Jun 2017 06:18:06 +0000 (23:18 -0700)]
intel/isl/format: Get rid of the ALPHA colorspace

Alpha-only formats are just linear.  There's no need to specially
deliminate them as being in their own colorspace.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/isl/format: Add field locations informations to channel_layout
Jason Ekstrand [Fri, 23 Jun 2017 00:12:36 +0000 (17:12 -0700)]
intel/isl/format: Add field locations informations to channel_layout

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/isl/format: Add a column for channel order to the table
Jason Ekstrand [Thu, 22 Jun 2017 23:52:56 +0000 (16:52 -0700)]
intel/isl/format: Add a column for channel order to the table

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agoi965/blorp: Remove a pile of blorp_blit restrictions
Jason Ekstrand [Sat, 21 Jan 2017 06:36:30 +0000 (22:36 -0800)]
i965/blorp: Remove a pile of blorp_blit restrictions

Previously, blorp could only blit into something that was renderable.
Thanks to recent additions to blorp, it can now blit into basically
anything so long as it isn't compressed.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agoi965/blorp: Allow blorp blits for 16x MSAA
Jason Ekstrand [Wed, 9 May 2018 16:48:29 +0000 (09:48 -0700)]
i965/blorp: Allow blorp blits for 16x MSAA

BLORP has supported 16x MSAA for quite a while now, we just never
bothered to enable it for CopyTexSubImage.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agoanv: Allow blitting to/from any supported format
Jason Ekstrand [Sat, 21 Jan 2017 19:30:40 +0000 (11:30 -0800)]
anv: Allow blitting to/from any supported format

Now that blorp handles all the cases, why not?  The only real change we
have to make is to stop using anv_swizzle_for_render() in blorp_blit
because it doesn't work for B4G4R4A4 and blorp now natively handles that.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/blorp: Support the RGB workaround on more formats
Jason Ekstrand [Sat, 21 Jan 2017 18:53:12 +0000 (10:53 -0800)]
intel/blorp: Support the RGB workaround on more formats

Previously we only supported UINT formats because that's what blorp_copy
required.  If we want to use it in blorp_blit, however, we need to
support everything.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/blorp: Silently convert RGBX destination formats to RGBA
Jason Ekstrand [Sat, 21 Jan 2017 17:34:44 +0000 (09:34 -0800)]
intel/blorp: Silently convert RGBX destination formats to RGBA

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/isl: Add some helpers for working with RGBX formats
Jason Ekstrand [Sat, 21 Jan 2017 17:24:26 +0000 (09:24 -0800)]
intel/isl: Add some helpers for working with RGBX formats

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/blorp: Handle more exotic destination formats
Jason Ekstrand [Sat, 21 Jan 2017 06:12:06 +0000 (22:12 -0800)]
intel/blorp: Handle more exotic destination formats

This commit adds support for the following formats as destination
formats even though the hardware does not support rendering to them:

 - ISL_FORMAT_R24_UNORM_X8_TYPELESS
 - ISL_FORMAT_A4B4G4R4_UNORM
 - ISL_FORMAT_L8_UNORM_SRGB
 - ISL_FORMAT_R9G9B9E5_SHAREDEXP

This is done by using a different format and emitting shader code to
fake it the rest of the way.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/blorp: Include nir_format_convert.h in blorp_blit.c
Jason Ekstrand [Fri, 26 Jan 2018 07:01:40 +0000 (23:01 -0800)]
intel/blorp: Include nir_format_convert.h in blorp_blit.c

nir_mask_shift_or is now defined in nir_format_convert.h so we can
delete the copy in blorp_blit.c.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agonir/format_convert: Add a function to pack RGB9_E5 formats
Jason Ekstrand [Fri, 26 Jan 2018 07:06:11 +0000 (23:06 -0800)]
nir/format_convert: Add a function to pack RGB9_E5 formats

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agonir/format_convert: Add pack/unpack for R11F_G11F_B10F
Jason Ekstrand [Fri, 26 Jan 2018 06:32:16 +0000 (22:32 -0800)]
nir/format_convert: Add pack/unpack for R11F_G11F_B10F

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agonir/format_convert: Add linear <-> sRGB helpers
Jason Ekstrand [Fri, 26 Jan 2018 06:52:37 +0000 (22:52 -0800)]
nir/format_convert: Add linear <-> sRGB helpers

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agonir: Add the start of a format conversion helper header
Jason Ekstrand [Fri, 20 Oct 2017 16:35:48 +0000 (09:35 -0700)]
nir: Add the start of a format conversion helper header

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/blorp: Add swizzle support for all hardware
Jason Ekstrand [Thu, 9 Feb 2017 02:00:05 +0000 (18:00 -0800)]
intel/blorp: Add swizzle support for all hardware

This commit makes blorp capable of swizzling anything even on hardware
that doesn't support texture swizzle.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/isl: Add a helper for inverting swizzles
Jason Ekstrand [Thu, 9 Feb 2017 01:59:43 +0000 (17:59 -0800)]
intel/isl: Add a helper for inverting swizzles

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agointel/isl: Add a helper for composing swizzles
Jason Ekstrand [Tue, 7 Feb 2017 17:14:46 +0000 (09:14 -0800)]
intel/isl: Add a helper for composing swizzles

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agointel/isl: Add an isl_swizzle_supports_rendering helper
Jason Ekstrand [Thu, 9 Feb 2017 01:21:54 +0000 (17:21 -0800)]
intel/isl: Add an isl_swizzle_supports_rendering helper

This helper encodes more details, specifically about Haswell, than the
previous asserts in isl_surface_state.c.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoi965/surface_state: Use an identity swizzle pre-Haswell
Jason Ekstrand [Thu, 9 Feb 2017 22:50:01 +0000 (14:50 -0800)]
i965/surface_state: Use an identity swizzle pre-Haswell

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoblorp: Handle the RGB workaround more like other workarounds
Jason Ekstrand [Sat, 21 Jan 2017 15:59:56 +0000 (07:59 -0800)]
blorp: Handle the RGB workaround more like other workarounds

The previous version was sort-of strapped on in that it just adjusted
the blit rectangle and trusted in the fact that we would use texelFetch
and round to the nearest integer to ensure that the component positions
matched.  This new version, while slightly more complicated, is more
accurate because all three components end up with exactly the same
dst_pos and so they will get interpolated and sampled at the same
texture coordinate.  This makes the workaround suitable for using with
scaled blits.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
6 years agoi965: silence unused variable
Lionel Landwerlin [Wed, 9 May 2018 15:40:37 +0000 (16:40 +0100)]
i965: silence unused variable

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 2dc29e095f9da ("i965: Don't leak blorp on Gen4-5.")
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
6 years agointel: devinfo: silence coverity warning
Lionel Landwerlin [Wed, 9 May 2018 14:08:03 +0000 (15:08 +0100)]
intel: devinfo: silence coverity warning

It's just not possible to have a device with no subslices.

CID: 1433511
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
6 years agodri3: Only update number of back buffers in loader_dri3_get_buffers
Michel Dänzer [Fri, 27 Apr 2018 15:41:48 +0000 (17:41 +0200)]
dri3: Only update number of back buffers in loader_dri3_get_buffers

And only free no longer needed back buffers there as well.

We want to stick to the same back buffer throughout a frame, otherwise
we can run into various issues.

Bugzilla: https://bugs.freedesktop.org/105906
Bugzilla: https://bugs.freedesktop.org/106399
Fixes: 3160cb86aa92 "egl/x11: Re-allocate buffers if format is suboptimal"
Reported-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Tested-by: Eero Tamminen <eero.t.tamminen@intel.com>
Acked-by: Daniel Stone <daniels@collabora.com>
6 years agoanv: ignore pColorBlendState if all color attachments of the subpass are unused
Samuel Iglesias Gonsálvez [Mon, 7 May 2018 06:42:56 +0000 (08:42 +0200)]
anv: ignore pColorBlendState if all color attachments of the subpass are unused

According to Vulkan spec:

  "pColorBlendState is a pointer to an instance of the
   VkPipelineColorBlendStateCreateInfo structure, and is ignored if the
   pipeline has rasterization disabled or if the subpass of the render pass the
   pipeline is created against does not use any color attachments."

Fixes tests from CL#2505:

   dEQP-VK.renderpass.*.simple.color_unused_omit_blend_state

v2:
- Check that blend is not NULL before usage.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agomesa: remove hard-coded OpenGL 3.2 compat limit
Timothy Arceri [Tue, 8 May 2018 00:35:40 +0000 (10:35 +1000)]
mesa: remove hard-coded OpenGL 3.2 compat limit

Just let validate_context_version() do it instead. This fixes
MESA_GL_VERSION_OVERRIDE for compat, it will also allow us to
enable new compat versions on a per driver bases in future.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
6 years agomesa: add GLSLVersionCompat constant
Timothy Arceri [Tue, 8 May 2018 00:10:39 +0000 (10:10 +1000)]
mesa: add GLSLVersionCompat constant

This allows drivers to define what version of GLSL they support
in compat. This will be needed in order to support compat 3.2
without breaking drivers that wont support it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
6 years agomesa: dont call _mesa_override_glsl_version() in _mesa_init_constants()
Timothy Arceri [Mon, 7 May 2018 23:22:41 +0000 (09:22 +1000)]
mesa: dont call _mesa_override_glsl_version() in _mesa_init_constants()

All drivers that support GLSL will later set their default GLSL versions
overriding this override call. They currently all call
 _mesa_override_glsl_version() again later in order to support overrides.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
6 years agomesa: dont set GLSLVersion in _mesa_init_constants()
Timothy Arceri [Mon, 7 May 2018 23:19:04 +0000 (09:19 +1000)]
mesa: dont set GLSLVersion in _mesa_init_constants()

Just leave it as 0 and let the drivers set it (as they already do)
to avoid redundantly initialising it.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
6 years agopipe-loader: Free driver_name in error path
Jan Vesely [Tue, 8 May 2018 03:40:47 +0000 (23:40 -0400)]
pipe-loader: Free driver_name in error path

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
6 years agoglsl: change ast_type_qualifier bitset size to work around GCC 5.4 bug
Brian Paul [Tue, 8 May 2018 14:24:21 +0000 (08:24 -0600)]
glsl: change ast_type_qualifier bitset size to work around GCC 5.4 bug

Change the size of the bitset from 128 bits to 96.  This works around an
apparent GCC 5.4 bug in which bad SSE code is generated, leading to a
crash in ast_type_qualifier::validate_in_qualifier() (ast_type.cpp:654).

This can be repro'd with the Piglit test tests/spec/glsl-1.50/execution/
varying-struct-basic-gs-fs.shader_test

Bugzilla:https://bugs.freedesktop.org/show_bug.cgi?id=105497
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Tested-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
6 years agoi965: Dump validation list on INTEL_DEBUG=bat,submit.
Kenneth Graunke [Tue, 10 Apr 2018 08:19:55 +0000 (01:19 -0700)]
i965: Dump validation list on INTEL_DEBUG=bat,submit.

This is really useful when debugging any sort of buffer management
issues, so just printing it during INTEL_DEBUG=bat,submit seems
reasonable.  With bat, we're already spamming so much output that
it doesn't really hurt.  With submit, it's still easy to grep for
the older information, and the new information is nice too.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
6 years agoi965/miptree: Remove redundant fields from intel_miptree_aux_buffer
Jason Ekstrand [Fri, 4 May 2018 23:49:47 +0000 (16:49 -0700)]
i965/miptree: Remove redundant fields from intel_miptree_aux_buffer

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoi965: Simplify brw_emit_depthbuffer and brw_emit_depth_stencil_hiz
Jason Ekstrand [Sat, 5 May 2018 05:57:09 +0000 (22:57 -0700)]
i965: Simplify brw_emit_depthbuffer and brw_emit_depth_stencil_hiz

Now that we're using ISL, a good chunk of brw_emit_depthstencil is
pointless checks which ISL will do for us anyway.  Since we only have
one manual depth buffer emit function, move the useful bits into it.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoi965: Move brw_emit_depth_stencil_hiz higher up in the file
Jason Ekstrand [Sat, 5 May 2018 05:46:49 +0000 (22:46 -0700)]
i965: Move brw_emit_depth_stencil_hiz higher up in the file

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoi965: Use ISL for emitting depth/stencil/hiz state on gen6+
Jason Ekstrand [Sat, 5 May 2018 05:32:24 +0000 (22:32 -0700)]
i965: Use ISL for emitting depth/stencil/hiz state on gen6+

We leave gen4-5 alone because the ISL code hasn't really been well-
tested on gen4-5 or with combined depth-stencil because we don't use
BLORP for depth operations on gen4-5.  Also, the gen4-5 code has to deal
with intratile offsets for LOD hacks and ISL doesn't handle those yet.
We could make ISL handle gen4-5 capable or we could just not bother.

Among other things, this should make future platform enabling easier
because it means we don't have to update multiple (or hand-rolled!)
depth stencil emit paths.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoi965: Use the brw_depthbuffer atom on all gens
Jason Ekstrand [Sat, 5 May 2018 05:41:19 +0000 (22:41 -0700)]
i965: Use the brw_depthbuffer atom on all gens

The only reason why we had two atoms was that the one we used for gen7+
depended on _NEW_DEPTH and _NEW_STENCIL as well as _NEW_BUFFERS.  Since
this is no longer true, we can combine them into one atom.  We do add a
dependence on BRW_NEW_AUX_STATE but that should never get set on gen4-5
so adding it is a no-op for those platforms.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoi965: Always set depth/stencil write enables on gen7+
Jason Ekstrand [Mon, 7 May 2018 17:57:49 +0000 (10:57 -0700)]
i965: Always set depth/stencil write enables on gen7+

The hardware will AND these fields with the corresponding fields in
DEPTH_STENCIL_STATE so there's no real reason to toggle them on and off
based on state bits.  This removes our reliance on the _NEW_DEPTH and
_NEW_STENCIL state bits and better matches what ISL does.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoi965: Re-order depth/stencil/hiz/clear packets to match ISL
Jason Ekstrand [Sat, 5 May 2018 19:35:01 +0000 (12:35 -0700)]
i965: Re-order depth/stencil/hiz/clear packets to match ISL

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoi965: Re-emit depth/stencil/hiz on BRW_NEW_AUX_STATE
Jason Ekstrand [Sat, 5 May 2018 19:48:54 +0000 (12:48 -0700)]
i965: Re-emit depth/stencil/hiz on BRW_NEW_AUX_STATE

Certain things can change the aux usage or fast clear color of a depth
surface and we want to re-emit if that happens.  For instance, if you do
a fast depth clear of an already clear depth surface, we will just set
the clear color and not do anything else.  In that case, we could fail
to re-emit 3DSTATE_CLEAR_PARAMS and not get the new fast-clear color.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agointel: devinfo: fix assertion on devices with odd number of EUs
Lionel Landwerlin [Mon, 23 Apr 2018 16:52:37 +0000 (17:52 +0100)]
intel: devinfo: fix assertion on devices with odd number of EUs

I forgot to change the assert in the second helper function in a
previous change.

This hit the assert() on a Broadwell platform with 1 slice, 3
subslices but all EUs disabled in subslice 1 & 2.

Fixes: c1900f5b0fb ("intel: devinfo: add helper functions to fill fusing masks values")
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agovulkan/wsi: Only use LINEAR modifier for prime if supported.
Bas Nieuwenhuizen [Sat, 5 May 2018 13:34:44 +0000 (15:34 +0200)]
vulkan/wsi: Only use LINEAR modifier for prime if supported.

This was setting the LINEAR modifier if neither the
X server nor the driver supported modifiers.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106180
Fixes: c80c08e226 "vulkan/wsi/x11: Add support for DRI3 v1.2"
CC: 18.1 <mesa-stable@lists.freedesktop.org>
Tested-by: Abel Garcia Dorta <mercuriete@gmail.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agoeg/compute: Drop reference to kernel_param bo in destructor
Jan Vesely [Tue, 8 May 2018 02:54:09 +0000 (22:54 -0400)]
eg/compute: Drop reference to kernel_param bo in destructor

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
6 years agor600: Cleanup constant buffers on context destruction
Jan Vesely [Tue, 8 May 2018 02:52:19 +0000 (22:52 -0400)]
r600: Cleanup constant buffers on context destruction

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
6 years agomesa/formatquery: remove online compression check on is_resource_supported
Alejandro Piñeiro [Fri, 4 May 2018 14:44:44 +0000 (16:44 +0200)]
mesa/formatquery: remove online compression check on is_resource_supported

is_resource_supported returns if the combination of
target/internalformat is supported in at least one operation. Online
compression is only mandatory for glTexImage2D. Some formats doesn't
support online compression, but can be used in any case, with
glCompressed*D methods.

Without this commit, ETC2 internalformats were returning FALSE, even
for the drivers supporting it. So any other query (like
TEXTURE_COMPRESSED) was returning FALSE/NONE instead of the proper
value.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
6 years agointel/genxml: Assert that genxml field start and ends are sane.
Kenneth Graunke [Mon, 7 May 2018 18:14:42 +0000 (11:14 -0700)]
intel/genxml: Assert that genxml field start and ends are sane.

Chris recently fixed a bunch of genxml end < start bugs, as well as
booleans that are wider than a bit.  These are way too easy to write, so
asserting that the fields are sane is a good plan.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agointel/genxml: Fix some more fake booleans in genxml.
Kenneth Graunke [Mon, 7 May 2018 18:40:24 +0000 (11:40 -0700)]
intel/genxml: Fix some more fake booleans in genxml.

None of these are actually booleans.  Tile Parameter is a tiling mode
enum.  Display pipes take plane numbers.  Predicate Enable has some
operations (and the default value of 6 was particular bogus).

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agointel/genxml: Make assert in gen_pack_header print a message.
Kenneth Graunke [Mon, 7 May 2018 18:23:27 +0000 (11:23 -0700)]
intel/genxml: Make assert in gen_pack_header print a message.

Python's assert can take both a condition and a string, which will cause
it to print the string if the assertion trips.  (You can't use parens as
that creates a tuple.)  Doing "condition and string" works in C, but
doesn't have the desired effect in Python.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agoi965: Don't leak blorp on Gen4-5.
Kenneth Graunke [Mon, 23 Apr 2018 17:40:04 +0000 (10:40 -0700)]
i965: Don't leak blorp on Gen4-5.

We used to only initialize BLORP on Gen6+.  When we added it on Gen4-5,
we forgot to destroy it unconditionally.

Fixes: 752d7af77a52898cebf5597def4fdd38b1d6303e (i965: Add blorp support for gen4-5)
Reviewed-by: Matt Turner <mattst88@gmail.com>
6 years agonir: Transform discard_if(true) into discard
Matt Turner [Fri, 27 Apr 2018 04:25:42 +0000 (21:25 -0700)]
nir: Transform discard_if(true) into discard

Noticed while reviewing Tim Arceri's NIR inlining series.

Without his series:

instructions in affected programs: 16 -> 14 (-12.50%)
helped: 2

With his series:

instructions in affected programs: 196 -> 174 (-11.22%)
helped: 22

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agoeg/compute: Drop reference on code_bo in destructor.
Jan Vesely [Fri, 4 May 2018 03:55:00 +0000 (23:55 -0400)]
eg/compute: Drop reference on code_bo in destructor.

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
6 years agoconfigure.ac/meson.build: Fix -latomic test
Nicolas Boichat [Thu, 5 Apr 2018 01:33:09 +0000 (09:33 +0800)]
configure.ac/meson.build: Fix -latomic test

When compiling with LLVM 6.0 on x86 (32-bit) for Android, the test
fails to detect that -latomic is actually required, as the atomic
call is inlined.

In the code itself (src/util/disk_cache.c), we see this pattern:
p_atomic_add(cache->size, - (uint64_t)size);
where cache->size is an uint64_t *, and results in the following
link time error without -latomic:
src/util/disk_cache.c:628: error: undefined reference to '__atomic_fetch_add_8'

Fix the configure/meson test to replicate this pattern, which then
correctly realizes the need for -latomic.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
6 years agoanv: remove unused field anv_queue::pool
Scott D Phillips [Wed, 2 May 2018 16:01:03 +0000 (09:01 -0700)]
anv: remove unused field anv_queue::pool

The last use of the field was removed in 2015's ("48a87f4ba06
anv/queue: Get rid of the serial")

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agoi965: Set initial kflags on BO creation.
Kenneth Graunke [Thu, 3 May 2018 07:37:37 +0000 (00:37 -0700)]
i965: Set initial kflags on BO creation.

This simplifies kflag initialization, by creating a bufmgr-wide setting
for initial kflags, and just applying it whenever we create a new BO.

This also properly allows 48-bit addresses for imported BOs (via prime
or flink), which I had missed in my earlier 48-bit support series.

This will be useful when adding softpin support, as we'll want to add
EXEC_OBJECT_PINNED to initial_kflags as well.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
6 years agodocs: update calendar, add news and link release notes to 18.0.3
Juan A. Suarez Romero [Mon, 7 May 2018 11:25:54 +0000 (11:25 +0000)]
docs: update calendar, add news and link release notes to 18.0.3

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
6 years agodocs: add sha256 checksums for 18.0.3
Juan A. Suarez Romero [Mon, 7 May 2018 11:18:19 +0000 (11:18 +0000)]
docs: add sha256 checksums for 18.0.3

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit ae12c5e990a06099340c9467ee1a02354420812d)

6 years agodocs: add sha256 checksums for 18.0.3
Juan A. Suarez Romero [Mon, 7 May 2018 10:19:36 +0000 (10:19 +0000)]
docs: add sha256 checksums for 18.0.3

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit 6dc2658fd66c18239ad33cb1ffbdfc22b0d9e51e)

6 years agointel/genxml: Fix a few invalid field widths
Chris Wilson [Sat, 5 May 2018 18:36:25 +0000 (19:36 +0100)]
intel/genxml: Fix a few invalid field widths

A couple of typos found by inspecting field.end - field.start, revealed
a few wide integers declared as bool and some that ended before they
started.

Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
6 years agoswr/rast: Fix include for createInstructionCombiningPass with llvm-7.0.
Vinson Lee [Sun, 29 Apr 2018 06:28:08 +0000 (23:28 -0700)]
swr/rast: Fix include for createInstructionCombiningPass with llvm-7.0.

Fix build error after llvm-7.0.0svn r330669 ("InstCombine: Fix layering
by not including Scalar.h in InstCombine").

  CXX      rasterizer/jitter/libmesaswr_la-blend_jit.lo
rasterizer/jitter/blend_jit.cpp:816:20: error: use of undeclared identifier 'createInstructionCombiningPass'; did you mean 'createInstructionSimplifierPass'?
        passes.add(createInstructionCombiningPass());
                   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                   createInstructionSimplifierPass

Suggested-by: George Kyriazis <george.kyriazis@intel.com>
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-By: George Kyriazis <george.kyriazis@intel.com>
6 years agoclover: Add explicit virtual destructor to argument class
Jan Vesely [Fri, 4 May 2018 15:43:38 +0000 (11:43 -0400)]
clover: Add explicit virtual destructor to argument class

It is needed to destroy the v vector in scalar_argument
Fixes memory leaks on parameter set/bind.

v2: Drop redundant sclara_argument destructor

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
6 years agoanv/device: expose shaderInt16 support in gen8+
Iago Toral Quiroga [Fri, 4 May 2018 09:35:55 +0000 (11:35 +0200)]
anv/device: expose shaderInt16 support in gen8+

This rollbacks the revert of this patch introduced with
commit 7cf284f18e6774c810ed6db17b98e597bf96f8a5.

Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agoi965/compiler: handle conversion to smaller type in the lowering pass for that
Iago Toral Quiroga [Fri, 4 May 2018 09:33:07 +0000 (11:33 +0200)]
i965/compiler: handle conversion to smaller type in the lowering pass for that

This rollbacks the revert of this same patch introduced in
commit 7b9c15628aae8729118b648f5f473e6ac926b99b.

And also squahes the following patch to prevent a piglit regression caused
by this change:

intel/compiler: Fix lower_conversions for 8-bit types.
Author: Jose Maria Casanova Crespo <jmcasanova@igalia.com>

For 8-bit types the execution type is word. A byte raw MOV has 16-bit
execution type and 8-bit destination and it shouldn't be considered
a conversion case. So there is no need to change alignment and enter
in lower_conversions for these instructions.

Fixes a regresion in the piglit test "glsl-fs-shader-stencil-export"
that is introduced with this patch from the Vulkan shaderInt16 series:
'i965/compiler: handle conversion to smaller type in the lowering
pass for that'. The problem is caused because there is already a case
in the driver that injects Byte instructions like this:

mov(8)          g127<1>UB       g2<32,8,4>UB

And the aforementioned pass was not accounting for the special
handling of the execution size of Byte instructions. This patch
fixes this.

v2: (Jason Ekstrand)
   - Simplify is_byte_raw_mov, include reference to PRM and not
   consider B <-> UB conversions as raw movs.

v3: (Matt Turner)
   - Indentation style fixes.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106393
Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agointel/compiler: handle 16-bit to 64-bit conversions in BSW platforms
Iago Toral Quiroga [Fri, 4 May 2018 07:55:55 +0000 (09:55 +0200)]
intel/compiler: handle 16-bit to 64-bit conversions in BSW platforms

These are subject to the general restriction that anything that is converted
to 64-bit needs to be aligned to 64-bit.  We had this already in place for
32-bit to 64-bit conversions, so this patch generalizes the implementation
to take effect on any conversion to 64-bit from a source smaller than
64-bit.

Fixes assembly validation errors in the following CTS tests in BSW:
dEQP-VK.spirv_assembly.instruction.compute.sconvert.int16_to_int64
dEQP-VK.spirv_assembly.instruction.compute.uconvert.uint16_to_uint64
dEQP-VK.spirv_assembly.instruction.compute.sconvert.int16_to_uint64

Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agointel/genxml: recognize 0x, 0o and 0b when setting default value
Caio Marcelo de Oliveira Filho [Wed, 2 May 2018 21:48:57 +0000 (14:48 -0700)]
intel/genxml: recognize 0x, 0o and 0b when setting default value

Remove the need of converting values that are documented in
hexadecimal. This patch would allow writing

    <field name="3D Command Sub Opcode" ... default="0x1B"/>

instead of

    <field name="3D Command Sub Opcode" ... default="27"/>

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
6 years agor200: Enable NV_fog_distance
Ian Romanick [Sun, 18 Jun 2017 01:56:13 +0000 (18:56 -0700)]
r200: Enable NV_fog_distance

With the previous fixes in place, it appears to just work.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoi965: Enable NV_fog_distance
Ian Romanick [Sat, 17 Jun 2017 02:15:56 +0000 (19:15 -0700)]
i965: Enable NV_fog_distance

With the previous fixes in place, it appears to just work.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agoffvertex: Don't try to read output registers in fog calculation
Ian Romanick [Sat, 17 Jun 2017 02:02:48 +0000 (19:02 -0700)]
ffvertex: Don't try to read output registers in fog calculation

Gallium drivers use _mesa_remove_output_reads() via st_program to lower
output reads away.  It seems better to just generate the right thing in
the first place.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agomesa: Add missing support for glFogiv(GL_FOG_DISTANCE_MODE_NV)
Ian Romanick [Sat, 17 Jun 2017 01:48:22 +0000 (18:48 -0700)]
mesa: Add missing support for glFogiv(GL_FOG_DISTANCE_MODE_NV)

Found by inspection, so I made a piglit test too.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agomesa: Silence an unused parameter warning
Ian Romanick [Mon, 22 May 2017 22:21:00 +0000 (15:21 -0700)]
mesa: Silence an unused parameter warning

main/framebuffer.c: In function ‘update_color_draw_buffers’:
main/framebuffer.c:629:46: warning: unused parameter ‘ctx’ [-Wunused-parameter]
 update_color_draw_buffers(struct gl_context *ctx, struct gl_framebuffer *fb)
                                              ^~~

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
6 years agomesa/main/readpix: Correct handling of packed floating point values
Gert Wollny [Fri, 27 Apr 2018 16:04:01 +0000 (18:04 +0200)]
mesa/main/readpix: Correct handling of packed floating point values

Make sure that clamping in the pixel transfer operations is enabled/disabled
for packed floating point values just like it is done for single normal and
half precision floating point values.

This fixes a series of CTS tests with virgl that use r11f_g11f_b10f
buffers as target, and where virglrenderer reads these surfaces back
using the format GL_UNSIGNED_INT_10F_11F_11F_REV.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
6 years agoutil/set: add a set_clear function
Scott D Phillips [Wed, 2 May 2018 16:01:02 +0000 (09:01 -0700)]
util/set: add a set_clear function

Clear a set back to the state of having zero entries.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agoegl: add EGL_BAD_MATCH error case for surfaceless and android
Tapani Pälli [Fri, 4 May 2018 05:28:50 +0000 (08:28 +0300)]
egl: add EGL_BAD_MATCH error case for surfaceless and android

Just like is done for other backends when suitable config is not
found (added in fd4eba4929).

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
6 years agoamd/common: use llvm.amdgcn.wqm for explicit derivatives
Nicolai Hähnle [Tue, 1 May 2018 09:06:18 +0000 (11:06 +0200)]
amd/common: use llvm.amdgcn.wqm for explicit derivatives

To comply with an upcoming change in LLVM, see
https://reviews.llvm.org/D46051

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
6 years agonv50/ir: fix printing of pixld
Rhys Perry [Thu, 3 May 2018 17:02:14 +0000 (18:02 +0100)]
nv50/ir: fix printing of pixld

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
6 years agost/va: Support YUV formats in vaCreateSurfaces
Drew Davenport [Fri, 27 Apr 2018 15:34:58 +0000 (09:34 -0600)]
st/va: Support YUV formats in vaCreateSurfaces

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
6 years agoRevert "anv/device: expose shaderInt16 support in gen8+"
Mark Janes [Thu, 3 May 2018 21:28:22 +0000 (14:28 -0700)]
Revert "anv/device: expose shaderInt16 support in gen8+"

This reverts commit 0ba0ac815e078185c1f408ec7078fd1efac1a634.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106393
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>