mesa.git
5 years agoradeonsi: remove r600 from comments
Marek Olšák [Sat, 19 Jan 2019 00:39:45 +0000 (19:39 -0500)]
radeonsi: remove r600 from comments

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agowinsys/amdgpu: rename rfence, rsrc, rdst -> afence, asrc, adst
Marek Olšák [Sat, 19 Jan 2019 00:36:49 +0000 (19:36 -0500)]
winsys/amdgpu: rename rfence, rsrc, rdst -> afence, asrc, adst

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradeonsi: rename rview -> sview
Marek Olšák [Sat, 19 Jan 2019 00:35:33 +0000 (19:35 -0500)]
radeonsi: rename rview -> sview

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradeonsi: rename rscreen -> sscreen
Marek Olšák [Sat, 19 Jan 2019 00:19:23 +0000 (19:19 -0500)]
radeonsi: rename rscreen -> sscreen

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradeonsi: disable render cond & pipeline stats for internal compute dispatches
Marek Olšák [Wed, 16 Jan 2019 23:57:07 +0000 (18:57 -0500)]
radeonsi: disable render cond & pipeline stats for internal compute dispatches

5 years agoradeonsi: use compute for resource_copy_region when possible
Sonny Jiang [Mon, 3 Dec 2018 17:36:33 +0000 (12:36 -0500)]
radeonsi: use compute for resource_copy_region when possible

v2: marek: fix snorm8 blits

Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
5 years agoradeonsi: add compute_last_block to configure the partial block fields
Jiang, Sonny [Tue, 8 Jan 2019 19:47:07 +0000 (19:47 +0000)]
radeonsi: add compute_last_block to configure the partial block fields

5 years agogallium/util: add util_format_snorm8_to_sint8 (from radeonsi)
Marek Olšák [Tue, 15 Jan 2019 17:33:53 +0000 (12:33 -0500)]
gallium/util: add util_format_snorm8_to_sint8 (from radeonsi)

5 years agogallium: add SINT formats to have exact counterparts to SNORM formats
Marek Olšák [Tue, 15 Jan 2019 17:32:27 +0000 (12:32 -0500)]
gallium: add SINT formats to have exact counterparts to SNORM formats

for radeonsi

5 years agoradeonsi: move PKT3_WRITE_DATA generation into a helper function
Marek Olšák [Thu, 17 Jan 2019 20:07:03 +0000 (15:07 -0500)]
radeonsi: move PKT3_WRITE_DATA generation into a helper function

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradeonsi: don't use WRITE_DATA.DST_SEL == MEM_GRBM on >= CIK
Marek Olšák [Thu, 17 Jan 2019 19:49:02 +0000 (14:49 -0500)]
radeonsi: don't use WRITE_DATA.DST_SEL == MEM_GRBM on >= CIK

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradeonsi: fix the top-of-pipe fence on SI
Marek Olšák [Thu, 17 Jan 2019 19:45:10 +0000 (14:45 -0500)]
radeonsi: fix the top-of-pipe fence on SI

SI doesn't have MEM.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradeonsi: correct WRITE_DATA.DST_SEL definitions
Marek Olšák [Thu, 17 Jan 2019 19:27:18 +0000 (14:27 -0500)]
radeonsi: correct WRITE_DATA.DST_SEL definitions

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradeonsi: compile clear and copy buffer compute shaders on demand
Marek Olšák [Fri, 11 Jan 2019 23:06:59 +0000 (18:06 -0500)]
radeonsi: compile clear and copy buffer compute shaders on demand

same as all other shaders

5 years agoradeonsi: remove redundant call to emit_cache_flush in compute clear/copy
Marek Olšák [Fri, 11 Jan 2019 21:57:06 +0000 (16:57 -0500)]
radeonsi: remove redundant call to emit_cache_flush in compute clear/copy

launch_grid calls it.

5 years agoradeonsi: use buffer_store_format_x & xy
Marek Olšák [Thu, 10 Jan 2019 21:17:00 +0000 (16:17 -0500)]
radeonsi: use buffer_store_format_x & xy

5 years agoradeonsi: fix rendering to tiny viewports where the viewport center is > 8K
Marek Olšák [Thu, 10 Jan 2019 19:32:42 +0000 (14:32 -0500)]
radeonsi: fix rendering to tiny viewports where the viewport center is > 8K

This fixes an assertion failure with GL CTS when cts-runner is used.
(not a specific test)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108877
Cc: 18.3 <mesa-stable@lists.freedesktop.org>
5 years agoradeonsi: fix a u_blitter crash after a shader with FBFETCH
Marek Olšák [Fri, 11 Jan 2019 20:11:30 +0000 (15:11 -0500)]
radeonsi: fix a u_blitter crash after a shader with FBFETCH

This fixes an assertion failure with GL CTS when cts-runner is used.
(not a specific test)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108877
Cc: 18.3 <mesa-stable@lists.freedesktop.org>
5 years agowinsys/amdgpu: use the new BO list API
Marek Olšák [Mon, 7 Jan 2019 19:32:33 +0000 (14:32 -0500)]
winsys/amdgpu: use the new BO list API

5 years agoanv: Implement transform feedback queries
Jason Ekstrand [Fri, 14 Sep 2018 20:10:28 +0000 (15:10 -0500)]
anv: Implement transform feedback queries

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agogenxml: Add SO_PRIM_STORAGE_NEEDED and SO_NUM_PRIMS_WRITTEN
Jason Ekstrand [Fri, 14 Sep 2018 19:45:12 +0000 (14:45 -0500)]
genxml: Add SO_PRIM_STORAGE_NEEDED and SO_NUM_PRIMS_WRITTEN

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agoanv: Implement CmdBegin/EndQueryIndexed
Jason Ekstrand [Fri, 14 Sep 2018 19:27:43 +0000 (14:27 -0500)]
anv: Implement CmdBegin/EndQueryIndexed

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agoanv: Implement vkCmdDrawIndirectByteCountEXT
Jason Ekstrand [Fri, 14 Sep 2018 17:25:10 +0000 (12:25 -0500)]
anv: Implement vkCmdDrawIndirectByteCountEXT

Annoyingly, this requires that we implement integer division on the
command streamer.  Fortunately, we're only ever dividing by constants so
we can use the mulh+add+shift trick and it's not as bad as it sounds.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agoanv: Implement the basic form of VK_EXT_transform_feedback
Jason Ekstrand [Mon, 10 Sep 2018 21:17:37 +0000 (16:17 -0500)]
anv: Implement the basic form of VK_EXT_transform_feedback

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agoanv: Add pipeline cache support for xfb_info
Jason Ekstrand [Wed, 12 Sep 2018 21:40:52 +0000 (16:40 -0500)]
anv: Add pipeline cache support for xfb_info

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agoanv: Add but do not enable VK_EXT_transform_feedback
Jason Ekstrand [Mon, 10 Sep 2018 20:46:02 +0000 (15:46 -0500)]
anv: Add but do not enable VK_EXT_transform_feedback

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agonir/xfb: distinguish array of structs vs array of blocks
Alejandro Piñeiro [Thu, 10 Jan 2019 18:45:12 +0000 (19:45 +0100)]
nir/xfb: distinguish array of structs vs array of blocks

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agonir/xfb: Properly handle arrays of blocks
Jason Ekstrand [Wed, 9 Jan 2019 00:22:16 +0000 (18:22 -0600)]
nir/xfb: Properly handle arrays of blocks

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
5 years agonir/xfb: don't assert when xfb_buffer/stride is present but not xfb_offset
Alejandro Piñeiro [Mon, 22 Oct 2018 16:30:39 +0000 (18:30 +0200)]
nir/xfb: don't assert when xfb_buffer/stride is present but not xfb_offset

In order to allow nir_gather_xfb_info to be used on OpenGL,
specifically ARB_gl_spirv.

So, from OpenGL 4.6 spec, section 11.1.2.1, "Output Variables":

    "outputs specifying both an *XfbBuffer* and an *Offset* are
     captured, while outputs not specifying both of these are not
     captured. Values are captured each time the shader writes to such
     a decorated object."

This implies that are captured if both are present, and not if one of
those are lacking. Technically, it doesn't explicitly point that
having just one or the other is a mistake. In some cases, glslang is
adding some extra XfbBuffer without XfbOffset around, and mentioning
that technically that is not a bug (see issue#1526)

And for the case of Vulkan, as the same glslang issue mentions, it is
not clear if that should be a mistake or not. But even if it is a
mistake, it is not really needed to be checked on the driver, and we
can let the validation layers to check that.

v2: simplify explicit_xfb_buffer and explicit_offset checks (Jason).

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agonir/xfb: Fix offset accounting for dvec3/4
Jason Ekstrand [Thu, 6 Dec 2018 22:49:27 +0000 (16:49 -0600)]
nir/xfb: Fix offset accounting for dvec3/4

Before, we were double-counting the component slots when we had a dvec3
or dvec4.  Instead, just add them in once and manually offset the
recorded output offset.

Fixes: 19064b8c "nir: Add a pass for gathering transform feedback info"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
5 years agonir: Preserve offsets in lower_io_to_scalar_early
Jason Ekstrand [Fri, 14 Sep 2018 20:54:19 +0000 (15:54 -0500)]
nir: Preserve offsets in lower_io_to_scalar_early

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
5 years agonir: fix lowering arrays to elements for XFB outputs
Samuel Pitoiset [Mon, 10 Sep 2018 19:59:31 +0000 (21:59 +0200)]
nir: fix lowering arrays to elements for XFB outputs

If we have a transform feedback output like:

float[2] x2_out (VARYING_SLOT_VAR1.x, 0, 0)

which is lowered by nir_lower_io_arrays_to_elements to,

float x2_out (VARYING_SLOT_VAR1.x, 0, 0)
float x2_out@5 (VARYING_SLOT_VAR2.x, 0, 0)

We have to update the destination offset to avoid overwriting
the same value.

v2 (Jason Ekstrand):
 - Compute the correct offsets for arrays of vectors and/or doubles

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
5 years agonir: do not remove varyings used for transform feedback
Samuel Pitoiset [Fri, 11 May 2018 08:29:17 +0000 (10:29 +0200)]
nir: do not remove varyings used for transform feedback

When a xfb buffer is explicitely declared on a varying
variable, we shouldn't remove it at link time.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agospirv: Only set interface_type on blocks
Jason Ekstrand [Mon, 21 Jan 2019 22:09:56 +0000 (16:09 -0600)]
spirv: Only set interface_type on blocks

Instead of setting interface_type to whatever the per-vertex type is, we
only set it on blocks.  This allows later passes to tell the difference
between variables that are in blocks and those that aren't.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
5 years agospirv: Only split blocks
Jason Ekstrand [Wed, 16 Jan 2019 17:52:03 +0000 (11:52 -0600)]
spirv: Only split blocks

Instead of splitting every per-vertex struct, just split the ones that
are actually blocks.  The reason for the split is so that we have
separate variables for separate locations, qualifiers, and builtin
decorations.  The vulkan spec only allows these on members of blocks.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
5 years agospirv: Initialize struct member offsets to -1
Jason Ekstrand [Wed, 9 Jan 2019 00:19:33 +0000 (18:19 -0600)]
spirv: Initialize struct member offsets to -1

This is the "no offset specified" value.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agoanv: Always emit at least one vertex element
Jason Ekstrand [Tue, 8 Jan 2019 23:35:19 +0000 (17:35 -0600)]
anv: Always emit at least one vertex element

This seems to make the simulator happier.  The early return wasn't
really protecting anything and the code that follows will happily
initialize the dummy element to STORE_0 and emit it.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agoconfigure: EGL requirements only apply if EGL is built
Eric Engestrom [Mon, 21 Jan 2019 19:44:45 +0000 (19:44 +0000)]
configure: EGL requirements only apply if EGL is built

Issue was hit with this configuration:
  --disable-{egl,gbm} --with-platform=drm

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Fixes: 3208fd2e46b ("configure: move platform handling further up")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
5 years agofreedreno: a2xx: add partial lower_scalar pass for ir2
Jonathan Marek [Thu, 13 Dec 2018 17:39:39 +0000 (12:39 -0500)]
freedreno: a2xx: add partial lower_scalar pass for ir2

Some instructions can only be scalar on a2xx, lower these only

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
5 years agofreedreno: a2xx: add ir2 copy propagation
Jonathan Marek [Wed, 19 Dec 2018 01:23:16 +0000 (20:23 -0500)]
freedreno: a2xx: add ir2 copy propagation

Two cases:
* replacing srcs which refer to MOV instructions
* replacing MOVs used to write to exports

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
5 years agofreedreno: a2xx: insert scalar MOV to allow 2 source scalar
Jonathan Marek [Mon, 21 Jan 2019 15:00:28 +0000 (10:00 -0500)]
freedreno: a2xx: insert scalar MOV to allow 2 source scalar

If we want to use a scalar instruction with two sources, both sources have
to be in the same register. This covers a common case by inserting a scalar
MOV into a previous instruction with only a vector alu instruction.

A better method would be to have the sources end up in the same register in
the first place, but when one source is a constant this is the only way.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
5 years agofreedreno: a2xx: NIR backend
Jonathan Marek [Wed, 19 Dec 2018 01:15:57 +0000 (20:15 -0500)]
freedreno: a2xx: NIR backend

This patch replaces the a2xx TGSI compiler with a NIR compiler.

It also adds several new features:
-gl_FrontFacing, gl_FragCoord, gl_PointCoord, gl_PointSize
-control flow (including loops)
-texture related features (LOD/bias, cubemaps)
-filling scalar ALU slot when possible

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
5 years agonir: cleanup glsl_get_struct_field_offset, glsl_get_explicit_stride
Tapani Pälli [Tue, 22 Jan 2019 07:37:58 +0000 (09:37 +0200)]
nir: cleanup glsl_get_struct_field_offset, glsl_get_explicit_stride

Take away const qualifier from return type of these functions as
-Wignored-qualifiers points out it is ignored for these cases.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agotravis: fix autotools build after --enable-autotools switch addition
Eric Engestrom [Mon, 21 Jan 2019 10:03:37 +0000 (10:03 +0000)]
travis: fix autotools build after --enable-autotools switch addition

Fixes: e68777c87ceed02ab199 "autotools: Deprecate the use of autotools"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agospirv: Update the JSON and headers from Khronos master
Jason Ekstrand [Sat, 19 Jan 2019 15:21:33 +0000 (09:21 -0600)]
spirv: Update the JSON and headers from Khronos master

This corresponds to commit 79b6681aadcb53c27d1052e on GitHub.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agonir: Mark deref UBO and SSBO access as non-scalar
Jason Ekstrand [Mon, 21 Jan 2019 22:35:25 +0000 (16:35 -0600)]
nir: Mark deref UBO and SSBO access as non-scalar

Fixes: 63b9aa2e2574 "spirv: Add support for using derefs for..."
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agonir/spirv: handle ContractionOff execution mode
Karol Herbst [Mon, 3 Dec 2018 18:08:41 +0000 (19:08 +0100)]
nir/spirv: handle ContractionOff execution mode

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agonir/vtn: add caps for some cl related capabilities
Rob Clark [Mon, 26 Feb 2018 23:01:02 +0000 (18:01 -0500)]
nir/vtn: add caps for some cl related capabilities

vtn supports these, so don't squalk if user is happy with enabling
these.

v2: add new members sorted

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agovtn: handle SpvExecutionModelKernel
Karol Herbst [Wed, 7 Mar 2018 16:41:03 +0000 (17:41 +0100)]
vtn: handle SpvExecutionModelKernel

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agomesa: add MESA_SHADER_KERNEL
Karol Herbst [Thu, 29 Nov 2018 14:21:12 +0000 (15:21 +0100)]
mesa: add MESA_SHADER_KERNEL

used for CL kernels

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoanv/pipeline: Add a pdevice helper variable
Jason Ekstrand [Sat, 19 Jan 2019 23:50:23 +0000 (17:50 -0600)]
anv/pipeline: Add a pdevice helper variable

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
5 years agorelnotes: Add newly added Vulkan extensions
Jason Ekstrand [Sat, 19 Jan 2019 19:10:15 +0000 (13:10 -0600)]
relnotes: Add newly added Vulkan extensions

Both the Intel and RADV people have been really bad about adding things
to the release notes.  We should start actually paying attention.

Acked-by: Tapani Pälli <tapani.palli@intel.com>
5 years agoanv: Only parse pImmutableSamplers if the descriptor has samplers
Jason Ekstrand [Sat, 19 Jan 2019 15:40:12 +0000 (09:40 -0600)]
anv: Only parse pImmutableSamplers if the descriptor has samplers

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
5 years agoradv: prevent dirtying of dynamic state when it does not change
Rhys Perry [Fri, 18 Jan 2019 20:35:15 +0000 (20:35 +0000)]
radv: prevent dirtying of dynamic state when it does not change

DXVK often sets dynamic state without actually changing it.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradv: avoid context rolls when binding graphics pipelines
Rhys Perry [Fri, 18 Jan 2019 20:17:35 +0000 (20:17 +0000)]
radv: avoid context rolls when binding graphics pipelines

It's common in some applications to bind a new graphics pipeline without
ending up changing any context registers.

This has a pipline have two command buffers: one for setting context
registers and one for everything else. The context register command buffer
is only emitted if it differs from the previous pipeline's.

v2: ensure late scissor emission is done when radv_emit_rbplus_state() is
    called
v2: make use of cmd_buffer->state.workaround_scissor_bug
v3: rename "workaround_scissor_bug" to
    "context_roll_without_scissor_emitted"

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradv: add missed situations for scissor bug workaround
Rhys Perry [Fri, 18 Jan 2019 20:17:35 +0000 (20:17 +0000)]
radv: add missed situations for scissor bug workaround

v2: rename "workaround_scissor_bug" to
    "context_roll_without_scissor_emitted"

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradv: pass radv_draw_info to radv_emit_draw_registers()
Rhys Perry [Fri, 18 Jan 2019 20:15:26 +0000 (20:15 +0000)]
radv: pass radv_draw_info to radv_emit_draw_registers()

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agofreedreno: a2xx: sysmem rendering
Jonathan Marek [Wed, 19 Dec 2018 02:35:41 +0000 (21:35 -0500)]
freedreno: a2xx: sysmem rendering

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno: a2xx: fix non-zero texture base offsets
Jonathan Marek [Mon, 10 Dec 2018 03:31:26 +0000 (22:31 -0500)]
freedreno: a2xx: fix non-zero texture base offsets

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno: a2xx: fix VERTEX_REUSE/DEALLOC on a20x
Jonathan Marek [Tue, 18 Dec 2018 23:11:04 +0000 (18:11 -0500)]
freedreno: a2xx: fix VERTEX_REUSE/DEALLOC on a20x

On a20x, set VGT_VERTEX_REUSE_BLOCK_CNTL to 2 and don't change it. Small
rearrangement on a220 to reduce the size of draw commands.

Only set DEALLOC_CNTL on a20x because the correct a220 value is not known.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno: a2xx: fix gmem2mem viewport
Jonathan Marek [Mon, 10 Dec 2018 04:14:41 +0000 (23:14 -0500)]
freedreno: a2xx: fix gmem2mem viewport

Fixes cases where previous viewport values might case gmem2mem to fail.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno: a2xx: cleanup REG_A2XX_PA_CL_VTE_CNTL
Jonathan Marek [Thu, 13 Dec 2018 17:11:31 +0000 (12:11 -0500)]
freedreno: a2xx: cleanup REG_A2XX_PA_CL_VTE_CNTL

Doesn't change much, but reduces the size of fd2_emit_state

gmem2mem does not need to change the value: no Z clipping on resolve
mem2gmem now needs to restore the common value after rendering

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno: a2xx: cleanup init_shader_const
Jonathan Marek [Wed, 16 Jan 2019 21:06:11 +0000 (16:06 -0500)]
freedreno: a2xx: cleanup init_shader_const

Only 3 vertices are used so we can drop the data for vertex 4

It doesn't make sense to have 1.1 for some coordinates, use 1.0 instead

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>
5 years agonir: add bit_size parameter to system values with multiple allowed bit sizes
Karol Herbst [Tue, 4 Dec 2018 15:40:30 +0000 (16:40 +0100)]
nir: add bit_size parameter to system values with multiple allowed bit sizes

v2: add assert to verify we have at least one valid bit_size
v3: fix use of load_front_face in nir_lower_two_sided_color and tgsi_to_nir

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agonir: add legal bit_sizes to intrinsics
Karol Herbst [Thu, 19 Jul 2018 11:04:43 +0000 (13:04 +0200)]
nir: add legal bit_sizes to intrinsics

With OpenCL some system values match the address bits, but in GLSL we also
have some system values being 64 bit like subgroup masks.

With this it is possible to adjust the builder functions so that depending
on the bit_sizes the correct bit_size is used or an additional argument is
added in case of multiple possible values.

v2: validate dest bit_size
v3: generate hex values in python code
    remove useless imports
    rename and move bit_sizes
v4: add 1 to legal bit_sizes for front_face

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agonir/validate: allow to check against a bitmask of bit_sizes
Karol Herbst [Tue, 4 Dec 2018 01:35:46 +0000 (02:35 +0100)]
nir/validate: allow to check against a bitmask of bit_sizes

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agonir: replace more nir_load_system_value calls with builder functions
Karol Herbst [Tue, 4 Dec 2018 16:15:42 +0000 (17:15 +0100)]
nir: replace more nir_load_system_value calls with builder functions

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoglsl/lower_output_reads: set invariant and precise flags on temporaries
Karol Herbst [Fri, 18 Jan 2019 13:13:25 +0000 (14:13 +0100)]
glsl/lower_output_reads: set invariant and precise flags on temporaries

fixes a couple of deqp tests (on nvc0 and potential other drivers):
dEQP-GLES3.functional.shaders.invariance.highp.common_subexpression_1
dEQP-GLES3.functional.shaders.invariance.highp.common_subexpression_2
dEQP-GLES3.functional.shaders.invariance.highp.common_subexpression_3
dEQP-GLES3.functional.shaders.invariance.mediump.common_subexpression_1
dEQP-GLES3.functional.shaders.invariance.mediump.common_subexpression_2
dEQP-GLES3.functional.shaders.invariance.mediump.common_subexpression_3
dEQP-GLES3.functional.shaders.invariance.lowp.common_subexpression_1
dEQP-GLES3.functional.shaders.invariance.lowp.common_subexpression_2
dEQP-GLES3.functional.shaders.invariance.lowp.common_subexpression_3

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agonv50,nvc0: add missing CAPs for unsupported features
Rhys Kidd [Fri, 18 Jan 2019 05:24:40 +0000 (00:24 -0500)]
nv50,nvc0: add missing CAPs for unsupported features

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agonir/spirv: handle SpvStorageClassCrossWorkgroup
Karol Herbst [Tue, 23 Oct 2018 12:06:16 +0000 (14:06 +0200)]
nir/spirv: handle SpvStorageClassCrossWorkgroup

v2: rename nir_var_global to nir_var_mem_global

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agonir: rename nir_var_shared to nir_var_mem_shared
Karol Herbst [Tue, 15 Jan 2019 23:12:38 +0000 (00:12 +0100)]
nir: rename nir_var_shared to nir_var_mem_shared

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agonir: rename nir_var_ssbo to nir_var_mem_ssbo
Karol Herbst [Tue, 15 Jan 2019 23:11:23 +0000 (00:11 +0100)]
nir: rename nir_var_ssbo to nir_var_mem_ssbo

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agonir: rename nir_var_ubo to nir_var_mem_ubo
Karol Herbst [Tue, 15 Jan 2019 23:09:27 +0000 (00:09 +0100)]
nir: rename nir_var_ubo to nir_var_mem_ubo

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agonir: rename nir_var_function to nir_var_function_temp
Karol Herbst [Tue, 15 Jan 2019 23:05:04 +0000 (00:05 +0100)]
nir: rename nir_var_function to nir_var_function_temp

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agonir: rename nir_var_private to nir_var_shader_temp
Karol Herbst [Tue, 15 Jan 2019 22:56:29 +0000 (23:56 +0100)]
nir: rename nir_var_private to nir_var_shader_temp

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agointel/genxml: add missing MI_PREDICATE compare operations
Lionel Landwerlin [Fri, 18 Jan 2019 16:12:06 +0000 (16:12 +0000)]
intel/genxml: add missing MI_PREDICATE compare operations

Doesn't save us a great deal of lines but at least they get decoded in
aubinators.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
5 years agoanv: document cache flushes & invalidations
Lionel Landwerlin [Fri, 18 Jan 2019 10:47:31 +0000 (10:47 +0000)]
anv: document cache flushes & invalidations

A little bit of explanation regarding how vkCmdPipelineBarrier()
works.

v2: Avoid referring to data port cache when it's actually sampler
    caches (Jason)
    Complete explanation for indirect draws (Jason)

v3: s/samplers/sampler/ (Jason)
    s/UBOs/data port/
    Add documentation for VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com> (v1)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v2)
5 years agoanv: narrow flushing of the render target to buffer writes
Lionel Landwerlin [Thu, 17 Jan 2019 17:00:14 +0000 (17:00 +0000)]
anv: narrow flushing of the render target to buffer writes

In commit 9a7b3199037ac4 ("anv/query: flush render target before
copying results") we tracked all the render target writes to apply a
flushes in the vkCopyQueryResults(). But we can narrow this down to
only when we write a buffer (which is the only input of
vkCopyQueryResults).

v2: Drop newer render target write flags introduce by 1952fd8d2ce905
    ("anv: Implement VK_EXT_conditional_rendering for gen 7.5+")

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v1)
5 years agoglsl: be much more aggressive when skipping shader compilation
Timothy Arceri [Thu, 17 Jan 2019 06:16:29 +0000 (17:16 +1100)]
glsl: be much more aggressive when skipping shader compilation

Currently we only add a cache key for a shader once it is linked.
However games like Team Fortress 2 compile a whole bunch of shaders
which are never actually linked. These compiled shaders can take
up a bunch of memory.

This patch changes things so that we add the key for the shader to
the cache as soon as it is compiled. This means on a warm cache we
can avoid the wasted memory from these shaders. Worst case scenario
is we need to compile the shaders at link time but this can happen
anyway if the shader has been evicted from the cache.

Reduces memory use in Team Fortress 2 from 1.3GB -> 770MB on a
warm cache from start up to the game menu.

V2: only add key to cache when compilation is successful.

Acked-by: Marek Olšák <marek.olsak@amd.com>
5 years agointel/fs: Promote execution type to 32-bit when any half-float conversion is needed.
Francisco Jerez [Tue, 15 Jan 2019 21:35:30 +0000 (13:35 -0800)]
intel/fs: Promote execution type to 32-bit when any half-float conversion is needed.

The docs are fairly incomplete and inconsistent about it, but this
seems to be the reason why half-float destinations are required to be
DWORD-aligned on BDW+ projects.  This way the regioning lowering pass
will make sure that the destination components of W to HF and HF to W
conversions are aligned like the corresponding conversion operation
with 32-bit execution data type.

Tested-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agoac/nir_to_llvm: fix interpolateAt* for arrays
Timothy Arceri [Thu, 10 Jan 2019 04:54:43 +0000 (15:54 +1100)]
ac/nir_to_llvm: fix interpolateAt* for arrays

This builds on the recent interpolate fix by Rhys ee8488ea3b99.

This fixes the arb_gpu_shader5 interpolateAt* tests that contain
arrays.

Fixes: ee8488ea3b99 ("ac/nir,radv,radeonsi/nir: use correct indices for interpolation intrinsics")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoRevert "glsl: be much more aggressive when skipping shader compilation"
Timothy Arceri [Fri, 18 Jan 2019 23:45:07 +0000 (10:45 +1100)]
Revert "glsl: be much more aggressive when skipping shader compilation"

This reverts commit 64b8c86d37ebb1e1d286c69d642d52b7bcf051d3.

Reverting for now as it was causing some segfaults.

5 years agofreedreno/a6xx: Turn on texture tiling by default
Kristian H. Kristensen [Fri, 21 Dec 2018 17:14:28 +0000 (09:14 -0800)]
freedreno/a6xx: Turn on texture tiling by default

The color swap isn't available for tiled formats and it's not needed
either. We pick one channel order and use for all non-linear formats.

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno: Synchronize batch and flush for staging resource
Kristian H. Kristensen [Thu, 17 Jan 2019 19:32:14 +0000 (11:32 -0800)]
freedreno: Synchronize batch and flush for staging resource

Staging blit downloads would wait on the src resource instead of the
staging resource and didn't make sure to submit the blit batch first.

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
5 years agoglsl: be much more aggressive when skipping shader compilation
Timothy Arceri [Thu, 17 Jan 2019 06:16:29 +0000 (17:16 +1100)]
glsl: be much more aggressive when skipping shader compilation

Currently we only add a cache key for a shader once it is linked.
However games like Team Fortress 2 compile a whole bunch of shaders
which are never actually linked. These compiled shaders can take
up a bunch of memory.

This patch changes things so that we add the key for the shader to
the cache as soon as it is compiled. This means on a warm cache we
can avoid the wasted memory from these shaders. Worst case scenario
is we need to compile the shaders at link time but this can happen
anyway if the shader has been evicted from the cache.

Reduces memory use in Team Fortress 2 from 1.3GB -> 770MB on a
warm cache from start up to the game menu.

Acked-by: Marek Olšák <marek.olsak@amd.com>
5 years agoglsl: don't skip GLSL IR opts on first-time compiles
Timothy Arceri [Thu, 17 Jan 2019 06:16:28 +0000 (17:16 +1100)]
glsl: don't skip GLSL IR opts on first-time compiles

This basically reverts c2bc0aa7b188.

By running the opts we reduce  memory using in Team Fortress 2
from 1.5GB -> 1.3GB from start-up to game menu.

This will likely increase Deus Ex start up times as per commit
c2bc0aa7b188. However currently 32bit games like Team Fortress 2
can run out of memory on low memory systems, so that seems more
important.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agonir: check NIR_SKIP to skip passes by name
Caio Marcelo de Oliveira Filho [Thu, 17 Jan 2019 21:06:04 +0000 (13:06 -0800)]
nir: check NIR_SKIP to skip passes by name

Passes' function names, separated by comma, listed in NIR_SKIP
environment variable will be skipped in debug mode.  The mechanism is
hooked into the _PASS macro, like NIR_PRINT.

The extra macro NIR_SKIP is available as a developer convenience, to
skip at pointer other than the passes entry points.

v2: Fix typo in NIR_SKIP macro. (Bas)

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoanv: Implement VK_EXT_conditional_rendering for gen 7.5+
Danylo Piliaiev [Fri, 5 Oct 2018 14:54:07 +0000 (17:54 +0300)]
anv: Implement VK_EXT_conditional_rendering for gen 7.5+

Conditional rendering affects next functions:
- vkCmdDraw, vkCmdDrawIndexed, vkCmdDrawIndirect, vkCmdDrawIndexedIndirect
- vkCmdDrawIndirectCountKHR, vkCmdDrawIndexedIndirectCountKHR
- vkCmdDispatch, vkCmdDispatchIndirect, vkCmdDispatchBase
- vkCmdClearAttachments

Value from conditional buffer is cached into designated register,
MI_PREDICATE is emitted every time conditional rendering is enabled
and command requires it.

v2: by Jason Ekstrand
  - Use vk_find_struct_const instead of manually looping
  - Move draw count loading to prepare function
  - Zero the top 32-bits of MI_ALU_REG15

v3: Apply pipeline flush before accessing conditional buffer
 (The issue was found by Samuel Iglesias)

v4: - Remove support of Haswell due to possible hardware bug
    - Made TMP_REG_PREDICATE and TMP_REG_DRAW_COUNT defines to
       define registers in one place.

v5: thanks to Jason Ekstrand and Lionel Landwerlin
    - Workaround the fact that MI_PREDICATE_RESULT is not
      accessible on Haswell by manually calculating
      MI_PREDICATE_RESULT and re-emitting MI_PREDICATE
      when necessary.

v6: suggested by Lionel Landwerlin
    - Instead of calculating the result of predicate once - re-emit
      MI_PREDICATE to make it easier to investigate error states.

v7: suggested by Jason
    - Make anv_pipe_invalidate_bits_for_access_flag add CS_STALL
      if VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT is set.

v8: suggested by Lionel
    - Precompute conditional predicate's result to
      support secondary command buffers.
    - Make prepare_for_draw_count_predicate more readable.

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agoanv: Implement VK_KHR_draw_indirect_count for gen 7+
Danylo Piliaiev [Fri, 5 Oct 2018 09:15:24 +0000 (12:15 +0300)]
anv: Implement VK_KHR_draw_indirect_count for gen 7+

v2: by Jason Ekstrand
  - Move out of the draw loop population of registers
    which aren't changed in it.
  - Remove dependency on ALU registers.
  - Clarify usage of PIPE_CONTROL
  - Without usage of ALU registers patch works for gen7+

v3: set pending_pipe_bits |= ANV_PIPE_RENDER_TARGET_WRITES

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agobin/meson-cmd-extract: Also handle cross and native files
Dylan Baker [Wed, 16 Jan 2019 22:51:38 +0000 (14:51 -0800)]
bin/meson-cmd-extract: Also handle cross and native files

Native file support in command line serialization isn't present in meson
0.49, but will be for 0.49.1 and 0.50

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
5 years agoanv: Re-sort the extensions list
Jason Ekstrand [Fri, 18 Jan 2019 16:23:33 +0000 (10:23 -0600)]
anv: Re-sort the extensions list

I like to keep things in good order so that you can find them.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agointel/fs: Don't touch accumulator destination while applying regioning alignment...
Jason Ekstrand [Wed, 16 Jan 2019 23:40:13 +0000 (17:40 -0600)]
intel/fs: Don't touch accumulator destination while applying regioning alignment rule

In some shaders, you can end up with a stride in the source of a
SHADER_OPCODE_MULH.  One way this can happen is if the MULH is acting on
the top bits of a 64-bit value due to 64-bit integer lowering.  In this
case, the compiler will produce something like this:

mul(8)    acc0<1>UD   g5<8,4,2>UD   0x0004UW      { align1 1Q };
mach(8)   g6<1>UD     g5<8,4,2>UD   0x00000004UD  { align1 1Q AccWrEnable };

The new region fixup pass looks at the MUL and sees a strided source and
unstrided destination and determines that the sequence is illegal.  It
then attempts to fix the illegal stride by replacing the destination of
the MUL with a temporary and emitting a MOV into the accumulator:

mul(8)    g9<2>UD     g5<8,4,2>UD   0x0004UW      { align1 1Q };
mov(8)    acc0<1>UD   g9<8,4,2>UD                 { align1 1Q };
mach(8)   g6<1>UD     g5<8,4,2>UD   0x00000004UD  { align1 1Q AccWrEnable };

Unfortunately, this new sequence isn't correct because MOV accesses the
accumulator with a different precision to MUL and, instead of filling
the bottom 32 bits with the source and zeroing the top 32 bits, it
leaves the top 32 (or maybe 31) bits alone and full of garbage.  When
the MACH comes along and tries to complete the multiplication, the
result is correct in the bottom 32 bits (which we throw away) and
garbage in the top 32 bits which are actually returned by MACH.

This commit does two things:  First, it adds an assert to ensure that we
don't try to rewrite accumulator destinations of MUL instructions so we
can avoid this precision issue.  Second, it modifies
required_dst_byte_stride to require a tightly packed stride so that we
fix up the sources instead and the actual code which gets emitted is
this:

mov(8)    g9<1>UD     g5<8,4,2>UD                 { align1 1Q };
mul(8)    acc0<1>UD   g9<8,8,1>UD   0x0004UW      { align1 1Q };
mach(8)   g6<1>UD     g5<8,4,2>UD   0x00000004UD  { align1 1Q AccWrEnable };

Fixes: efa4e4bc5fc "intel/fs: Introduce regioning lowering pass"
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
5 years agointel/eu: Stop overriding exec sizes in send_indirect_message
Jason Ekstrand [Sun, 13 Jan 2019 02:26:53 +0000 (20:26 -0600)]
intel/eu: Stop overriding exec sizes in send_indirect_message

For a long time, we based exec sizes on destination register widths.
We've not been doing that since 1ca3a9442760b6f7 but a few remnants
accidentally remained.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
5 years agoradv: initialize the per-queue descriptor BO only once
Samuel Pitoiset [Thu, 17 Jan 2019 17:11:10 +0000 (18:11 +0100)]
radv: initialize the per-queue descriptor BO only once

Totally useless to write the descriptors inside the loop.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradv: do not write unused descriptors to the per-queue BO
Samuel Pitoiset [Thu, 17 Jan 2019 17:11:09 +0000 (18:11 +0100)]
radv: do not write unused descriptors to the per-queue BO

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradv: reduce size of the per-queue descriptor BO
Samuel Pitoiset [Thu, 17 Jan 2019 17:11:08 +0000 (18:11 +0100)]
radv: reduce size of the per-queue descriptor BO

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradv: drop unused code related to 16 sample locations
Samuel Pitoiset [Thu, 17 Jan 2019 17:11:07 +0000 (18:11 +0100)]
radv: drop unused code related to 16 sample locations

The driver only supports up to 8 sample locations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agogm107/ir: disable TEXS for tex with derivAll set
Karol Herbst [Fri, 18 Jan 2019 01:43:54 +0000 (02:43 +0100)]
gm107/ir: disable TEXS for tex with derivAll set

fixes deqp tests:
dEQP-GLES3.functional.shaders.texture_functions.texturegrad.samplercube_fixed_vertex
dEQP-GLES3.functional.shaders.texture_functions.texturegrad.samplercube_float_vertex
dEQP-GLES3.functional.shaders.texture_functions.texturegrad.isamplercube_vertex
dEQP-GLES3.functional.shaders.texture_functions.texturegrad.usamplercube_vertex
dEQP-GLES3.functional.shaders.texture_functions.texturegrad.sampler3d_fixed_vertex
dEQP-GLES3.functional.shaders.texture_functions.texturegrad.sampler3d_float_vertex
dEQP-GLES3.functional.shaders.texture_functions.texturegrad.isampler3d_vertex
dEQP-GLES3.functional.shaders.texture_functions.texturegrad.usampler3d_vertex
dEQP-GLES3.functional.shaders.texture_functions.texturegrad.sampler2dshadow_vertex
dEQP-GLES3.functional.shaders.texture_functions.textureprojgrad.sampler3d_fixed_vertex
dEQP-GLES3.functional.shaders.texture_functions.textureprojgrad.sampler3d_float_vertex
dEQP-GLES3.functional.shaders.texture_functions.textureprojgrad.isampler3d_vertex
dEQP-GLES3.functional.shaders.texture_functions.textureprojgrad.usampler3d_vertex
dEQP-GLES3.functional.shaders.texture_functions.textureprojgrad.sampler2dshadow_vertex

Fixes: f821e80213e38e93f96255b3deacb737a600ed40
       "gm107/ir: use scalar tex instructions where possible"
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agonv50/ir: disable tryCollapseChainedMULs in ConstantFolding for precise instructions
Karol Herbst [Thu, 17 Jan 2019 22:32:19 +0000 (23:32 +0100)]
nv50/ir: disable tryCollapseChainedMULs in ConstantFolding for precise instructions

fixes dEQP-GLES2.functional.shaders.invariance.mediump.loop_3

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
5 years agonir: Account for atomics in copy propagation.
Bas Nieuwenhuizen [Thu, 17 Jan 2019 18:54:20 +0000 (19:54 +0100)]
nir: Account for atomics in copy propagation.

Otherwise writes get propagated across atomics if no barrier is
used. Without barrier writes should still be visible in the same
invocation, so an atomic has to be considered a write.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Fixes: b3c61469255 "nir: Copy propagation between blocks"
Fixes: 62332d139c8 "nir: Add a local variable-based copy propagation pass"