Luke Kenneth Casson Leighton [Sun, 20 Sep 2020 14:28:00 +0000 (15:28 +0100)]
continuing async clock experimenting
Luke Kenneth Casson Leighton [Sun, 20 Sep 2020 14:20:27 +0000 (15:20 +0100)]
add an async clock synchronizer experiment
Luke Kenneth Casson Leighton [Sun, 20 Sep 2020 11:54:07 +0000 (12:54 +0100)]
first version code-morph on dmi2jtag
Luke Kenneth Casson Leighton [Sat, 19 Sep 2020 22:38:13 +0000 (23:38 +0100)]
add pc_o not connected
Luke Kenneth Casson Leighton [Sat, 19 Sep 2020 22:36:45 +0000 (23:36 +0100)]
set ROM to empty, set SRAM to tiny 0x200, get things working first
Cesar Strauss [Sat, 19 Sep 2020 22:14:45 +0000 (19:14 -0300)]
Remove demonstration code
This was moved to nmutil.test.example_gtkwave.
Luke Kenneth Casson Leighton [Sat, 19 Sep 2020 15:00:37 +0000 (16:00 +0100)]
urk. wishbone slave devices declared incorrectly (I/O inverted)
Luke Kenneth Casson Leighton [Sat, 19 Sep 2020 14:45:07 +0000 (15:45 +0100)]
disable internal RAM set SRAM to much smaller
Luke Kenneth Casson Leighton [Sat, 19 Sep 2020 14:29:31 +0000 (15:29 +0100)]
shrink size of SRAM to 8k, move things around
Luke Kenneth Casson Leighton [Sat, 19 Sep 2020 13:36:25 +0000 (14:36 +0100)]
add (disabled) tri-state GPIO
Luke Kenneth Casson Leighton [Sat, 19 Sep 2020 13:10:02 +0000 (14:10 +0100)]
remove the gpio peripheral which was previously hard-linked to interrupts
Luke Kenneth Casson Leighton [Sat, 19 Sep 2020 11:17:34 +0000 (12:17 +0100)]
add 3x EINTs to ls180soc
Luke Kenneth Casson Leighton [Fri, 18 Sep 2020 22:13:17 +0000 (23:13 +0100)]
add SPI, sdcard, preliminary GPIO to ls180 pinouts
Luke Kenneth Casson Leighton [Fri, 18 Sep 2020 21:35:12 +0000 (22:35 +0100)]
argh got fed up trying to shoe-horn into sim.py
Luke Kenneth Casson Leighton [Fri, 18 Sep 2020 13:11:24 +0000 (14:11 +0100)]
can remove unneeded overrides of Prev/Next Control
Jacob Lifshay [Thu, 17 Sep 2020 22:32:22 +0000 (15:32 -0700)]
add divwe regression test case
Jacob Lifshay [Thu, 17 Sep 2020 22:31:50 +0000 (15:31 -0700)]
re-enable test case -- no longer goes into an infinite loop
Jacob Lifshay [Thu, 17 Sep 2020 22:24:40 +0000 (15:24 -0700)]
fix bug #492
Jacob Lifshay [Thu, 17 Sep 2020 21:30:36 +0000 (14:30 -0700)]
replace sim._state.timeline.now with sim._engine.now
Luke Kenneth Casson Leighton [Thu, 17 Sep 2020 10:36:43 +0000 (11:36 +0100)]
add versa ecp5 fpga litex build script
Cole Poirier [Wed, 16 Sep 2020 22:34:13 +0000 (15:34 -0700)]
complete first translation pass of dmi_dtm_xilinx.vhdl into nmigen,
different sync domains indicated as 'sync = m.d.[SYS|JTAG]_sync', left
some parts undone, didn't rearrange or clean up so Luke can easily
compare with original
Luke Kenneth Casson Leighton [Wed, 16 Sep 2020 21:54:15 +0000 (22:54 +0100)]
make a start on LS180 platform
Cole Poirier [Wed, 16 Sep 2020 20:48:08 +0000 (13:48 -0700)]
initial commit of JTAGToDMI debug interface translated from
microwatt/dmi_dtm_xilinx.vhdl
Cole Poirier [Wed, 16 Sep 2020 20:44:38 +0000 (13:44 -0700)]
add template file/starting point (copy of litex/boards/platforms/ulx3s.py) for asic platform that derives from generic platform for 180nm
tapeout
Luke Kenneth Casson Leighton [Tue, 15 Sep 2020 20:27:47 +0000 (21:27 +0100)]
add back (totally confusing) accidentally-removed code due to use of "types"
(which should not be placed in the .py file, they should only go in a .pyi)
Luke Kenneth Casson Leighton [Tue, 15 Sep 2020 20:26:01 +0000 (21:26 +0100)]
instantiate MMU from AllFunctionUnits
Luke Kenneth Casson Leighton [Tue, 15 Sep 2020 20:19:51 +0000 (21:19 +0100)]
do not need FAST regs in MMU
Luke Kenneth Casson Leighton [Tue, 15 Sep 2020 19:38:37 +0000 (20:38 +0100)]
comment mmu test
Luke Kenneth Casson Leighton [Tue, 15 Sep 2020 19:36:18 +0000 (20:36 +0100)]
add edge-triggering to dcache/mmu "valid"
Luke Kenneth Casson Leighton [Tue, 15 Sep 2020 17:23:16 +0000 (18:23 +0100)]
add set MTSPR prtbl to mmu unit test
Luke Kenneth Casson Leighton [Tue, 15 Sep 2020 16:11:47 +0000 (17:11 +0100)]
add OP_MFSPR to mmu
Luke Kenneth Casson Leighton [Tue, 15 Sep 2020 15:43:30 +0000 (16:43 +0100)]
use convenience vars
Luke Kenneth Casson Leighton [Tue, 15 Sep 2020 15:40:25 +0000 (16:40 +0100)]
add OP_TLBIE to mmu fsm
Luke Kenneth Casson Leighton [Tue, 15 Sep 2020 15:22:01 +0000 (16:22 +0100)]
add OP_DCBZ to mmu fsm, needs RA to be added to MMU pipe_data
Luke Kenneth Casson Leighton [Tue, 15 Sep 2020 14:16:12 +0000 (15:16 +0100)]
add MMU MTSPR connection into FSM
Luke Kenneth Casson Leighton [Tue, 15 Sep 2020 11:52:04 +0000 (12:52 +0100)]
add in MMU and DCache into MMU FSM
Luke Kenneth Casson Leighton [Tue, 15 Sep 2020 11:34:56 +0000 (12:34 +0100)]
moved PLRU to nmutil
Luke Kenneth Casson Leighton [Tue, 15 Sep 2020 10:41:49 +0000 (11:41 +0100)]
add mmu fsm
Luke Kenneth Casson Leighton [Tue, 15 Sep 2020 10:30:12 +0000 (11:30 +0100)]
remove more (confusing/spurious) types, should be in .pyi file
Luke Kenneth Casson Leighton [Tue, 15 Sep 2020 10:28:59 +0000 (11:28 +0100)]
remove more (confusing/spurious) types, should be in .pyi file
Luke Kenneth Casson Leighton [Tue, 15 Sep 2020 10:24:38 +0000 (11:24 +0100)]
remove more (confusing/spurious) types, should be in .pyi file
Luke Kenneth Casson Leighton [Tue, 15 Sep 2020 10:06:55 +0000 (11:06 +0100)]
removed (confusing/spurious) types, should be in .pyi file
Luke Kenneth Casson Leighton [Tue, 15 Sep 2020 09:58:34 +0000 (10:58 +0100)]
add MMU FunctionUnit
Luke Kenneth Casson Leighton [Tue, 15 Sep 2020 09:23:30 +0000 (10:23 +0100)]
mmu uses RB, go with it
Luke Kenneth Casson Leighton [Tue, 15 Sep 2020 09:22:31 +0000 (10:22 +0100)]
add OP_TLBIE
Luke Kenneth Casson Leighton [Tue, 15 Sep 2020 09:13:43 +0000 (10:13 +0100)]
add mmu initial pipe_data.py
Luke Kenneth Casson Leighton [Tue, 15 Sep 2020 08:46:00 +0000 (09:46 +0100)]
add extra "modes" to PortInterface
Luke Kenneth Casson Leighton [Tue, 15 Sep 2020 07:48:57 +0000 (08:48 +0100)]
syntax error correction
Luke Kenneth Casson Leighton [Tue, 15 Sep 2020 07:46:50 +0000 (08:46 +0100)]
add inline comments into icache.py
Cole Poirier [Mon, 14 Sep 2020 18:41:07 +0000 (11:41 -0700)]
icache.py add missing funciton bodies, add missing return statment, fix
variable names, fix typos
Luke Kenneth Casson Leighton [Mon, 14 Sep 2020 15:59:21 +0000 (16:59 +0100)]
increase TLB_NUM_WAYS to 4
Luke Kenneth Casson Leighton [Mon, 14 Sep 2020 15:58:58 +0000 (16:58 +0100)]
vhdl conversion not really working for plru
Luke Kenneth Casson Leighton [Mon, 14 Sep 2020 13:51:45 +0000 (14:51 +0100)]
add array signal names
Luke Kenneth Casson Leighton [Mon, 14 Sep 2020 13:46:53 +0000 (14:46 +0100)]
rename plru input
Luke Kenneth Casson Leighton [Mon, 14 Sep 2020 13:46:36 +0000 (14:46 +0100)]
rename plru input
Luke Kenneth Casson Leighton [Mon, 14 Sep 2020 12:34:32 +0000 (13:34 +0100)]
reorg mmu lookup test so it is called twice
Luke Kenneth Casson Leighton [Mon, 14 Sep 2020 12:34:15 +0000 (13:34 +0100)]
TLB PLRUs are of TLB_WAY_BITS width
Luke Kenneth Casson Leighton [Mon, 14 Sep 2020 12:24:23 +0000 (13:24 +0100)]
fix mmu perms/lookup in dcache
Luke Kenneth Casson Leighton [Mon, 14 Sep 2020 11:52:34 +0000 (12:52 +0100)]
whitespace
Luke Kenneth Casson Leighton [Mon, 14 Sep 2020 11:52:17 +0000 (12:52 +0100)]
remove duplicated signal
Luke Kenneth Casson Leighton [Mon, 14 Sep 2020 10:07:04 +0000 (11:07 +0100)]
comments on icache
Luke Kenneth Casson Leighton [Mon, 14 Sep 2020 10:05:49 +0000 (11:05 +0100)]
get rid of rst
Luke Kenneth Casson Leighton [Mon, 14 Sep 2020 10:00:34 +0000 (11:00 +0100)]
use word_select
Luke Kenneth Casson Leighton [Mon, 14 Sep 2020 09:58:02 +0000 (10:58 +0100)]
add mmu-dcache test
Cole Poirier [Mon, 14 Sep 2020 01:09:23 +0000 (18:09 -0700)]
icache.py connect up all the sub-functions, fix typos and other small
errors I get running the file, hit a wall with current error so stopping for today
Cole Poirier [Mon, 14 Sep 2020 00:16:20 +0000 (17:16 -0700)]
icache.py add parameters to 'process' functions, fix small errors
Cole Poirier [Sun, 13 Sep 2020 23:46:03 +0000 (16:46 -0700)]
icache.py move get/read/write functions out of ICache class to top of
file under constants
Cole Poirier [Sun, 13 Sep 2020 22:34:35 +0000 (15:34 -0700)]
icache.py copy simulation code from dcache.py, fix syntax
Cole Poirier [Sun, 13 Sep 2020 22:06:32 +0000 (15:06 -0700)]
icache.py fix syntax, move all constants and Array/type creation
functions to top of file
Cole Poirier [Sun, 13 Sep 2020 21:26:13 +0000 (14:26 -0700)]
icache.py fix syntax errors that occured when running python3 icache.py
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 19:11:40 +0000 (20:11 +0100)]
dcache truncate wishbone address, store real_addr in alternative
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 17:42:36 +0000 (18:42 +0100)]
last mmu get seems ok
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 17:37:07 +0000 (18:37 +0100)]
whoops recursion error v.shift calculated from v.shift
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 16:57:34 +0000 (17:57 +0100)]
more experimenting with mmu READ_WAIT state
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 16:40:39 +0000 (17:40 +0100)]
radix tree wait error, investigating
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 15:57:04 +0000 (16:57 +0100)]
mmu test starting to make sense
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 14:40:51 +0000 (15:40 +0100)]
floundering around with MMU unit test, no idea what to do
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 14:18:17 +0000 (15:18 +0100)]
mmu code-morph
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 13:43:07 +0000 (14:43 +0100)]
code-morph, add masked function
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 13:30:33 +0000 (14:30 +0100)]
move code to mmu_0
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 13:22:34 +0000 (14:22 +0100)]
add example radix walk from power-gem5
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 13:16:18 +0000 (14:16 +0100)]
MMU test
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 12:55:46 +0000 (13:55 +0100)]
submodule update
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 11:39:33 +0000 (12:39 +0100)]
clarify
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 11:25:24 +0000 (12:25 +0100)]
sort out ariane PLRU, rename/clarify
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 10:36:59 +0000 (11:36 +0100)]
minor error in plru
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 10:17:06 +0000 (11:17 +0100)]
rename cache_valid_bits to cache_validsg
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 10:16:10 +0000 (11:16 +0100)]
cache_valid_idx too large in dcache
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 09:59:33 +0000 (10:59 +0100)]
whoops, cache valid array too small in dcache
Luke Kenneth Casson Leighton [Sat, 12 Sep 2020 23:07:02 +0000 (00:07 +0100)]
more dcache debugging
Luke Kenneth Casson Leighton [Sat, 12 Sep 2020 22:21:22 +0000 (23:21 +0100)]
missing reservation address comparison
Luke Kenneth Casson Leighton [Sat, 12 Sep 2020 22:17:17 +0000 (23:17 +0100)]
dcache tidyup
Luke Kenneth Casson Leighton [Sat, 12 Sep 2020 20:09:50 +0000 (21:09 +0100)]
more dcache debugging
Luke Kenneth Casson Leighton [Sat, 12 Sep 2020 15:16:03 +0000 (16:16 +0100)]
add random dcache mem test
Luke Kenneth Casson Leighton [Sat, 12 Sep 2020 13:09:43 +0000 (14:09 +0100)]
cache valid corrupted: fixed
Luke Kenneth Casson Leighton [Sat, 12 Sep 2020 10:44:46 +0000 (11:44 +0100)]
adding names to array signals
Luke Kenneth Casson Leighton [Sat, 12 Sep 2020 10:14:38 +0000 (11:14 +0100)]
whoops, indentation error
Luke Kenneth Casson Leighton [Sat, 12 Sep 2020 10:14:22 +0000 (11:14 +0100)]
enable Display debugs
Luke Kenneth Casson Leighton [Sat, 12 Sep 2020 08:36:13 +0000 (09:36 +0100)]
set bytesel in dcache store
Luke Kenneth Casson Leighton [Fri, 11 Sep 2020 20:46:42 +0000 (21:46 +0100)]
separat stbs_done into ld/st