mesa.git
5 years agost/mesa: Fix GL_MAP_COLOR with glDrawPixels GL_COLOR_INDEX
Danylo Piliaiev [Wed, 3 Apr 2019 15:09:24 +0000 (18:09 +0300)]
st/mesa: Fix GL_MAP_COLOR with glDrawPixels GL_COLOR_INDEX

Documentation for glDrawPixels with GL_COLOR_INDEX says:
 "If the GL is in color index mode, and if GL_MAP_COLOR is true,
  the index is replaced with the value that it references in
  lookup table GL_PIXEL_MAP_I_TO_I"

We are always in RGBA mode and there is nothing in documentation
about GL_MAP_COLOR in RGBA mode for GL_COLOR_INDEX.

Scale and bias are also only applicable for RGBA format and not
mentioned for GL_COLOR_INDEX.

Thus the behaviour will be on par with i965.

Fixes: gl-1.0-drawpixels-color-index
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
5 years agogallium/hud: fix rounding error in nic bps computation
Eric Engestrom [Tue, 19 Mar 2019 14:15:35 +0000 (14:15 +0000)]
gallium/hud: fix rounding error in nic bps computation

While at it, fix typo in "rounding error" :P

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agogallium/hud: prevent buffer overflow
Eric Engestrom [Tue, 19 Mar 2019 14:11:48 +0000 (14:11 +0000)]
gallium/hud: prevent buffer overflow

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agogallium/hud: fix memory leaks
Eric Engestrom [Tue, 19 Mar 2019 14:11:09 +0000 (14:11 +0000)]
gallium/hud: fix memory leaks

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoradeonsi: enable displayable DCC on Ravens
Marek Olšák [Wed, 9 Jan 2019 01:08:08 +0000 (20:08 -0500)]
radeonsi: enable displayable DCC on Ravens

5 years agoradeonsi: add support for displayable DCC for multi-RB chips
Marek Olšák [Sat, 5 Jan 2019 00:39:01 +0000 (19:39 -0500)]
radeonsi: add support for displayable DCC for multi-RB chips

A compute shader is used to reorder DCC data from aligned to unaligned.

5 years agoradeonsi: add support for displayable DCC for 1 RB chips
Marek Olšák [Sat, 5 Jan 2019 00:19:54 +0000 (19:19 -0500)]
radeonsi: add support for displayable DCC for 1 RB chips

This is the simpler codepath - just disable RB and pipe alignment for DCC.

5 years agoradeonsi: add ability to bind images as image buffers
Marek Olšák [Sat, 5 Jan 2019 00:27:27 +0000 (19:27 -0500)]
radeonsi: add ability to bind images as image buffers

so that we can bind DCC (texture) as an image buffer.

5 years agoradeonsi/gfx9: add support for PIPE_ALIGNED=0
Marek Olšák [Fri, 9 Nov 2018 21:51:47 +0000 (16:51 -0500)]
radeonsi/gfx9: add support for PIPE_ALIGNED=0

Needed by displayable DCC.

We need to flush L2 after rendering if PIPE_ALIGNED=0 and DCC is enabled.

5 years agoamd/addrlib: fix uninitialized values for Addr2ComputeDccAddrFromCoord
Marek Olšák [Wed, 3 Apr 2019 21:17:08 +0000 (17:17 -0400)]
amd/addrlib: fix uninitialized values for Addr2ComputeDccAddrFromCoord

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoiris: move variable to the scope where it is being used
Tapani Pälli [Tue, 2 Apr 2019 06:12:21 +0000 (09:12 +0300)]
iris: move variable to the scope where it is being used

iris_upload_border_color is passed a pointer which points to
variable that is introduced in a different scope.

CID: 1444296
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agost/nir: run st_nir_opts after 64bit ops lowering
Tapani Pälli [Tue, 2 Apr 2019 05:56:07 +0000 (08:56 +0300)]
st/nir: run st_nir_opts after 64bit ops lowering

CID: 1444309
Fixes: 9ab1b1d0227 "st/nir: Move 64-bit lowering later"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agopanfrost: Size tiled temp buffers correctly
Alyssa Rosenzweig [Wed, 3 Apr 2019 03:52:36 +0000 (03:52 +0000)]
panfrost: Size tiled temp buffers correctly

This should lower transient memory usage and improve performance
slightly (due to less memory to malloc/free, better cache locality,
etc).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost: Respect box->width in tiled stores
Alyssa Rosenzweig [Wed, 3 Apr 2019 03:36:38 +0000 (03:36 +0000)]
panfrost: Respect box->width in tiled stores

This fixes a regression uploading partial tiled textures introduced
sometime during the cubemap series.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost: Cleanup some indirection in pan_resource
Alyssa Rosenzweig [Wed, 3 Apr 2019 02:15:18 +0000 (02:15 +0000)]
panfrost: Cleanup some indirection in pan_resource

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost: Implement system values
Alyssa Rosenzweig [Wed, 3 Apr 2019 01:48:09 +0000 (01:48 +0000)]
panfrost: Implement system values

This patch implements system values via specially-crafted uniforms.
While we previously had an ad hoc system for passing the viewport into
the vertex shader, this commit generalizes the system to allow for
arbitrary system values to be added to both shader stages. While we're
at it, we clean up uniform handling code (which was considerably muddied
to handle the ad hoc viewport uniform).

This commit serves as both a cleanup of the existing codebase and the
precursor to new functionality, like implementing textureSize().

Concurrent with these changes is respecting the depth transform, which
was not possible with the old fixed uniform system and here serves as a
proof-of-correctness test (as well as justifying the NIR changes).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agonir: Add "viewport vector" system values
Alyssa Rosenzweig [Wed, 3 Apr 2019 01:45:44 +0000 (01:45 +0000)]
nir: Add "viewport vector" system values

While a partial set of viewport system values exist, these are scalar
values, which is a poor fit for viewport transformations on vector ISAs
like Midgard (where the vec3 values for scale and offset each need to be
coherent in a vec4 uniform slot to take advantage of vectorized
transform math). This patch adds vec3 scale/offset fields corresponding
to the 3D Gallium viewport / glViewport+depth

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agovirgl: also destroy all read-transfers
Erik Faye-Lund [Tue, 2 Apr 2019 08:48:30 +0000 (10:48 +0200)]
virgl: also destroy all read-transfers

For texture write-transfers, we either free them on the transfer-queue
or right away. But for read-transfers, we currently only destroy them in
case they used a temp-resource. This leads to occasional resource-leaks.

Let's add a call to virgl_resource_destroy_transfer in the missing case.

Do the same thing for buffers as well, but the logic is a bit easier to
follow there.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes: f0e71b10888 ("virgl: use transfer queue")
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
5 years agomeson: Error if LLVM is turned off but clover it turned on
Dylan Baker [Mon, 1 Apr 2019 17:14:54 +0000 (10:14 -0700)]
meson: Error if LLVM is turned off but clover it turned on

Since clover has a hard requirement on LLVM

v2: - make error message more specific

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
5 years agomeson: Error if LLVM doesn't have rtti when building clover
Dylan Baker [Mon, 1 Apr 2019 17:12:03 +0000 (10:12 -0700)]
meson: Error if LLVM doesn't have rtti when building clover

We already do this for nouveau, but it's required for clover too.

5 years agopanfrost: Remove support for legacy kernels
Alyssa Rosenzweig [Sun, 31 Mar 2019 19:06:05 +0000 (19:06 +0000)]
panfrost: Remove support for legacy kernels

Previously, there was minimal support for interoperating with legacy
kernels (reusing kernel modules originally designed for proprietary
legacy userspaces, rather than for upstream-friendly free software
stacks). Now that the Panfrost kernel is stabilising, this commit drops
the legacy code path.

Panfrost users need to use a modern, mainline kernel supporting the
Panfrost kernel driver from this commit forward.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
5 years agoetnaviv: only try to construct scanout resource when on KMS winsys
Lucas Stach [Wed, 27 Mar 2019 11:25:18 +0000 (12:25 +0100)]
etnaviv: only try to construct scanout resource when on KMS winsys

Trying to construct a scanout capable buffer will only ever work when
when we are on top of a KMS winsys, as the render node isn't capable
of allocating contiguous buffers.

Tested-by: Marius Vlad <marius.vlad@collabora.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
5 years agoetnaviv: flush all pending contexts when accessing a resource with the CPU
Lucas Stach [Wed, 27 Mar 2019 11:22:58 +0000 (12:22 +0100)]
etnaviv: flush all pending contexts when accessing a resource with the CPU

When setting up a transfer to a resource, all contexts where the resource
is pending must be flushed. Otherwise a write transfer might be started
in the current context before all contexts that access the resource in
shared (read) mode have been executed.

Fixes: 64813541d575 (etnaviv: fix resource usage tracking across
different pipe_context's)
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-By: Guido Günther <agx@sigxcpu.org>
5 years agoetnaviv: don't flush own context when updating resource use
Lucas Stach [Wed, 27 Mar 2019 11:22:57 +0000 (12:22 +0100)]
etnaviv: don't flush own context when updating resource use

The context is self synchronizing at the GPU side, as commands are
executed in order. We must not flush our own context when updating the
resource use, as that leads to excessive flushing on effectively every
draw call, causing huge CPU overhead.

Fixes: 64813541d575 (etnaviv: fix resource usage tracking across
different pipe_context's)
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
5 years agoetnaviv: shrink struct etna_3d_state
Christian Gmeiner [Wed, 27 Mar 2019 13:58:16 +0000 (14:58 +0100)]
etnaviv: shrink struct etna_3d_state

Drop struct members which are only written to but never read from.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
5 years agointel/compiler: use defined size for vector components
Dave Airlie [Wed, 3 Apr 2019 02:20:40 +0000 (12:20 +1000)]
intel/compiler: use defined size for vector components

If we increase vector sizing later it would be nice to avoid
tripped over this again.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
5 years agonir: use proper array sizing define for vectors
Dave Airlie [Wed, 3 Apr 2019 02:20:02 +0000 (12:20 +1000)]
nir: use proper array sizing define for vectors

If we increase the vector size in the future it would be good
to not have to fix these up, this should change nothing at present.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
5 years agoRevert "nir: propagate known constant values into the if-then branch"
Timothy Arceri [Wed, 3 Apr 2019 02:24:18 +0000 (13:24 +1100)]
Revert "nir: propagate known constant values into the if-then branch"

This reverts commit 4218b6422cf1ff70c7f0feeec699a35e88522ed7.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110311

5 years agonir: propagate known constant values into the if-then branch
Timothy Arceri [Fri, 23 Nov 2018 00:49:19 +0000 (11:49 +1100)]
nir: propagate known constant values into the if-then branch

Helps Max Waves / VGPR use in a bunch of Unigine Heaven
shaders.

shader-db results radeonsi (VEGA):
Totals from affected shaders:
SGPRS: 5505440 -> 5505872 (0.01 %)
VGPRS: 3077520 -> 3077296 (-0.01 %)
Spilled SGPRs: 39032 -> 39030 (-0.01 %)
Spilled VGPRs: 16326 -> 16326 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 744 -> 744 (0.00 %) dwords per thread
Code Size: 123755028 -> 123753316 (-0.00 %) bytes
Compile Time: 2751028 -> 2560786 (-6.92 %) milliseconds
LDS: 1415 -> 1415 (0.00 %) blocks
Max Waves: 972192 -> 972240 (0.00 %)
Wait states: 0 -> 0 (0.00 %)

vkpipeline-db results RADV (VEGA):

Totals from affected shaders:
SGPRS: 160 -> 160 (0.00 %)
VGPRS: 88 -> 88 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 18268 -> 18152 (-0.63 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 26 -> 26 (0.00 %)
Wait states: 0 -> 0 (0.00 %)

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
5 years agovirgl: close drm fd when destroying virgl screen.
Lepton Wu [Mon, 18 Mar 2019 23:40:25 +0000 (16:40 -0700)]
virgl: close drm fd when destroying virgl screen.

This fd was create in virgl_drm_screen_create and should be closed
in virgl_drm_screen_destroy.

Signed-off-by: Lepton Wu <lepton@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
5 years agoiris: Enable fast clears on gen8.
Rafael Antognolli [Tue, 26 Mar 2019 22:35:00 +0000 (15:35 -0700)]
iris: Enable fast clears on gen8.

Since we are now properly storing the clear color with SCS bits, we can
now enable fast clears on gen8 too.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoiris: Add aux.sampler_usages.
Rafael Antognolli [Wed, 27 Mar 2019 21:42:12 +0000 (14:42 -0700)]
iris: Add aux.sampler_usages.

We want to skip some types of aux usages (for instance,
ISL_AUX_USAGE_HIZ when the hardware doesn't support it, or when we have
multisampling) when sampling from the surface.

Instead of checking for those cases while filling the surface state and
leaving it blank, let's have a version of aux.possible_usages for
sampling. This way we can also avoid allocating surface state for the
cases we don't use.

Fixes: a8b5ea8ef015ed4a "iris: Add function to update clear color in surface state."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoiris: Do not allocate clear_color_bo for gen8.
Rafael Antognolli [Tue, 26 Mar 2019 23:28:10 +0000 (16:28 -0700)]
iris: Do not allocate clear_color_bo for gen8.

Since we are not using it for the clear color, there's no need to
allocate it.

Fixes: a8b5ea8ef015ed4a "iris: Add function to update clear color in surface state."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoiris: Manually apply fast clear color channel overrides.
Rafael Antognolli [Wed, 27 Mar 2019 17:27:18 +0000 (10:27 -0700)]
iris: Manually apply fast clear color channel overrides.

At the fast clear time, the only swizzle we have available is actually
the identity swizzle (which we use for most rendering). So the call to
swizzle_color_value() becomes simply a no-op, and doesn't properly zero
out the unused channels.

We have to manually override those channels.

Fixes: a8b5ea8ef015ed4a "iris: Add function to update clear color in surface state."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoiris/gen8: Re-emit the SURFACE_STATE if the clear color changed.
Rafael Antognolli [Wed, 27 Mar 2019 20:09:34 +0000 (13:09 -0700)]
iris/gen8: Re-emit the SURFACE_STATE if the clear color changed.

The swizzle for rendering surfaces is always identity. So when we are
doing the fast clear, we don't have enough information to store the
clear color OR'ed with the Shader Channel Select bits for the dword in
the SURFACE_STATE.

Instead of trying to patch up the SURFACE_STATE correctly later, by
reading the color from the clear color state buffer and then doing all
the operations to store it, let's just re-emit the whole SURFACE_STATE.
That should make things way simpler on gen8, and we can still use the
clear color state buffer for gen9+.

Fixes: a8b5ea8ef015ed4a "iris: Add function to update clear color in surface state."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoiris: Only update clear color for gens 8 and 9.
Rafael Antognolli [Tue, 26 Mar 2019 18:08:22 +0000 (11:08 -0700)]
iris: Only update clear color for gens 8 and 9.

Newer gens can read it directly.

Also properly skip updating the ISL_AUX_USAGE_NONE surface.

Fixes: a8b5ea8ef015ed4a "iris: Add function to update clear color in surface state."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agohaiku: Fix hgl dispatch build. Tested under meson/scons.
Alexander von Gluck IV [Sun, 31 Mar 2019 00:15:40 +0000 (00:15 +0000)]
haiku: Fix hgl dispatch build. Tested under meson/scons.

Reviewed-by: Brian Paul <brianp@vmware.com>
5 years agodocs: Fix 19.0.x version numbers
Guido Günther [Mon, 1 Apr 2019 15:58:24 +0000 (17:58 +0200)]
docs: Fix 19.0.x version numbers

The list has 19.0.2 twice.

Signed-off-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
5 years agodocs/relnotes: document parallel_shader_compile changes in 19.1.0, not 19.0.0
Marek Olšák [Tue, 2 Apr 2019 14:47:37 +0000 (10:47 -0400)]
docs/relnotes: document parallel_shader_compile changes in 19.1.0, not 19.0.0

5 years agoCI: use wayland ci-templates repo to create the base image
Benjamin Tissoires [Tue, 2 Apr 2019 07:24:00 +0000 (09:24 +0200)]
CI: use wayland ci-templates repo to create the base image

There shouldn't be a difference for users, but this way we do manage
all of our containers from freedesktop.org

note: compared to the provious Dockerfile, we need to manually
      add gcc, g++ and python*-wheel

Signed-off-by: Benjamin Tissoires <benjamin.tissoires@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
5 years agoradeonsi: don't use PFP_SYNC_ME with compute-only contexts
Marek Olšák [Mon, 1 Apr 2019 16:29:43 +0000 (12:29 -0400)]
radeonsi: don't use PFP_SYNC_ME with compute-only contexts

Compute rings don't have PFP.

Fixes: a1378639ab1 "radeonsi: always use compute rings for clover on CI and newer (v2)"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Jan Vesely <jan.vesely@rutgers.edu>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
5 years agovirgl: define MAX_VERTEX_STREAMS based on availability of TF3
Gert Wollny [Wed, 13 Mar 2019 17:50:52 +0000 (18:50 +0100)]
virgl: define MAX_VERTEX_STREAMS based on availability of TF3

Since with gles hosts we lie about the GLSL feature level it is better
to set the number of streams based on actual hosts capabilities.

v2: Make use of feature check level to avoid regressions.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-By: Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
5 years agosoftpipe: Implement ATOMFADD and enable cap TGSI_ATOMFADD
Gert Wollny [Tue, 19 Mar 2019 16:24:26 +0000 (17:24 +0100)]
softpipe: Implement ATOMFADD and enable cap TGSI_ATOMFADD

This enables the following piglits with PASS:
  nv_shader_atomic_float/execution/
    shared-atomicadd-float
    shared-atomicexchange-float
    ssbo-atomicadd-float
    ssbo-atomicexchange-float

v2: Minimize the patch by using type punning (Eric Anholt)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
5 years agovirgl: stricter usage of compressed 3d textures
Erik Faye-Lund [Thu, 28 Mar 2019 18:03:47 +0000 (19:03 +0100)]
virgl: stricter usage of compressed 3d textures

Using RGTC, ETC1, ETC2 or S3TC for 3D-textures isn't alowed by any of
OpenGL 4.6, OpenGL ES 3.2, ARB_texture_compression_rgtc,
EXT_texture_compression_rgtc, OES_compressed_ETC1_RGB8_texture,
S3_s3tc or EXT_texture_compression_s3tc specifications.

So let's not allow any of those compressed 3d-textures at all. It's not
going to work once it hits the OpenGL driver in virglrenderer.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
5 years agovirgl: do not allow compressed formats for buffers
Erik Faye-Lund [Fri, 29 Mar 2019 09:48:33 +0000 (10:48 +0100)]
virgl: do not allow compressed formats for buffers

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
5 years agodri3: Return the current swap interval from glXGetSwapIntervalMESA().
Eric Anholt [Fri, 29 Mar 2019 17:16:05 +0000 (10:16 -0700)]
dri3: Return the current swap interval from glXGetSwapIntervalMESA().

We were caching only the value set with glXSwapIntervalSGI(), missing out
on the default setting of the swap interval by the loader.  This fixes
glxgears's warning about being vblank synchronized by default.

Fixes: 9777c4234b0e ("loader: drop the [gs]et_swap_interval callbacks")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
5 years agointel: Add support for Comet Lake
Anuj Phogat [Fri, 29 Mar 2019 20:13:01 +0000 (13:13 -0700)]
intel: Add support for Comet Lake

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
5 years agoiris: Adapt to variable ppGTT size
Chris Wilson [Mon, 1 Apr 2019 10:39:46 +0000 (11:39 +0100)]
iris: Adapt to variable ppGTT size

Not all hardware is made equal and some does not have the full
complement of 48b of address space. Ask what the actual size of virtual
address space allocated for contexts, and bail if that is not enough to
satisfy our static partitioning needs.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoradv: partially enable VK_KHR_shader_float16_int8
Samuel Pitoiset [Mon, 1 Apr 2019 14:18:11 +0000 (16:18 +0200)]
radv: partially enable VK_KHR_shader_float16_int8

Only 8-bit integers for now, float16 requires a bit more work.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoac: add 8-bit and 64-bit support to ac_build_bitfield_reverse()
Samuel Pitoiset [Mon, 1 Apr 2019 14:18:10 +0000 (16:18 +0200)]
ac: add 8-bit and 64-bit support to ac_build_bitfield_reverse()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoac: add 8-bit support to ac_build_umsb()
Samuel Pitoiset [Mon, 1 Apr 2019 14:18:09 +0000 (16:18 +0200)]
ac: add 8-bit support to ac_build_umsb()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoac: add 8-bit support to ac_find_lsb()
Samuel Pitoiset [Mon, 1 Apr 2019 14:18:08 +0000 (16:18 +0200)]
ac: add 8-bit support to ac_find_lsb()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoac: add 8-bit support to ac_build_bit_count()
Samuel Pitoiset [Mon, 1 Apr 2019 14:18:07 +0000 (16:18 +0200)]
ac: add 8-bit support to ac_build_bit_count()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoac/nir: add support for nir_op_b2i8
Samuel Pitoiset [Mon, 1 Apr 2019 14:18:06 +0000 (16:18 +0200)]
ac/nir: add support for nir_op_b2i8

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradeonsi: implement ARB/KHR_parallel_shader_compile callbacks
Marek Olšák [Mon, 6 Aug 2018 11:11:33 +0000 (07:11 -0400)]
radeonsi: implement ARB/KHR_parallel_shader_compile callbacks

5 years agoutil/queue: add util_queue_adjust_num_threads
Marek Olšák [Tue, 7 Aug 2018 00:40:05 +0000 (20:40 -0400)]
util/queue: add util_queue_adjust_num_threads

for ARB_parallel_shader_compile

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
5 years agoutil/queue: hold a lock when reading num_threads in util_queue_finish
Marek Olšák [Tue, 7 Aug 2018 00:34:24 +0000 (20:34 -0400)]
util/queue: hold a lock when reading num_threads in util_queue_finish

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
5 years agoutil/queue: add ability to kill a subset of threads
Marek Olšák [Tue, 7 Aug 2018 00:32:31 +0000 (20:32 -0400)]
util/queue: add ability to kill a subset of threads

for ARB_parallel_shader_compile

5 years agoutil/queue: move thread creation into a separate function
Marek Olšák [Tue, 7 Aug 2018 00:15:43 +0000 (20:15 -0400)]
util/queue: move thread creation into a separate function

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
5 years agogallium: implement ARB/KHR_parallel_shader_compile
Marek Olšák [Mon, 6 Aug 2018 11:09:28 +0000 (07:09 -0400)]
gallium: implement ARB/KHR_parallel_shader_compile

5 years agomesa: implement ARB/KHR_parallel_shader_compile
Marek Olšák [Mon, 6 Aug 2018 11:05:19 +0000 (07:05 -0400)]
mesa: implement ARB/KHR_parallel_shader_compile

Tested by piglit.

5 years agoradeonsi: fix assertion failure by using the correct type
Marek Olšák [Wed, 27 Feb 2019 23:31:54 +0000 (18:31 -0500)]
radeonsi: fix assertion failure by using the correct type

src/gallium/drivers/radeonsi/si_state_viewport.c:196: si_emit_guardband:
Assertion `vp_as_scissor.maxx <= max_viewport_size[vp_as_scissor.quant_mode]
&& vp_as_scissor.maxy <= max_viewport_size[vp_as_scissor.quant_mode]' failed.

The comparison was unsigned, so negative maxx or maxy would fail.

Fixes: 3c540e0a7488 "radeonsi: Fix guardband computation for large render targets"
5 years agoradeon/vcn/vp9: search the render target from the whole list
Leo Liu [Wed, 27 Mar 2019 12:37:28 +0000 (08:37 -0400)]
radeon/vcn/vp9: search the render target from the whole list

The number of render targets could be more than max of references,
so we search the full list of the render pictures for the current
render target index

https://bugs.freedesktop.org/show_bug.cgi?id=109648

Signed-off-by: Leo Liu <leo.liu@amd.com>
Tested-by: James Zhu <James.Zhu@amd.com>
Acked-by: James Zhu<James.Zhu@amd.com>
Cc: <mesa-stable@lists.freedesktop.org>
5 years agoradv: lower 16-bit flrp
Rhys Perry [Thu, 6 Dec 2018 14:01:15 +0000 (14:01 +0000)]
radv: lower 16-bit flrp

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agoac: fix ac_build_umsb() for 16-bit integer type
Samuel Pitoiset [Tue, 26 Mar 2019 10:34:46 +0000 (11:34 +0100)]
ac: fix ac_build_umsb() for 16-bit integer type

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoac: fix ac_find_lsb() for 16-bit integer type
Samuel Pitoiset [Tue, 26 Mar 2019 10:34:45 +0000 (11:34 +0100)]
ac: fix ac_find_lsb() for 16-bit integer type

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoac: fix ac_build_bitfield_reverse() for 16-bit integer type
Samuel Pitoiset [Tue, 26 Mar 2019 10:34:44 +0000 (11:34 +0100)]
ac: fix ac_build_bitfield_reverse() for 16-bit integer type

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoac: fix ac_build_bit_count() for 16-bit integer type
Samuel Pitoiset [Tue, 26 Mar 2019 10:34:43 +0000 (11:34 +0100)]
ac: fix ac_build_bit_count() for 16-bit integer type

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoac/nir: fix nir_op_b2i16
Samuel Pitoiset [Tue, 26 Mar 2019 10:34:42 +0000 (11:34 +0100)]
ac/nir: fix nir_op_b2i16

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agomeson: strip rpath from megadrivers
Eric Engestrom [Tue, 26 Mar 2019 11:21:09 +0000 (11:21 +0000)]
meson: strip rpath from megadrivers

More specifically, use the library file that has been post-processed by Meson
when creating the hardlinks.

Bugs: https://bugs.freedesktop.org/show_bug.cgi?id=108766
Fixes: 3218056e0eb375eeda47 "meson: Build i965 and dri stack"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
5 years agospirv: fix a compiler warning
Tapani Pälli [Thu, 28 Mar 2019 09:35:27 +0000 (11:35 +0200)]
spirv: fix a compiler warning

Fixes implicit conversion from enumeration type 'SpvOp' warning.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agoi965: perf: update render basic configs for big core gen9/gen10
Lionel Landwerlin [Sun, 31 Mar 2019 09:41:17 +0000 (10:41 +0100)]
i965: perf: update render basic configs for big core gen9/gen10

This updates allows an MI_LRI to trigger a OA report write in the
global OA buffer. This isn't really useful for us, we just keep close
to the internal public configs.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoi965: perf: add ring busyness metric for cfl gt2
Lionel Landwerlin [Sun, 31 Mar 2019 09:38:19 +0000 (10:38 +0100)]
i965: perf: add ring busyness metric for cfl gt2

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoi965: perf: enable Icelake metrics
Lionel Landwerlin [Fri, 4 May 2018 11:28:57 +0000 (12:28 +0100)]
i965: perf: enable Icelake metrics

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoi965: perf: add Icelake metrics
Lionel Landwerlin [Fri, 4 May 2018 11:28:34 +0000 (12:28 +0100)]
i965: perf: add Icelake metrics

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoi965: perf: sklgt2: drop programming of an unused NOA register
Lionel Landwerlin [Fri, 4 May 2018 10:32:07 +0000 (11:32 +0100)]
i965: perf: sklgt2: drop programming of an unused NOA register

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoi965: perf: hsw: drop register programming not needed on HSW
Lionel Landwerlin [Thu, 3 May 2018 16:57:01 +0000 (17:57 +0100)]
i965: perf: hsw: drop register programming not needed on HSW

This register is flagged as IVB only in the documentation.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoi965: perf: chv: fixup counters names
Lionel Landwerlin [Thu, 3 May 2018 16:56:30 +0000 (17:56 +0100)]
i965: perf: chv: fixup counters names

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoi965: perf: add PMA stall metrics
Lionel Landwerlin [Thu, 3 May 2018 16:51:42 +0000 (17:51 +0100)]
i965: perf: add PMA stall metrics

These are new metrics for Gen8/9 to measure the effect of the PMA
stall workaround fix.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoi965: perf: sklgt2: update memory write config
Lionel Landwerlin [Thu, 3 May 2018 17:54:20 +0000 (18:54 +0100)]
i965: perf: sklgt2: update memory write config

This rework the programming between older pre-production steppings &
new ones.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoi965: perf: sklgt2: update compute metrics config
Lionel Landwerlin [Thu, 3 May 2018 17:52:46 +0000 (18:52 +0100)]
i965: perf: sklgt2: update compute metrics config

This unifies some of the programming between pre-production stepping
and production ones.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agoi965: perf: sklgt2: update a priority for register programming
Lionel Landwerlin [Thu, 3 May 2018 17:51:23 +0000 (18:51 +0100)]
i965: perf: sklgt2: update a priority for register programming

This makes no difference in term of programming, it's just a cleanup.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agopanfrost: Implement FIXED formats
Alyssa Rosenzweig [Sun, 31 Mar 2019 04:34:22 +0000 (04:34 +0000)]
panfrost: Implement FIXED formats

Fixes crash in dEQP-GLES2.functional.draw.random.9

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost: Fix index calculation types and asserts
Alyssa Rosenzweig [Sun, 31 Mar 2019 04:27:29 +0000 (04:27 +0000)]
panfrost: Fix index calculation types and asserts

Fixes crash in
dEQP-GLES2.functional.draw.draw_elements.points.single_attribute.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost: Clean index state between indexed draws
Alyssa Rosenzweig [Sun, 31 Mar 2019 04:26:48 +0000 (04:26 +0000)]
panfrost: Clean index state between indexed draws

Fixes subsequent tests in
dEQP-GLES2.functional.draw.draw_elements.indices.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost/decode: Print negative_start
Alyssa Rosenzweig [Sun, 31 Mar 2019 04:15:46 +0000 (04:15 +0000)]
panfrost/decode: Print negative_start

This property slipped through..

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost: Implement missing texture formats
Alyssa Rosenzweig [Fri, 29 Mar 2019 01:46:17 +0000 (01:46 +0000)]
panfrost: Implement missing texture formats

 - Implements RGB565/RGBA5551 formats
 - Don't advertise support for flipped RGBA5551 and ETC

Fixes remaining tests in dEQP-GLES2.functional.texture.format.* which is
now at 36/36.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost: Extend tiling for cubemaps
Alyssa Rosenzweig [Thu, 28 Mar 2019 23:47:10 +0000 (23:47 +0000)]
panfrost: Extend tiling for cubemaps

transfer_unmap now tiles for any tiled resource, not just TEXTURE_2D,
which should more than just cubemaps!

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost: Implement command stream for linear cubemaps
Alyssa Rosenzweig [Thu, 28 Mar 2019 04:33:28 +0000 (04:33 +0000)]
panfrost: Implement command stream for linear cubemaps

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost/midgard: Emit cubemap coordinates
Alyssa Rosenzweig [Thu, 28 Mar 2019 04:27:13 +0000 (04:27 +0000)]
panfrost/midgard: Emit cubemap coordinates

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost: Include all cubemap faces in bitmap list
Alyssa Rosenzweig [Thu, 28 Mar 2019 02:12:03 +0000 (02:12 +0000)]
panfrost: Include all cubemap faces in bitmap list

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost/decode: Decode all cubemap faces
Alyssa Rosenzweig [Thu, 28 Mar 2019 01:59:02 +0000 (01:59 +0000)]
panfrost/decode: Decode all cubemap faces

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost: Preliminary work for cubemaps
Alyssa Rosenzweig [Wed, 27 Mar 2019 04:37:26 +0000 (04:37 +0000)]
panfrost: Preliminary work for cubemaps

Again, not yet functional, but this sets up the memory management for
cube maps.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost/midgard: Add L/S op for writing cubemap coordinates
Alyssa Rosenzweig [Wed, 27 Mar 2019 04:36:42 +0000 (04:36 +0000)]
panfrost/midgard: Add L/S op for writing cubemap coordinates

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost/midgard: Disassemble `cube` texture op
Alyssa Rosenzweig [Wed, 27 Mar 2019 04:36:10 +0000 (04:36 +0000)]
panfrost/midgard: Disassemble `cube` texture op

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agopanfrost: Fix vertex buffer corruption
Alyssa Rosenzweig [Wed, 27 Mar 2019 02:22:33 +0000 (02:22 +0000)]
panfrost: Fix vertex buffer corruption

Fixes crash in dEQP-GLES2.functional.buffer.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
5 years agoiris: fix set_sampler_view
Rob Clark [Thu, 14 Mar 2019 19:12:28 +0000 (15:12 -0400)]
iris: fix set_sampler_view

Update to match docs.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agogallium/docs: clarify set_sampler_views (v2)
Rob Clark [Thu, 14 Mar 2019 12:48:08 +0000 (08:48 -0400)]
gallium/docs: clarify set_sampler_views (v2)

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agofreedreno/ir3: convert to "new style" frag inputs
Rob Clark [Sat, 23 Mar 2019 15:38:37 +0000 (11:38 -0400)]
freedreno/ir3: convert to "new style" frag inputs

Add support for load_barycentric_pixel, load_interpolated_input, and
friends.  For now, this retains support for old-style inputs, which can
probably be dropped with some ttn work.

Prep work for sample-shading support.

Signed-off-by: Rob Clark <robdclark@gmail.com>
5 years agofreedreno/ir3: add pass to move varying loads
Rob Clark [Tue, 26 Mar 2019 15:28:34 +0000 (11:28 -0400)]
freedreno/ir3: add pass to move varying loads

Signed-off-by: Rob Clark <robdclark@gmail.com>