Lucas Stach [Wed, 27 Mar 2019 11:25:18 +0000 (12:25 +0100)]
etnaviv: only try to construct scanout resource when on KMS winsys
Trying to construct a scanout capable buffer will only ever work when
when we are on top of a KMS winsys, as the render node isn't capable
of allocating contiguous buffers.
Tested-by: Marius Vlad <marius.vlad@collabora.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Lucas Stach [Wed, 27 Mar 2019 11:22:58 +0000 (12:22 +0100)]
etnaviv: flush all pending contexts when accessing a resource with the CPU
When setting up a transfer to a resource, all contexts where the resource
is pending must be flushed. Otherwise a write transfer might be started
in the current context before all contexts that access the resource in
shared (read) mode have been executed.
Fixes: 64813541d575 (etnaviv: fix resource usage tracking across
different pipe_context's)
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-By: Guido Günther <agx@sigxcpu.org>
Lucas Stach [Wed, 27 Mar 2019 11:22:57 +0000 (12:22 +0100)]
etnaviv: don't flush own context when updating resource use
The context is self synchronizing at the GPU side, as commands are
executed in order. We must not flush our own context when updating the
resource use, as that leads to excessive flushing on effectively every
draw call, causing huge CPU overhead.
Fixes: 64813541d575 (etnaviv: fix resource usage tracking across
different pipe_context's)
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Christian Gmeiner [Wed, 27 Mar 2019 13:58:16 +0000 (14:58 +0100)]
etnaviv: shrink struct etna_3d_state
Drop struct members which are only written to but never read from.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Dave Airlie [Wed, 3 Apr 2019 02:20:40 +0000 (12:20 +1000)]
intel/compiler: use defined size for vector components
If we increase vector sizing later it would be nice to avoid
tripped over this again.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Dave Airlie [Wed, 3 Apr 2019 02:20:02 +0000 (12:20 +1000)]
nir: use proper array sizing define for vectors
If we increase the vector size in the future it would be good
to not have to fix these up, this should change nothing at present.
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Timothy Arceri [Wed, 3 Apr 2019 02:24:18 +0000 (13:24 +1100)]
Revert "nir: propagate known constant values into the if-then branch"
This reverts commit
4218b6422cf1ff70c7f0feeec699a35e88522ed7.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110311
Timothy Arceri [Fri, 23 Nov 2018 00:49:19 +0000 (11:49 +1100)]
nir: propagate known constant values into the if-then branch
Helps Max Waves / VGPR use in a bunch of Unigine Heaven
shaders.
shader-db results radeonsi (VEGA):
Totals from affected shaders:
SGPRS:
5505440 ->
5505872 (0.01 %)
VGPRS:
3077520 ->
3077296 (-0.01 %)
Spilled SGPRs: 39032 -> 39030 (-0.01 %)
Spilled VGPRs: 16326 -> 16326 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 744 -> 744 (0.00 %) dwords per thread
Code Size:
123755028 ->
123753316 (-0.00 %) bytes
Compile Time:
2751028 ->
2560786 (-6.92 %) milliseconds
LDS: 1415 -> 1415 (0.00 %) blocks
Max Waves: 972192 -> 972240 (0.00 %)
Wait states: 0 -> 0 (0.00 %)
vkpipeline-db results RADV (VEGA):
Totals from affected shaders:
SGPRS: 160 -> 160 (0.00 %)
VGPRS: 88 -> 88 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 18268 -> 18152 (-0.63 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 26 -> 26 (0.00 %)
Wait states: 0 -> 0 (0.00 %)
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Lepton Wu [Mon, 18 Mar 2019 23:40:25 +0000 (16:40 -0700)]
virgl: close drm fd when destroying virgl screen.
This fd was create in virgl_drm_screen_create and should be closed
in virgl_drm_screen_destroy.
Signed-off-by: Lepton Wu <lepton@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Rafael Antognolli [Tue, 26 Mar 2019 22:35:00 +0000 (15:35 -0700)]
iris: Enable fast clears on gen8.
Since we are now properly storing the clear color with SCS bits, we can
now enable fast clears on gen8 too.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Wed, 27 Mar 2019 21:42:12 +0000 (14:42 -0700)]
iris: Add aux.sampler_usages.
We want to skip some types of aux usages (for instance,
ISL_AUX_USAGE_HIZ when the hardware doesn't support it, or when we have
multisampling) when sampling from the surface.
Instead of checking for those cases while filling the surface state and
leaving it blank, let's have a version of aux.possible_usages for
sampling. This way we can also avoid allocating surface state for the
cases we don't use.
Fixes: a8b5ea8ef015ed4a "iris: Add function to update clear color in surface state."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Tue, 26 Mar 2019 23:28:10 +0000 (16:28 -0700)]
iris: Do not allocate clear_color_bo for gen8.
Since we are not using it for the clear color, there's no need to
allocate it.
Fixes: a8b5ea8ef015ed4a "iris: Add function to update clear color in surface state."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Wed, 27 Mar 2019 17:27:18 +0000 (10:27 -0700)]
iris: Manually apply fast clear color channel overrides.
At the fast clear time, the only swizzle we have available is actually
the identity swizzle (which we use for most rendering). So the call to
swizzle_color_value() becomes simply a no-op, and doesn't properly zero
out the unused channels.
We have to manually override those channels.
Fixes: a8b5ea8ef015ed4a "iris: Add function to update clear color in surface state."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Wed, 27 Mar 2019 20:09:34 +0000 (13:09 -0700)]
iris/gen8: Re-emit the SURFACE_STATE if the clear color changed.
The swizzle for rendering surfaces is always identity. So when we are
doing the fast clear, we don't have enough information to store the
clear color OR'ed with the Shader Channel Select bits for the dword in
the SURFACE_STATE.
Instead of trying to patch up the SURFACE_STATE correctly later, by
reading the color from the clear color state buffer and then doing all
the operations to store it, let's just re-emit the whole SURFACE_STATE.
That should make things way simpler on gen8, and we can still use the
clear color state buffer for gen9+.
Fixes: a8b5ea8ef015ed4a "iris: Add function to update clear color in surface state."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rafael Antognolli [Tue, 26 Mar 2019 18:08:22 +0000 (11:08 -0700)]
iris: Only update clear color for gens 8 and 9.
Newer gens can read it directly.
Also properly skip updating the ISL_AUX_USAGE_NONE surface.
Fixes: a8b5ea8ef015ed4a "iris: Add function to update clear color in surface state."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Alexander von Gluck IV [Sun, 31 Mar 2019 00:15:40 +0000 (00:15 +0000)]
haiku: Fix hgl dispatch build. Tested under meson/scons.
Reviewed-by: Brian Paul <brianp@vmware.com>
Guido Günther [Mon, 1 Apr 2019 15:58:24 +0000 (17:58 +0200)]
docs: Fix 19.0.x version numbers
The list has 19.0.2 twice.
Signed-off-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Marek Olšák [Tue, 2 Apr 2019 14:47:37 +0000 (10:47 -0400)]
docs/relnotes: document parallel_shader_compile changes in 19.1.0, not 19.0.0
Benjamin Tissoires [Tue, 2 Apr 2019 07:24:00 +0000 (09:24 +0200)]
CI: use wayland ci-templates repo to create the base image
There shouldn't be a difference for users, but this way we do manage
all of our containers from freedesktop.org
note: compared to the provious Dockerfile, we need to manually
add gcc, g++ and python*-wheel
Signed-off-by: Benjamin Tissoires <benjamin.tissoires@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Marek Olšák [Mon, 1 Apr 2019 16:29:43 +0000 (12:29 -0400)]
radeonsi: don't use PFP_SYNC_ME with compute-only contexts
Compute rings don't have PFP.
Fixes: a1378639ab1 "radeonsi: always use compute rings for clover on CI and newer (v2)"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Jan Vesely <jan.vesely@rutgers.edu>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Gert Wollny [Wed, 13 Mar 2019 17:50:52 +0000 (18:50 +0100)]
virgl: define MAX_VERTEX_STREAMS based on availability of TF3
Since with gles hosts we lie about the GLSL feature level it is better
to set the number of streams based on actual hosts capabilities.
v2: Make use of feature check level to avoid regressions.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-By: Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Gert Wollny [Tue, 19 Mar 2019 16:24:26 +0000 (17:24 +0100)]
softpipe: Implement ATOMFADD and enable cap TGSI_ATOMFADD
This enables the following piglits with PASS:
nv_shader_atomic_float/execution/
shared-atomicadd-float
shared-atomicexchange-float
ssbo-atomicadd-float
ssbo-atomicexchange-float
v2: Minimize the patch by using type punning (Eric Anholt)
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Erik Faye-Lund [Thu, 28 Mar 2019 18:03:47 +0000 (19:03 +0100)]
virgl: stricter usage of compressed 3d textures
Using RGTC, ETC1, ETC2 or S3TC for 3D-textures isn't alowed by any of
OpenGL 4.6, OpenGL ES 3.2, ARB_texture_compression_rgtc,
EXT_texture_compression_rgtc, OES_compressed_ETC1_RGB8_texture,
S3_s3tc or EXT_texture_compression_s3tc specifications.
So let's not allow any of those compressed 3d-textures at all. It's not
going to work once it hits the OpenGL driver in virglrenderer.
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Erik Faye-Lund [Fri, 29 Mar 2019 09:48:33 +0000 (10:48 +0100)]
virgl: do not allow compressed formats for buffers
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Eric Anholt [Fri, 29 Mar 2019 17:16:05 +0000 (10:16 -0700)]
dri3: Return the current swap interval from glXGetSwapIntervalMESA().
We were caching only the value set with glXSwapIntervalSGI(), missing out
on the default setting of the swap interval by the loader. This fixes
glxgears's warning about being vblank synchronized by default.
Fixes: 9777c4234b0e ("loader: drop the [gs]et_swap_interval callbacks")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Anuj Phogat [Fri, 29 Mar 2019 20:13:01 +0000 (13:13 -0700)]
intel: Add support for Comet Lake
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Chris Wilson [Mon, 1 Apr 2019 10:39:46 +0000 (11:39 +0100)]
iris: Adapt to variable ppGTT size
Not all hardware is made equal and some does not have the full
complement of 48b of address space. Ask what the actual size of virtual
address space allocated for contexts, and bail if that is not enough to
satisfy our static partitioning needs.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Samuel Pitoiset [Mon, 1 Apr 2019 14:18:11 +0000 (16:18 +0200)]
radv: partially enable VK_KHR_shader_float16_int8
Only 8-bit integers for now, float16 requires a bit more work.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Mon, 1 Apr 2019 14:18:10 +0000 (16:18 +0200)]
ac: add 8-bit and 64-bit support to ac_build_bitfield_reverse()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Mon, 1 Apr 2019 14:18:09 +0000 (16:18 +0200)]
ac: add 8-bit support to ac_build_umsb()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Mon, 1 Apr 2019 14:18:08 +0000 (16:18 +0200)]
ac: add 8-bit support to ac_find_lsb()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Mon, 1 Apr 2019 14:18:07 +0000 (16:18 +0200)]
ac: add 8-bit support to ac_build_bit_count()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Mon, 1 Apr 2019 14:18:06 +0000 (16:18 +0200)]
ac/nir: add support for nir_op_b2i8
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Marek Olšák [Mon, 6 Aug 2018 11:11:33 +0000 (07:11 -0400)]
radeonsi: implement ARB/KHR_parallel_shader_compile callbacks
Marek Olšák [Tue, 7 Aug 2018 00:40:05 +0000 (20:40 -0400)]
util/queue: add util_queue_adjust_num_threads
for ARB_parallel_shader_compile
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Marek Olšák [Tue, 7 Aug 2018 00:34:24 +0000 (20:34 -0400)]
util/queue: hold a lock when reading num_threads in util_queue_finish
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Marek Olšák [Tue, 7 Aug 2018 00:32:31 +0000 (20:32 -0400)]
util/queue: add ability to kill a subset of threads
for ARB_parallel_shader_compile
Marek Olšák [Tue, 7 Aug 2018 00:15:43 +0000 (20:15 -0400)]
util/queue: move thread creation into a separate function
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Marek Olšák [Mon, 6 Aug 2018 11:09:28 +0000 (07:09 -0400)]
gallium: implement ARB/KHR_parallel_shader_compile
Marek Olšák [Mon, 6 Aug 2018 11:05:19 +0000 (07:05 -0400)]
mesa: implement ARB/KHR_parallel_shader_compile
Tested by piglit.
Marek Olšák [Wed, 27 Feb 2019 23:31:54 +0000 (18:31 -0500)]
radeonsi: fix assertion failure by using the correct type
src/gallium/drivers/radeonsi/si_state_viewport.c:196: si_emit_guardband:
Assertion `vp_as_scissor.maxx <= max_viewport_size[vp_as_scissor.quant_mode]
&& vp_as_scissor.maxy <= max_viewport_size[vp_as_scissor.quant_mode]' failed.
The comparison was unsigned, so negative maxx or maxy would fail.
Fixes: 3c540e0a7488 "radeonsi: Fix guardband computation for large render targets"
Leo Liu [Wed, 27 Mar 2019 12:37:28 +0000 (08:37 -0400)]
radeon/vcn/vp9: search the render target from the whole list
The number of render targets could be more than max of references,
so we search the full list of the render pictures for the current
render target index
https://bugs.freedesktop.org/show_bug.cgi?id=109648
Signed-off-by: Leo Liu <leo.liu@amd.com>
Tested-by: James Zhu <James.Zhu@amd.com>
Acked-by: James Zhu<James.Zhu@amd.com>
Cc: <mesa-stable@lists.freedesktop.org>
Rhys Perry [Thu, 6 Dec 2018 14:01:15 +0000 (14:01 +0000)]
radv: lower 16-bit flrp
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Samuel Pitoiset [Tue, 26 Mar 2019 10:34:46 +0000 (11:34 +0100)]
ac: fix ac_build_umsb() for 16-bit integer type
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 26 Mar 2019 10:34:45 +0000 (11:34 +0100)]
ac: fix ac_find_lsb() for 16-bit integer type
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 26 Mar 2019 10:34:44 +0000 (11:34 +0100)]
ac: fix ac_build_bitfield_reverse() for 16-bit integer type
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 26 Mar 2019 10:34:43 +0000 (11:34 +0100)]
ac: fix ac_build_bit_count() for 16-bit integer type
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Tue, 26 Mar 2019 10:34:42 +0000 (11:34 +0100)]
ac/nir: fix nir_op_b2i16
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Eric Engestrom [Tue, 26 Mar 2019 11:21:09 +0000 (11:21 +0000)]
meson: strip rpath from megadrivers
More specifically, use the library file that has been post-processed by Meson
when creating the hardlinks.
Bugs: https://bugs.freedesktop.org/show_bug.cgi?id=108766
Fixes: 3218056e0eb375eeda47 "meson: Build i965 and dri stack"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Tapani Pälli [Thu, 28 Mar 2019 09:35:27 +0000 (11:35 +0200)]
spirv: fix a compiler warning
Fixes implicit conversion from enumeration type 'SpvOp' warning.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Lionel Landwerlin [Sun, 31 Mar 2019 09:41:17 +0000 (10:41 +0100)]
i965: perf: update render basic configs for big core gen9/gen10
This updates allows an MI_LRI to trigger a OA report write in the
global OA buffer. This isn't really useful for us, we just keep close
to the internal public configs.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Sun, 31 Mar 2019 09:38:19 +0000 (10:38 +0100)]
i965: perf: add ring busyness metric for cfl gt2
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Fri, 4 May 2018 11:28:57 +0000 (12:28 +0100)]
i965: perf: enable Icelake metrics
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Fri, 4 May 2018 11:28:34 +0000 (12:28 +0100)]
i965: perf: add Icelake metrics
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Fri, 4 May 2018 10:32:07 +0000 (11:32 +0100)]
i965: perf: sklgt2: drop programming of an unused NOA register
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Thu, 3 May 2018 16:57:01 +0000 (17:57 +0100)]
i965: perf: hsw: drop register programming not needed on HSW
This register is flagged as IVB only in the documentation.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Thu, 3 May 2018 16:56:30 +0000 (17:56 +0100)]
i965: perf: chv: fixup counters names
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Thu, 3 May 2018 16:51:42 +0000 (17:51 +0100)]
i965: perf: add PMA stall metrics
These are new metrics for Gen8/9 to measure the effect of the PMA
stall workaround fix.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Thu, 3 May 2018 17:54:20 +0000 (18:54 +0100)]
i965: perf: sklgt2: update memory write config
This rework the programming between older pre-production steppings &
new ones.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Thu, 3 May 2018 17:52:46 +0000 (18:52 +0100)]
i965: perf: sklgt2: update compute metrics config
This unifies some of the programming between pre-production stepping
and production ones.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Thu, 3 May 2018 17:51:23 +0000 (18:51 +0100)]
i965: perf: sklgt2: update a priority for register programming
This makes no difference in term of programming, it's just a cleanup.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Alyssa Rosenzweig [Sun, 31 Mar 2019 04:34:22 +0000 (04:34 +0000)]
panfrost: Implement FIXED formats
Fixes crash in dEQP-GLES2.functional.draw.random.9
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Sun, 31 Mar 2019 04:27:29 +0000 (04:27 +0000)]
panfrost: Fix index calculation types and asserts
Fixes crash in
dEQP-GLES2.functional.draw.draw_elements.points.single_attribute.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Sun, 31 Mar 2019 04:26:48 +0000 (04:26 +0000)]
panfrost: Clean index state between indexed draws
Fixes subsequent tests in
dEQP-GLES2.functional.draw.draw_elements.indices.*
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Sun, 31 Mar 2019 04:15:46 +0000 (04:15 +0000)]
panfrost/decode: Print negative_start
This property slipped through..
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Fri, 29 Mar 2019 01:46:17 +0000 (01:46 +0000)]
panfrost: Implement missing texture formats
- Implements RGB565/RGBA5551 formats
- Don't advertise support for flipped RGBA5551 and ETC
Fixes remaining tests in dEQP-GLES2.functional.texture.format.* which is
now at 36/36.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Thu, 28 Mar 2019 23:47:10 +0000 (23:47 +0000)]
panfrost: Extend tiling for cubemaps
transfer_unmap now tiles for any tiled resource, not just TEXTURE_2D,
which should more than just cubemaps!
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Thu, 28 Mar 2019 04:33:28 +0000 (04:33 +0000)]
panfrost: Implement command stream for linear cubemaps
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Thu, 28 Mar 2019 04:27:13 +0000 (04:27 +0000)]
panfrost/midgard: Emit cubemap coordinates
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Thu, 28 Mar 2019 02:12:03 +0000 (02:12 +0000)]
panfrost: Include all cubemap faces in bitmap list
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Thu, 28 Mar 2019 01:59:02 +0000 (01:59 +0000)]
panfrost/decode: Decode all cubemap faces
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Wed, 27 Mar 2019 04:37:26 +0000 (04:37 +0000)]
panfrost: Preliminary work for cubemaps
Again, not yet functional, but this sets up the memory management for
cube maps.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Wed, 27 Mar 2019 04:36:42 +0000 (04:36 +0000)]
panfrost/midgard: Add L/S op for writing cubemap coordinates
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Wed, 27 Mar 2019 04:36:10 +0000 (04:36 +0000)]
panfrost/midgard: Disassemble `cube` texture op
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Alyssa Rosenzweig [Wed, 27 Mar 2019 02:22:33 +0000 (02:22 +0000)]
panfrost: Fix vertex buffer corruption
Fixes crash in dEQP-GLES2.functional.buffer.*
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Rob Clark [Thu, 14 Mar 2019 19:12:28 +0000 (15:12 -0400)]
iris: fix set_sampler_view
Update to match docs.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rob Clark [Thu, 14 Mar 2019 12:48:08 +0000 (08:48 -0400)]
gallium/docs: clarify set_sampler_views (v2)
Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Rob Clark [Sat, 23 Mar 2019 15:38:37 +0000 (11:38 -0400)]
freedreno/ir3: convert to "new style" frag inputs
Add support for load_barycentric_pixel, load_interpolated_input, and
friends. For now, this retains support for old-style inputs, which can
probably be dropped with some ttn work.
Prep work for sample-shading support.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Tue, 26 Mar 2019 15:28:34 +0000 (11:28 -0400)]
freedreno/ir3: add pass to move varying loads
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sun, 24 Mar 2019 15:58:21 +0000 (11:58 -0400)]
freedreno/ir3: rework varying packing
Originally we kept track of a table of inputs. But with new-style frag
inputs this becomes awkward. Re-work it so that initially we assigned
un-packed varying locations, and then after the shader is compiled scan
to find actual used inputs, and re-pack.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Sat, 23 Mar 2019 15:37:49 +0000 (11:37 -0400)]
freedreno/ir3: re-indent comment
Make it more clear that it applies to the following 'case' statements,
rather than the previous one.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Thu, 28 Mar 2019 14:57:31 +0000 (10:57 -0400)]
nir: add lower_all_io_to_elements
I need this part of lower_all_io_to_temps but without the actual
lowering to temps part.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 27 Mar 2019 15:29:56 +0000 (11:29 -0400)]
nir: print var name for load_interpolated_input too
Signed-off-by: Rob Clark <robdclark@gmail.com>
Acked-by: Karol Herbst <kherbst@redhat.com>
Sergii Romantsov [Thu, 28 Feb 2019 11:35:54 +0000 (13:35 +0200)]
i965,iris/blorp: do not blit 0-sizes
Seems there is no sense in blitting 0-sized sources
or destinations.
Additionaly it may cause segfaults for i965.
v2: Function call replaced with inline check
v3: Added check to avoid devision by zero (L. Landwerlin)
v4: Added simillar check for Iris (L. Landwerlin)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110239
Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Vinson Lee [Sat, 30 Mar 2019 06:24:05 +0000 (23:24 -0700)]
gallium: Fix autotools build with libxatracker.la.
CXXLD libxatracker.la
/usr/bin/ld: ../../../../src/gallium/auxiliary/.libs/libgallium.a(tgsi_to_nir.o): in function `ttn_finalize_nir':
src/gallium/auxiliary/nir/tgsi_to_nir.c:2111: undefined reference to `gl_nir_lower_samplers_as_deref'
/usr/bin/ld: src/gallium/auxiliary/nir/tgsi_to_nir.c:2113: undefined reference to `gl_nir_lower_samplers'
Fixes: 9a834447d652 ("tgsi_to_nir: Produce optimized NIR for a given pipe_screen.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109929
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Timur Kristóf [Thu, 14 Mar 2019 14:32:37 +0000 (15:32 +0100)]
gallium: fix autotools build of pipe_msm.la
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Fixes: 9a834447d652 ("tgsi_to_nir: Produce optimized NIR for a given pipe_screen.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109929
Jason Ekstrand [Wed, 27 Mar 2019 15:13:28 +0000 (10:13 -0500)]
nir: Lock around validation fail shader dumping
This prevents getting mixed-up results if a multi-threaded app has two
validation errors in different threads.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Brian Paul [Fri, 29 Mar 2019 16:45:44 +0000 (10:45 -0600)]
util: no-op __builtin_types_compatible_p() for non-GCC compilers
__builtin_types_compatible_p() is GCC-specific and breaks the
MSVC build.
This intrinsic has been in u_vector_foreach() for a long time, but
that macro has only recently been used in code
(nir/nir_opt_comparison_pre.c) that's built with MSVC.
Fixes: 2cf59861a ("nir: Add partial redundancy elimination for compares")
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Caio Marcelo de Oliveira Filho [Fri, 29 Mar 2019 18:55:08 +0000 (11:55 -0700)]
iris: Clean up compiler warnings about unused
Removed a few unused variables and iris_getparam_boolean().
Kept 'name' around since there's a commented debug that make use of it.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Engestrom [Thu, 15 Nov 2018 18:07:33 +0000 (18:07 +0000)]
egl: hide entrypoints that shouldn't be exported when using glvnd
From GLVND author:
> From a functional standpoint, exporting additional symbols doesn't
> really matter, since libglvnd will load the vendor libraries with
> RTLD_LOCAL.
Suggested-by: Kyle Brenneman <kbrenneman@nvidia.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Kyle Brenneman <kbrenneman@nvidia.com>
Karol Herbst [Sun, 24 Mar 2019 04:36:36 +0000 (05:36 +0100)]
nir/validate: validate that tex deref sources are actually derefs
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Karol Herbst [Thu, 28 Mar 2019 22:50:54 +0000 (23:50 +0100)]
nir/print: fix printing the image_array intrinsic index
Fixes: 0de003be0363 ("nir: Add handle/index-based image intrinsics")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Timothy Arceri [Thu, 28 Mar 2019 00:43:06 +0000 (11:43 +1100)]
Revert "ac/nir: use new LLVM 8 intrinsics for SSBO atomic operations"
This reverts commit
29132af2347ede46a6d02422295a5fadbe5fe788.
It seems the new intrinsic causes a hang on radeonsi (VEGA) when running the
piglit test:
tests/spec/arb_shader_storage_buffer_object/execution/ssbo-atomicCompSwap-int.shader_test
Samuel Pitoiset [Fri, 29 Mar 2019 07:39:43 +0000 (08:39 +0100)]
ac: fix return type for llvm.amdgcn.frexp.exp.i32.64
This fixes the following piglit with RadeonSI
tests/spec/arb_gpu_shader_fp64/execution/built-in-functions/fs-frexp-dvec4.shader_test
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Gert Wollny [Wed, 27 Mar 2019 08:07:36 +0000 (09:07 +0100)]
virgl: Add a caps feature check version
When we add new feature checks on the host side that is used to
enable a cap conditionally that was enabled unconditionally before
we might end up with a feature regression when a new mesa version
is used with an old virglrenderer version that doesn't check for
that cap.
To work around this problem add a version id to the caps that corresponds
to the features that are actually checked on the host and check that
version too when enabling the cap.
Fixes: 2ee197d6e84aa37638d423363aca183952816067
virgl: Enable mixed color FBO attachemnets only when the host supports it
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Pohsien Wang <pwang@chromium.org>
Samuel Pitoiset [Thu, 28 Mar 2019 15:03:03 +0000 (16:03 +0100)]
radv: do not always initialize HTILE in compressed state
Especially when performing a transtion from UNDEFINED->GENERAL,
the driver shouldn't initialize HTILE metadata in compressed
state because it doesn't decompress when the src layout is
GENERAL.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110259
Fixes: 3a2e93147f7 ("radv: always initialize HTILE when the src layout is UNDEFINED")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Kenneth Graunke [Sat, 23 Mar 2019 16:32:38 +0000 (09:32 -0700)]
iris: Print the memzone name when allocating BOs with INTEL_DEBUG=buf
This gives me an idea of what kinds of buffers are being allocated on
the fly which could help inform our cache decisions.
Brian Paul [Fri, 29 Mar 2019 02:33:32 +0000 (20:33 -0600)]
nir: use {0} initializer instead of {} to fix MSVC build
Trivial change.
Fixes: c6ee46a75 ("nir: Add nir_alu_srcs_negative_equal")
Ian Romanick [Wed, 23 May 2018 01:56:41 +0000 (18:56 -0700)]
intel/compiler: Use partial redundancy elimination for compares
Almost all of the hurt shaders are repeated instances of the same shader
in synmark's compilation speed tests.
shader-db results:
All Gen6+ platforms had similar results. (Skylake shown)
total instructions in shared programs:
15256840 ->
15256389 (<.01%)
instructions in affected programs: 54137 -> 53686 (-0.83%)
helped: 288
HURT: 0
helped stats (abs) min: 1 max: 15 x̄: 1.57 x̃: 1
helped stats (rel) min: 0.06% max: 26.67% x̄: 1.99% x̃: 0.74%
95% mean confidence interval for instructions value: -1.76 -1.38
95% mean confidence interval for instructions %-change: -2.47% -1.50%
Instructions are helped.
total cycles in shared programs:
372286583 ->
372283851 (<.01%)
cycles in affected programs: 833829 -> 831097 (-0.33%)
helped: 265
HURT: 16
helped stats (abs) min: 2 max: 74 x̄: 11.81 x̃: 4
helped stats (rel) min: 0.04% max: 9.07% x̄: 0.99% x̃: 0.35%
HURT stats (abs) min: 2 max: 130 x̄: 24.88 x̃: 8
HURT stats (rel) min: <.01% max: 12.31% x̄: 1.44% x̃: 0.27%
95% mean confidence interval for cycles value: -12.30 -7.15
95% mean confidence interval for cycles %-change: -1.06% -0.64%
Cycles are helped.
Iron Lake and GM45 had similar results. (GM45 shown)
total instructions in shared programs:
5038653 ->
5038495 (<.01%)
instructions in affected programs: 13939 -> 13781 (-1.13%)
helped: 50
HURT: 1
helped stats (abs) min: 1 max: 15 x̄: 3.18 x̃: 4
helped stats (rel) min: 0.33% max: 13.33% x̄: 2.24% x̃: 1.09%
HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel) min: 0.83% max: 0.83% x̄: 0.83% x̃: 0.83%
95% mean confidence interval for instructions value: -3.73 -2.47
95% mean confidence interval for instructions %-change: -3.16% -1.21%
Instructions are helped.
total cycles in shared programs:
128118922 ->
128118228 (<.01%)
cycles in affected programs: 134906 -> 134212 (-0.51%)
helped: 50
HURT: 0
helped stats (abs) min: 2 max: 60 x̄: 13.88 x̃: 18
helped stats (rel) min: 0.06% max: 3.19% x̄: 0.74% x̃: 0.70%
95% mean confidence interval for cycles value: -16.54 -11.22
95% mean confidence interval for cycles %-change: -0.95% -0.53%
Cycles are helped.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Wed, 23 May 2018 01:19:16 +0000 (18:19 -0700)]
nir: Add partial redundancy elimination for compares
This pass attempts to dectect code sequences like
if (x < y) {
z = y - x;
...
}
and replace them with sequences like
t = x - y;
if (t < 0) {
z = -t;
...
}
On architectures where the subtract can generate the flags used by the
if-statement, this saves an instruction. It's also possible that moving
an instruction out of the if-statement will allow
nir_opt_peephole_select to convert the whole thing to a bcsel.
Currently only floating point compares and adds are supported. Adding
support for integer will be a challenge due to integer overflow. There
are a couple possible solutions, but they may not apply to all
architectures.
v2: Fix a typo in the commit message and a couple typos in comments.
Fix possible NULL pointer deref from result of push_block(). Add
missing (-A + B) case. Suggested by Caio.
v3: Fix is_not_const_zero to work correctly with types other than
nir_type_float32. Suggested by Ken.
v4: Add some comments explaining how this works. Suggested by Ken.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>