Tim Rowley [Fri, 18 Mar 2016 17:48:47 +0000 (11:48 -0600)]
swr: [rasterizer core] Add clipping against user clip distances in the NullPS backend.
Tim Rowley [Fri, 18 Mar 2016 00:10:25 +0000 (18:10 -0600)]
swr: [rasterizer core] Arena optimizations - preparing for global allocator.
Tim Rowley [Thu, 17 Mar 2016 22:50:46 +0000 (16:50 -0600)]
swr: [rasterizer core] Reset DrawContext arena at end of draw rather than upon reclaim of DC
Keeps overall memory consumption lower.
Also, remove unused knobs.
Tim Rowley [Thu, 17 Mar 2016 22:12:17 +0000 (16:12 -0600)]
swr: [rasterizer core] Add clipping of user clip planes in clipper.
Tim Rowley [Thu, 17 Mar 2016 21:39:13 +0000 (15:39 -0600)]
swr: [rasterizer] Reduce max in-flight draws to 96 (by default)
Tim Rowley [Thu, 17 Mar 2016 18:22:43 +0000 (12:22 -0600)]
swr: [rasterizer] Fix run-time check asserts
One innocuous (uninitialized variable), and one not so innocuous
(stack corruption).
Tim Rowley [Wed, 16 Mar 2016 23:54:04 +0000 (17:54 -0600)]
swr: [rasterizer jitter] signed immediate builder
Tim Rowley [Wed, 16 Mar 2016 17:56:50 +0000 (11:56 -0600)]
swr: [rasterizer common] changes for cygwin
Tim Rowley [Mon, 14 Mar 2016 21:54:29 +0000 (15:54 -0600)]
swr: [rasterizer] code styling and update copyrights
Tim Rowley [Fri, 11 Mar 2016 01:20:07 +0000 (19:20 -0600)]
swr: [rasterizer core] Guard against enquing work to invalid hot tiles
Tim Rowley [Fri, 11 Mar 2016 01:19:30 +0000 (19:19 -0600)]
swr: [rasterizer] Stop setting viewport size to larger than hottile array
Guard against enquing work to invalid tiles
Tim Rowley [Fri, 11 Mar 2016 00:30:40 +0000 (18:30 -0600)]
swr: [rasterizer] Discard work + misc fixes
Tim Rowley [Thu, 10 Mar 2016 21:15:40 +0000 (15:15 -0600)]
swr: [rasterizer] remove use of BYTE type
Tim Rowley [Wed, 9 Mar 2016 23:18:55 +0000 (17:18 -0600)]
swr: [rasterizer core] Fix crash that can occur when switching contexts
Tim Rowley [Wed, 9 Mar 2016 22:33:33 +0000 (16:33 -0600)]
swr: [rasterizer] remove unused knob
Tim Rowley [Wed, 9 Mar 2016 22:15:37 +0000 (16:15 -0600)]
swr: [rasterizer core] subcontext rework
Tim Rowley [Wed, 9 Mar 2016 00:58:54 +0000 (18:58 -0600)]
swr: [rasterizer common] add _simd_s[rl]lv_epi32
Tim Rowley [Tue, 8 Mar 2016 17:56:06 +0000 (11:56 -0600)]
swr: [rasterizer core] Alleviate potential stack overflow for 32bit builds
Move large stack allocations in the GS and clipper into thread local storage.
Tim Rowley [Mon, 7 Mar 2016 20:45:17 +0000 (14:45 -0600)]
swr: [rasterizer] remove use of UCHAR and UINT64 types
Tim Rowley [Mon, 7 Mar 2016 16:51:56 +0000 (10:51 -0600)]
swr: [rasterizer] remove use of FLOAT type
Tim Rowley [Mon, 7 Mar 2016 07:14:13 +0000 (01:14 -0600)]
swr: [rasterizer] Fix Coverity issues reported by Mesa developers.
Tim Rowley [Sat, 5 Mar 2016 06:53:04 +0000 (00:53 -0600)]
swr: [rasterizer] add debug/perf category to knobs
Tim Rowley [Thu, 24 Mar 2016 16:07:32 +0000 (11:07 -0500)]
swr: [rasterizer core] don't assume linux is 64-bit
Tim Rowley [Thu, 24 Mar 2016 16:07:15 +0000 (11:07 -0500)]
swr: [rasterizer common] remove old unused win32 types
Tim Rowley [Fri, 4 Mar 2016 00:19:45 +0000 (18:19 -0600)]
swr: [rasterizer jitter] vpermps support
Tim Rowley [Mon, 29 Feb 2016 18:01:48 +0000 (12:01 -0600)]
swr: [rasterizer] Add rdtsc buckets support for shaders
Pass pointer to core buckets mgr back to sim layer.
Add support for RDTSC_START/RDTSC_STOP macros in the builder.
Each unique shader now has a unique bucket associated with it,
enabling more detailed reporting at the shader level. Currently
due to some llvm issue with thread local storage, 64bit runs require
single threaded mode.
Tim Rowley [Wed, 24 Feb 2016 19:34:50 +0000 (13:34 -0600)]
swr: [rasterizer core] backend reorganization
Tim Rowley [Thu, 25 Feb 2016 01:03:33 +0000 (19:03 -0600)]
swr: [rasterizer core] store blend output in temporary instead of PS output.
Fixes additive blend problem with MSAA
Tim Rowley [Tue, 23 Feb 2016 23:29:59 +0000 (17:29 -0600)]
swr: [rasterizer core] Move InitializeHotTiles and corresponding clear code out of threads.cpp.
Tim Rowley [Tue, 23 Feb 2016 19:47:24 +0000 (13:47 -0600)]
swr: [rasterizer jitter] Cleanup use of types inside of Builder.
Also, cached the simd width since we don't have to keep querying
the JitManager for it.
Tim Rowley [Mon, 22 Feb 2016 17:00:07 +0000 (11:00 -0600)]
swr: [rasterizer jitter] Fix type mismatch on select args for SCATTERPS
Tim Rowley [Sat, 20 Feb 2016 01:05:14 +0000 (19:05 -0600)]
swr: [rasterizer core] fix rasterizing multisampling with scissor enabled
We were not evaluating the scissor edge equations at sample positions.
Tim Rowley [Fri, 19 Feb 2016 23:55:23 +0000 (17:55 -0600)]
swr: [rasterizer core] RingBuffer class for DC/DS
Use head/tail ring buffer indices for thread synchronization.
1. SwrWaitForIdle loops until ring is empty. (head == tail)
2. GetDrawContext waits until ring is not full. (head - tail) == Ring Size
3. Draw enqueues by incrementing head.
4. Last worker thread to move past a DC dequeues by incrementing tail.
Todo: To reduce contention we can cache the tail in the API thread. For
example, if you know you have 64 free entries in the ring then you don't
need to keep checking the tail until you used those 64 entries.
Tim Rowley [Fri, 19 Feb 2016 01:00:30 +0000 (19:00 -0600)]
swr: [rasterizer] switch assert uses to SWR_ASSERT
Tim Rowley [Wed, 17 Feb 2016 23:55:59 +0000 (17:55 -0600)]
swr: [rasterizer core] Split all RECT_LIST draws into 1 RECT per draw
Needed until proper RECT_LIST PrimAssembly code is written.
Tim Rowley [Tue, 16 Feb 2016 23:32:34 +0000 (17:32 -0600)]
swr: [rasterizer] Add string knob type
Sonny Jiang [Wed, 4 Nov 2015 16:01:33 +0000 (11:01 -0500)]
radeonsi: add Polaris PCI IDs
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (Polaris10)
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> (Polaris11)
Sonny Jiang [Tue, 15 Dec 2015 20:33:40 +0000 (15:33 -0500)]
radeon/vce: disable two pipe mode for Polaris11
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Sonny Jiang [Tue, 15 Dec 2015 20:16:29 +0000 (15:16 -0500)]
radeon/vce: add Polaris11 VCE firmware support
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Sonny Jiang [Wed, 4 Nov 2015 21:13:07 +0000 (16:13 -0500)]
radeonsi: add support for Polaris (v2)
v2: Polaris chips should be defined after Stoney
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> (v1)
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> (v1)
Signed-off-by: Leo Liu <leo.liu@amd.com> (v2 diff)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v2 diff)
Sonny Jiang [Tue, 3 Nov 2015 16:46:38 +0000 (11:46 -0500)]
winsys/amdgpu: addrlib - add Polaris support (v2)
v2: fix indentation as noted by Michel
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Kenneth Graunke [Thu, 24 Mar 2016 05:35:41 +0000 (22:35 -0700)]
mesa: Check glReadBuffer enums against the ES3 table.
From the ES 3.2 spec, section 16.1.1 (Selecting Buffers for Reading):
"An INVALID_ENUM error is generated if src is not BACK or one of
the values from table 15.5."
Table 15.5 contains NONE and COLOR_ATTACHMENTi.
Mesa properly returned INVALID_ENUM for unknown enums, but it decided
what was known by using read_buffer_enum_to_index, which handles all
enums in every API. So enums that were valid in GL were making it
past the "valid enum" check. Such targets would then be classified
as unsupported, and we'd raise INVALID_OPERATION, but that's technically
the wrong error code.
Fixes dEQP-GLES31's
functional.debug.negative_coverage.get_error.buffer.read_buffer
v2: Only call read_buffer_enuM_to_index when required (Eduardo).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Jason Ekstrand [Sun, 14 Feb 2016 01:31:05 +0000 (17:31 -0800)]
nir: Add a pass to inline functions
This commit adds a new NIR pass that lowers all function calls away by
inlining the functions.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Sat, 26 Dec 2015 18:48:14 +0000 (10:48 -0800)]
nir/builder: Add helpers for easily inserting copy_var intrinsics
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Sun, 14 Feb 2016 01:08:57 +0000 (17:08 -0800)]
nir: Add return lowering pass
This commit adds a NIR pass for lowering away returns in functions. If the
return is in a loop, it is lowered to a break. If it is not in a loop,
it's lowered away by moving/deleting code as needed.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Mon, 28 Dec 2015 06:50:14 +0000 (22:50 -0800)]
nir: Add a cursor helper for getting a cursor after any phi nodes
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Sun, 14 Feb 2016 01:14:27 +0000 (17:14 -0800)]
nir/builder: Add a helper for inserting jump instructions
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Thu, 24 Dec 2015 02:10:08 +0000 (18:10 -0800)]
nir/cf: Make extracting or re-inserting nothing a no-op
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Jason Ekstrand [Sat, 26 Dec 2015 18:32:10 +0000 (10:32 -0800)]
nir: Add a function for comparing cursors
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Fri, 18 Dec 2015 19:27:00 +0000 (11:27 -0800)]
nir/cf: Handle relinking top-level blocks
This can happen if a function ends in a return instruction and you remove
the return.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Jason Ekstrand [Sat, 13 Feb 2016 05:52:46 +0000 (21:52 -0800)]
nir: Add a pass to repair SSA form
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Sat, 13 Feb 2016 05:48:26 +0000 (21:48 -0800)]
nir/vars_to_ssa: Use the new nir_phi_builder helper
The efficiency should be approximately the same. We do a little more work
per phi node because we have to sort the predecessors. However, we no
longer have to walk the blocks a second time to pop things off the stack.
The bigger advantage, however, is that we can now re-use the phi placement
and per-block SSA value tracking in other passes.
As a side-benifit, the phi builder actually handles unreachable blocks
correctly. The original vars_to_ssa code, because of the way it iterated
the blocks and added phi sources, didn't add sources corresponding to
predecessors of unreachable blocks. The new strategy employed by the phi
builder creates a phi source for each predecessor and should correctly
handle unreachable blocks by setting those sources to SSA undefs.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Tue, 29 Dec 2015 23:25:43 +0000 (15:25 -0800)]
nir/dominance: Handle unreachable blocks
Previously, nir_dominance.c didn't properly handle unreachable blocks.
This can happen if, for instance, you have something like this:
loop {
if (...) {
break;
} else {
break;
}
}
In this case, the block right after the if statement will be unreachable.
This commit makes two changes to handle this. First, it removes an assert
and allows block->imm_dom to be null if the block is unreachable. Second,
it properly skips unreachable blocks in calc_dom_frontier_cb.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Jason Ekstrand [Sat, 13 Feb 2016 05:41:42 +0000 (21:41 -0800)]
nir: Add a phi node placement helper
Right now, we have phi placement code in two places and there are other
places where it would be nice to be able to do this analysis. Instead of
repeating it all over the place, this commit adds a helper for placing all
of the needed phi nodes for a value.
v2: Add better documentation
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Sun, 17 Jan 2016 00:42:06 +0000 (16:42 -0800)]
util/bitset: Allow iterating over const bitsets
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Rob Clark [Thu, 24 Mar 2016 19:44:35 +0000 (15:44 -0400)]
ttn: remove stray global from header
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Samuel Pitoiset [Wed, 23 Mar 2016 22:29:20 +0000 (23:29 +0100)]
nv50/ir: silence unhandled TGSI_PROPERTY_NEXT_SHADER info
radeonsi uses this property to make the best decision about which
shader to compile, but this is not currently used by our codegen.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Kenneth Graunke [Thu, 24 Mar 2016 06:46:12 +0000 (23:46 -0700)]
mesa: Handle negative length in glPushDebugGroup().
The KHR_debug spec doesn't actually say we should handle this, but that
is most likely an oversight - it says to check against strlen and
generate errors if length is negative. It appears they just forgot to
explicitly spell out that we should then proceed to actually handle it.
Fixes crashes from uncaught std::string exceptions in many
dEQP-GLES31.functional.debug.error_filters.* tests.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Kenneth Graunke [Thu, 24 Mar 2016 06:35:40 +0000 (23:35 -0700)]
mesa: Make glDebugMessageInsert deal with negative length for all types.
From the KHR_debug spec, section 5.5.5 (Externally Generated Messages):
"If <length> is negative, it is implied that <buf> contains a null
terminated string. The error INVALID_VALUE will be generated if the
number of characters in <buf>, excluding the null terminator when
<length> is negative, is not less than the value of
MAX_DEBUG_MESSAGE_LENGTH."
This indicates that length should be set to strlen for all types, not
just GL_DEBUG_TYPE_MARKER. We want it to be after validate_length()
so we still generate appropriate errors.
Fixes crashes from uncaught std::string exceptions in many
dEQP-GLES31.functional.debug.error_filters.* tests.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Kenneth Graunke [Thu, 24 Mar 2016 04:38:42 +0000 (21:38 -0700)]
mesa: Include null terminator in GL_DEBUG_NEXT_LOGGED_MESSAGE_LENGTH.
From the KHR_debug spec:
"Applications can query the number of messages currently in the log by
obtaining the value of DEBUG_LOGGED_MESSAGES, and the string length
(including its null terminator) of the oldest message in the log
through the value of DEBUG_NEXT_LOGGED_MESSAGE_LENGTH."
Because we weren't including the null terminator, many dEQP tests
called glGetDebugMessageLog with a bufSize parameter that was 1 too
small, and unable to contain the message, so we skipped returning it,
failing many cases.
Fixes 298 dEQP-GLES31.functional.debug.* tests.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Stephane Marchesin <stephane.marchesin@gmail.com>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Nicolai Hähnle [Wed, 23 Mar 2016 20:22:16 +0000 (15:22 -0500)]
st/mesa: use RGBA instead of BGRA for SRGB_ALPHA
This fixes a regression introduced by commit
a8eea696 "st/mesa: honour sized
internal formats in st_choose_format (v2)".
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94657
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94671
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Wed, 23 Mar 2016 16:58:28 +0000 (11:58 -0500)]
radeonsi: silence a coverity warning
The following Coverity warning
5378 tmpl.fetch_args = atomic_fetch_args;
5379 tmpl.emit = atomic_emit;
>>> CID
1357115: Uninitialized variables (UNINIT)
>>> Using uninitialized value "tmpl". Field "tmpl.intr_name" is uninitialized.
5380 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
5381 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
... is a false positive, but what the hell. This change should "fix" it.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Bas Nieuwenhuizen [Thu, 24 Mar 2016 14:30:09 +0000 (08:30 -0600)]
mesa: replace gl_context->Multisample._Enabled with _mesa_is_multisample_enabled.
This removes any dependency on driver validation of the number of
framebuffer samples.
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Brian Paul <brianp@vmware.com>
Rob Clark [Tue, 22 Mar 2016 19:02:42 +0000 (15:02 -0400)]
nir: fix dangling ssadef->name ptrs
In many places, the convention is to pass an existing ssadef name ptr
when construction/initializing a new nir_ssa_def. But that goes badly
(as noticed by garbage in nir_print output) when the original string
gets freed.
Just use ralloc_strdup() instead, and add ralloc_free() in the two
places that would care (not that the strings wouldn't eventually get
freed anyways).
Also fixup the nir_search code which was directly setting ssadef->name
to use the parent instruction as memctx.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jason Ekstrand [Thu, 24 Mar 2016 04:04:18 +0000 (21:04 -0700)]
glsl: Add propagate_invariance to the other makefile
This fixes the scons build
Jason Ekstrand [Thu, 17 Mar 2016 22:20:20 +0000 (15:20 -0700)]
nir/glsl: Propagate invariant into NIR alu ops
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Jason Ekstrand [Thu, 17 Mar 2016 21:44:57 +0000 (14:44 -0700)]
glsl/rebalance_tree: Don't handle invariant or precise trees
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Jason Ekstrand [Thu, 17 Mar 2016 21:41:14 +0000 (14:41 -0700)]
glsl/opt_algebraic: Don't handle invariant or precise trees
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Jason Ekstrand [Thu, 17 Mar 2016 20:58:40 +0000 (13:58 -0700)]
glsl: Add a pass to propagate the "invariant" and "precise" qualifiers
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Jason Ekstrand [Thu, 17 Mar 2016 23:13:40 +0000 (16:13 -0700)]
nir/alu_to_scalar: Propagate the "exact" bit
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Jason Ekstrand [Thu, 17 Mar 2016 20:39:07 +0000 (13:39 -0700)]
i965/peephole_ffma: Don't fuse exact adds
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Jason Ekstrand [Thu, 17 Mar 2016 18:38:54 +0000 (11:38 -0700)]
nir/cse: Properly handle nir_ssa_def.exact
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Jason Ekstrand [Thu, 17 Mar 2016 18:31:48 +0000 (11:31 -0700)]
nir/algebraic: Flag inexact optimizations
Many of our optimizations, while great for cutting shaders down to size,
aren't really precision-safe. This commit tries to flag all of the
inexact floating-point optimizations so they don't get run on values that
are flagged "exact". It's a bit conservative and maybe flags some safe
optimizations as unsafe but that's better than missing one.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Jason Ekstrand [Wed, 23 Mar 2016 21:30:29 +0000 (14:30 -0700)]
nir/algebraic: Fix fmin detection to match the spec
The previous transformation got the arguments to fmin backwards. When NaNs
are involved, the GLSL min/max aren't commutative so it matters.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Jason Ekstrand [Wed, 23 Mar 2016 21:25:56 +0000 (14:25 -0700)]
nir/algebraic: Get rid of an invlid fxor optimization
The fxor opcode is required to return 1.0f or 0.0f but the input variable
may not be 1.0f or 0.0f.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Jason Ekstrand [Thu, 17 Mar 2016 18:04:49 +0000 (11:04 -0700)]
nir/algebraic: Allow for flagging operations as being inexact
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Jason Ekstrand [Thu, 17 Mar 2016 22:20:34 +0000 (15:20 -0700)]
nir/search: Propagate exactness into newly created expressions
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Jason Ekstrand [Thu, 17 Mar 2016 22:54:26 +0000 (15:54 -0700)]
nir/builder: Add a flag for setting exact
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Jason Ekstrand [Thu, 17 Mar 2016 17:50:27 +0000 (10:50 -0700)]
nir: Add an "exact" bit to nir_alu_instr
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Jason Ekstrand [Wed, 23 Mar 2016 22:05:55 +0000 (15:05 -0700)]
nir/clone: Export nir_variable_clone
Reviewed-by: Rob Clark <robclark@gmail.com>
Jason Ekstrand [Thu, 31 Dec 2015 02:44:19 +0000 (18:44 -0800)]
nir/clone: Expose nir_constant_clone
Reviewed-by: Rob Clark <robclark@gmail.com>
Jason Ekstrand [Wed, 23 Mar 2016 21:57:57 +0000 (14:57 -0700)]
nir: Fix whitespace
Reviewed-by: Rob Clark <robclark@gmail.com>
Brian Paul [Wed, 23 Mar 2016 18:55:45 +0000 (12:55 -0600)]
docs: use latest libDRM version
Signed-off-by: Brian Paul <brianp@vmware.com>
Lars Hamre [Wed, 23 Mar 2016 14:14:23 +0000 (10:14 -0400)]
compiler/glsl: allow sequence op as a const expr in gles 1.0
Allow the sequence operator to be a constant expression in GLSL ES
versions prior to GLSL ES 3.0
Fixes the following piglit test:
/all/spec/glsl-es-1.0/compiler/array-sized-by-sequence-in-parenthesis.vert
This is similar to the logic from process_initializer() which performs
the same check for constant variable initialization with sequence
operators.
v2: Fixed regression pointed out by Eduardo Lima Mitev
Signed-off-by: Lars Hamre <chemecse@gmail.com>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Nicolai Hähnle [Mon, 21 Mar 2016 19:50:50 +0000 (14:50 -0500)]
radeonsi: fix out-of-bounds indexing of shader images
Results are undefined but may not crash. Without this change, out-of-bounds
indexing can lead to VM faults and GPU hangs.
Constant buffers, samplers, and possibly others will eventually need similar
treatment to support GL_ARB_robust_buffer_access_behavior.
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Nicolai Hähnle [Thu, 17 Mar 2016 01:47:47 +0000 (20:47 -0500)]
radeonsi: cache flush/invalidation for missing PIPE_BARRIER_*_BUFFER bits (v2)
This fixes arb_shader_image_load_store-host-mem-barrier.
v2: flush TC L2 for index buffers on <= CIK (Marek)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 18 Mar 2016 00:49:26 +0000 (19:49 -0500)]
st/mesa: add missing MemoryBarrier bits and some explanations
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 18 Mar 2016 00:49:03 +0000 (19:49 -0500)]
gallium: add PIPE_BARRIER_STREAMOUT_BUFFER
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Marek Olšák [Tue, 22 Mar 2016 17:26:53 +0000 (18:26 +0100)]
radeonsi: fix 2D array MSAA failures since image support landed
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-and-Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Jason Ekstrand [Thu, 17 Mar 2016 02:31:02 +0000 (19:31 -0700)]
i965/fs: Don't constant-fold RCP
No shader-db changes on Broadwell
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Wed, 16 Mar 2016 23:06:10 +0000 (16:06 -0700)]
i965: Remove the RCP+RSQ algebraic optimizations
NIR already has this optimization and it can do much better than the little
peephole in the backend.
No shader-db change on Haswell or Broadwell.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Wed, 2 Mar 2016 21:47:56 +0000 (13:47 -0800)]
nir: Don't abs slt and friends
No shader-db changes, but this is symmetric with the previous commit.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Wed, 2 Mar 2016 21:46:50 +0000 (13:46 -0800)]
nir: Don't abs the result of b2f or b2i
In the results below, 2 SIMD16 shaders in Trine are lost.
G4X
total instructions in shared programs:
4012279 ->
4011108 (-0.03%)
instructions in affected programs: 116776 -> 115605 (-1.00%)
helped: 339
HURT: 0
total cycles in shared programs:
84315862 ->
84313584 (-0.00%)
cycles in affected programs:
1767232 ->
1764954 (-0.13%)
helped: 274
HURT: 81
Ironlake
total instructions in shared programs:
6399073 ->
6396998 (-0.03%)
instructions in affected programs: 218050 -> 215975 (-0.95%)
helped: 600
HURT: 0
total cycles in shared programs:
128892088 ->
128888810 (-0.00%)
cycles in affected programs:
2867452 ->
2864174 (-0.11%)
helped: 422
HURT: 137
Sandy Bridge
total instructions in shared programs:
8462174 ->
8460759 (-0.02%)
instructions in affected programs: 178529 -> 177114 (-0.79%)
helped: 596
HURT: 0
total cycles in shared programs:
117542276 ->
117534098 (-0.01%)
cycles in affected programs:
1239166 ->
1230988 (-0.66%)
helped: 369
HURT: 150
Ivy Bridge
total instructions in shared programs:
7775131 ->
7773410 (-0.02%)
instructions in affected programs: 162903 -> 161182 (-1.06%)
helped: 590
HURT: 0
total cycles in shared programs:
65759882 ->
65747268 (-0.02%)
cycles in affected programs:
1004354 -> 991740 (-1.26%)
helped: 467
HURT: 141
Haswell
total instructions in shared programs:
7107786 ->
7106327 (-0.02%)
instructions in affected programs: 140954 -> 139495 (-1.04%)
helped: 590
HURT: 0
total cycles in shared programs:
64668028 ->
64655322 (-0.02%)
cycles in affected programs: 967080 -> 954374 (-1.31%)
helped: 452
HURT: 149
LOST: 2
GAINED: 0
Broadwell
total instructions in shared programs:
8980029 ->
8978287 (-0.02%)
instructions in affected programs: 197232 -> 195490 (-0.88%)
helped: 715
HURT: 0
total cycles in shared programs:
70070448 ->
70055970 (-0.02%)
cycles in affected programs: 975724 -> 961246 (-1.48%)
helped: 471
HURT: 111
LOST: 2
GAINED: 0
Skylake
total instructions in shared programs:
9115178 ->
9113436 (-0.02%)
instructions in affected programs: 203012 -> 201270 (-0.86%)
helped: 715
HURT: 0
total cycles in shared programs:
68848660 ->
68834004 (-0.02%)
cycles in affected programs: 993888 -> 979232 (-1.47%)
helped: 473
HURT: 116
LOST: 2
GAINED: 0
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Wed, 2 Mar 2016 23:36:14 +0000 (15:36 -0800)]
nir: Simplify 0 < fabs(a)
Sandy Bridge / Ivy Bridge / Haswell
total instructions in shared programs:
8462180 ->
8462174 (-0.00%)
instructions in affected programs: 564 -> 558 (-1.06%)
helped: 6
HURT: 0
total cycles in shared programs:
117542462 ->
117542276 (-0.00%)
cycles in affected programs: 9768 -> 9582 (-1.90%)
helped: 12
HURT: 0
Broadwell / Skylake
total instructions in shared programs:
8980833 ->
8980826 (-0.00%)
instructions in affected programs: 626 -> 619 (-1.12%)
helped: 7
HURT: 0
total cycles in shared programs:
70077900 ->
70077714 (-0.00%)
cycles in affected programs: 9378 -> 9192 (-1.98%)
helped: 12
HURT: 0
G45 and Ironlake showed no change.
v2: Modify the comments to look more like a proof.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Wed, 2 Mar 2016 23:18:34 +0000 (15:18 -0800)]
nir: Simplify 0 >= b2f(a)
This also prevented some regressions with other patches in my local
tree.
Broadwell / Skylake
total instructions in shared programs:
8980835 ->
8980833 (-0.00%)
instructions in affected programs: 45 -> 43 (-4.44%)
helped: 1
HURT: 0
total cycles in shared programs:
70077904 ->
70077900 (-0.00%)
cycles in affected programs: 122 -> 118 (-3.28%)
helped: 1
HURT: 0
No changes on earlier platforms.
v2: Modify the comments to look more like a proof.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Wed, 2 Mar 2016 02:59:57 +0000 (18:59 -0800)]
nir: Simplify i2b with negated or abs operand
This enables removing ssa_201 and ssa_202 in sequences like:
vec1 ssa_200 = flt ssa_199, ssa_194
vec1 ssa_201 = b2i ssa_200
vec1 ssa_202 = i2b -ssa_201
shader-db results:
Sandy Bridge
total instructions in shared programs:
8462257 ->
8462180 (-0.00%)
instructions in affected programs: 3846 -> 3769 (-2.00%)
helped: 35
HURT: 0
total cycles in shared programs:
117542934 ->
117542462 (-0.00%)
cycles in affected programs: 20072 -> 19600 (-2.35%)
helped: 20
HURT: 1
Ivy Bridge
total instructions in shared programs:
7775252 ->
7775137 (-0.00%)
instructions in affected programs: 3645 -> 3530 (-3.16%)
helped: 35
HURT: 0
total cycles in shared programs:
65760522 ->
65760068 (-0.00%)
cycles in affected programs: 21082 -> 20628 (-2.15%)
helped: 25
HURT: 2
Haswell
total instructions in shared programs:
7108666 ->
7108589 (-0.00%)
instructions in affected programs: 3253 -> 3176 (-2.37%)
helped: 35
HURT: 0
total cycles in shared programs:
64675726 ->
64675272 (-0.00%)
cycles in affected programs: 21034 -> 20580 (-2.16%)
helped: 26
HURT: 1
Broadwell / Skylake
total instructions in shared programs:
8980912 ->
8980835 (-0.00%)
instructions in affected programs: 3223 -> 3146 (-2.39%)
helped: 35
HURT: 0
total cycles in shared programs:
70077926 ->
70077904 (-0.00%)
cycles in affected programs: 21886 -> 21864 (-0.10%)
helped: 21
HURT: 6
G45 and Ironlake showed no change.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Suggested-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Mon, 7 Mar 2016 21:09:30 +0000 (13:09 -0800)]
nir: Lower flrp with Boolean interpolator to bcsel
On Intel platforms that don't set lower_flrp, using bcsel instead of
flrp seems to be a small amount worse. On those platforms, the use of
flrp, bcsel, and multiply of b2f is still an active area of research.
In review, Matt suggested this is because bcsel turns into CMP+SEL, and
because of the flag register we can't schedule instructions well.
shader-db results:
G4X / Ironlake
total instructions in shared programs:
4016538 ->
4012279 (-0.11%)
instructions in affected programs: 161556 -> 157297 (-2.64%)
helped: 1077
HURT: 1
total cycles in shared programs:
84328296 ->
84315862 (-0.01%)
cycles in affected programs:
4174570 ->
4162136 (-0.30%)
helped: 926
HURT: 53
Unsurprisingly, no changes on later platforms.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ian Romanick [Mon, 7 Mar 2016 18:55:21 +0000 (10:55 -0800)]
i965: Have NIR lower flrp on pre-GEN6 vec4 backend
Previously we were doing the lowering by hand in vec4_visitor::emit_lrp.
By doing it in NIR, we have the opportunity for NIR to do additional
optimization of the expanded code.
This also enables optimizations added by the next commit.
shader-db results:
G4X / Ironlake
total instructions in shared programs:
4024401 ->
4016538 (-0.20%)
instructions in affected programs: 447686 -> 439823 (-1.76%)
helped: 2623
HURT: 0
total cycles in shared programs:
84375846 ->
84328296 (-0.06%)
cycles in affected programs:
16964960 ->
16917410 (-0.28%)
helped: 2556
HURT: 41
Unsurprisingly, no changes on later platforms.
v2: Formatting and comment changes suggested by Matt.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Brian Paul [Tue, 22 Mar 2016 14:35:25 +0000 (08:35 -0600)]
swrast: fix discarded const warning in s_texture.c
Signed-off-by: Brian Paul <brianp@vmware.com>
Marc-André Lureau [Fri, 18 Mar 2016 19:01:07 +0000 (20:01 +0100)]
i965: fix invalid memory write
I noticed some heap corruption running virgl tests, and valgrind
helped me to track it down to the following error:
==29272== Invalid write of size 4
==29272== at 0x90283D4: push_loop_stack (brw_eu_emit.c:1307)
==29272== by 0x9029A7D: brw_DO (brw_eu_emit.c:1750)
==29272== by 0x90554B0: fs_generator::generate_code(cfg_t const*, int) (brw_fs_generator.cpp:1999)
==29272== by 0x904491F: brw_compile_fs (brw_fs.cpp:5685)
==29272== by 0x8FC5DC5: brw_codegen_wm_prog (brw_wm.c:137)
==29272== by 0x8FC7663: brw_fs_precompile (brw_wm.c:638)
==29272== by 0x8FA4040: brw_shader_precompile(gl_context*, gl_shader_program*) (brw_link.cpp:51)
==29272== by 0x8FA4A9A: brw_link_shader (brw_link.cpp:260)
==29272== by 0x8DEF751: _mesa_glsl_link_shader (ir_to_mesa.cpp:3006)
==29272== by 0x8C84325: _mesa_link_program (shaderapi.c:1042)
==29272== by 0x8C851D7: _mesa_LinkProgram (shaderapi.c:1515)
==29272== by 0x4E4B8E8: add_shader_program (vrend_renderer.c:880)
==29272== Address 0xf2f3cb0 is 0 bytes after a block of size 112 alloc'd
==29272== at 0x4C2AA98: calloc (vg_replace_malloc.c:711)
==29272== by 0x8ED11F7: ralloc_size (ralloc.c:113)
==29272== by 0x8ED1282: rzalloc_size (ralloc.c:134)
==29272== by 0x8ED14C0: rzalloc_array_size (ralloc.c:196)
==29272== by 0x9019C7B: brw_init_codegen (brw_eu.c:291)
==29272== by 0x904F565: fs_generator::fs_generator(brw_compiler const*, void*, void*, void const*, brw_stage_prog_data*, unsigned int, bool, gl_shader_stage) (brw_fs_generator.cpp:124)
==29272== by 0x9044883: brw_compile_fs (brw_fs.cpp:5675)
==29272== by 0x8FC5DC5: brw_codegen_wm_prog (brw_wm.c:137)
==29272== by 0x8FC7663: brw_fs_precompile (brw_wm.c:638)
==29272== by 0x8FA4040: brw_shader_precompile(gl_context*, gl_shader_program*) (brw_link.cpp:51)
==29272== by 0x8FA4A9A: brw_link_shader (brw_link.cpp:260)
==29272== by 0x8DEF751: _mesa_glsl_link_shader (ir_to_mesa.cpp:3006)
if_depth_in_loop is an array of size p->loop_stack_array_size, and
push_loop_stack() will access if_depth_in_loop[p->loop_stack_depth+1],
thus the condition to grow the array should be
p->loop_stack_array_size <= (p->loop_stack_depth + 1) (it's currently
off by 2...)
This can be reproduced by running the following test with virgl test
server:
LIBGL_ALWAYS_SOFTWARE=y GALLIUM_DRIVER=virpipe bin/shader_runner
./tests/shaders/glsl-fs-unroll-explosion.shader_test -auto
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>