Torbjørn [Mon, 27 Nov 2017 05:56:53 +0000 (06:56 +0100)]
Rv32ud tests (#108)
* Probably implemented the changes required to support fadd test for rv32ud
* Created test files in rv32ud, implemented working(?) test for ldst
* fclass, fcvt_w, fmin and recoding seem to be working now
* Got fdiv (and sqrt) tests working
* fmadd tests seem to work
* fcmp works
* [WIP] fcvt working, but lacks a 32-bit implementation of the final test
* Renamed macro TEST_LDST_D32 to TEST_CASE_D32 to indicate that it can be used for more than just LDST
* Added Makefrag for rv32ud tests and included in main isa Makefile
* Don't run 64-bit tests if the defined XLEN is 32
Christopher Celio [Wed, 22 Nov 2017 22:01:26 +0000 (14:01 -0800)]
Check sepc for rv64si/scall test. (#107)
Closes #105.
Andrew Waterman [Mon, 20 Nov 2017 19:59:28 +0000 (11:59 -0800)]
Check mtval in rv64mi-p-illegal (#104)
Closes #103
Tim Newsome [Mon, 20 Nov 2017 04:54:33 +0000 (20:54 -0800)]
Ensure log file is fully written before reading it
Fixes --print-failures sometimes not actually printing out details about
failures.
Tim Newsome [Mon, 20 Nov 2017 04:54:14 +0000 (20:54 -0800)]
Make pylint happy.
Megan Wachs [Fri, 17 Nov 2017 21:43:33 +0000 (13:43 -0800)]
Merge pull request #102 from riscv/xlen_fix
debug: Fix the XLEN command line check
Megan Wachs [Fri, 17 Nov 2017 19:27:04 +0000 (11:27 -0800)]
debug: Fix the XLEN command line check
Megan Wachs [Fri, 17 Nov 2017 00:34:02 +0000 (16:34 -0800)]
Debug: Use the --32 and --64 command line arguments (#97)
* Debug: Actually use the --32 and --64 command line arguments
* debug: make XLEN mismatch message clearer
Tim Newsome [Thu, 16 Nov 2017 23:40:27 +0000 (15:40 -0800)]
Disable PMP for PrivRw test.
Tim Newsome [Thu, 16 Nov 2017 00:51:49 +0000 (16:51 -0800)]
Clarify PrivTest detail.
Andrew Waterman [Sun, 12 Nov 2017 00:15:22 +0000 (16:15 -0800)]
Make sure that code is 4-byte aligned before disabling rvc (#100)
Andrew Waterman [Fri, 10 Nov 2017 03:25:22 +0000 (19:25 -0800)]
Make rv64mi-p-ecall work when U-mode is not present
Andrew Waterman [Fri, 10 Nov 2017 01:12:49 +0000 (17:12 -0800)]
Use mstatus.MPP to check existence of U-mode
misa is allowed to be hardwired to 0, so checking its U bit could
incorrectly suggest that U-mode is not supported.
Tim Newsome [Thu, 2 Nov 2017 22:14:40 +0000 (15:14 -0700)]
Add --print-log-names to print temp log names ASAP
When not passed, they are no longer printed out.
Tim Newsome [Thu, 2 Nov 2017 20:11:50 +0000 (13:11 -0700)]
Ensure gdb connection failures end up in main log.
Megan Wachs [Thu, 2 Nov 2017 15:46:24 +0000 (08:46 -0700)]
debug: Need to apply remotetimeout before connecting to remote target (#94)
* debug: Need to apply remotetimeout before connecting to remote target
* debug: whitespace cleanup
Christopher Celio [Wed, 1 Nov 2017 20:46:34 +0000 (13:46 -0700)]
SBREAK test now checks EPC value. (#92)
Closes #89
Tim Newsome [Wed, 1 Nov 2017 19:36:36 +0000 (12:36 -0700)]
Make pylint 1.6.5 happy.
Tim Newsome [Wed, 1 Nov 2017 19:19:16 +0000 (12:19 -0700)]
Test register aliases in the simple register tests
Tim Newsome [Wed, 1 Nov 2017 18:43:04 +0000 (11:43 -0700)]
Fix MulticoreRegTest.
This test would fail intermittently if gdb on the first hart managed to
set a breakpoint, resume, halt, and clear the breakpoint before the
second hart got a chance to resume.
Palmer Dabbelt [Tue, 31 Oct 2017 23:07:21 +0000 (16:07 -0700)]
Merge pull request #90 from richardxia/comment-out-multicore-reg-test
Temporarily comment out MulticoreRegTest due to flakiness.
Richard Xia [Tue, 31 Oct 2017 20:19:21 +0000 (13:19 -0700)]
Temporarily comment out MulticoreRegTest due to flakiness.
Richard Xia [Mon, 30 Oct 2017 22:44:21 +0000 (15:44 -0700)]
Remove cache miss test from last AMO test. (#88)
Follow-up to
b68b39031a730ecc155ed87fba2ed5f111d0ab07.
The 64KiB allocated by the code to force a cache miss makes it impossible to run
the test from any memories that are smaller 64KiB, such as scratchpad memories
or LIMs. Since this is trying to test microarchitectural behavior, they don't
belong in these ISA tests anyway.
Richard Xia [Mon, 30 Oct 2017 19:18:49 +0000 (12:18 -0700)]
Declare trap handlers as global symbols. (#87)
This allows them to be referenced by other files, such as a test environment
that lives in a separate compilation unit.
Andrew Waterman [Wed, 20 Sep 2017 17:47:11 +0000 (10:47 -0700)]
Verify that mtval/stval is written correctly on misaligned fetch
Richard Xia [Fri, 27 Oct 2017 04:33:49 +0000 (21:33 -0700)]
Fix rv64mi-csr for the case where U-mode is not available. (#86)
Tim Newsome [Tue, 24 Oct 2017 18:55:01 +0000 (11:55 -0700)]
Increase dual-core RV64 timeouts.
I need this for CompareSections to pass when I instrument spike to be
really slow.
Tim Newsome [Thu, 19 Oct 2017 20:21:26 +0000 (13:21 -0700)]
Get helpful gdb output in MemTestBlock.
Tim Newsome [Thu, 12 Oct 2017 18:53:22 +0000 (11:53 -0700)]
Pay attention to server_timeout_sec
Fixes #83.
Tim Newsome [Sat, 30 Sep 2017 21:48:15 +0000 (14:48 -0700)]
Resurrect priv tests.
Tim Newsome [Wed, 4 Oct 2017 19:40:30 +0000 (12:40 -0700)]
Merge pull request #79 from riscv/multigdb
Multigdb support
Tim Newsome [Fri, 29 Sep 2017 22:41:30 +0000 (15:41 -0700)]
Make ExamineTarget multi-core aware.
Now on multi-core targets it only runs once, wasting less time.
Tim Newsome [Fri, 29 Sep 2017 20:20:30 +0000 (13:20 -0700)]
Fix tests to work in multi-gdb mode.
The Gdb class now can handle connecting to more than one gdb. It
enumerates the harts across all connections, and when asked to select a
hart, it transparently sends future gdb commands to the correct
instance.
Multicore tests still have to be aware of some differences. The main one
is that when executing 'c' in RTOS mode, all harts resume, while in
multi-gdb mode only the current one resumes. Additionally, gdb doesn't
set breakpoints until 'c' is issued, so the hart where breakpoints are
set needs to be resumed before other harts might see them.
Tim Newsome [Fri, 22 Sep 2017 19:57:51 +0000 (12:57 -0700)]
Remove unused function.
Tim Newsome [Thu, 21 Sep 2017 22:19:47 +0000 (15:19 -0700)]
Add coverage for single-core non-rtos OpenOCD.
Tim Newsome [Wed, 20 Sep 2017 00:10:36 +0000 (17:10 -0700)]
Allow multiple reset vectors.
Some boards have jumpers that control the reset vector, and forcing them
one way or another is more annoying than dealing with it in software.
Andrew Waterman [Tue, 19 Sep 2017 21:34:42 +0000 (14:34 -0700)]
Link against libm for fma()
Tim Newsome [Tue, 19 Sep 2017 21:12:12 +0000 (14:12 -0700)]
Merge pull request #76 from riscv/multicore
Add interrupts to MulticoreRunHaltStepiTest.
Tim Newsome [Tue, 19 Sep 2017 18:23:35 +0000 (11:23 -0700)]
Forgot to commit this earlier.
Fixes #77.
Tim Newsome [Mon, 18 Sep 2017 18:31:08 +0000 (11:31 -0700)]
Add interrupts to MulticoreRunHaltStepiTest.
Just to hammer on anything at once, and hopefully catch weird
interactions if they exist.
Tim Newsome [Fri, 15 Sep 2017 19:03:52 +0000 (12:03 -0700)]
Don't read entire log into RAM just to print it.
Tim Newsome [Thu, 14 Sep 2017 23:26:51 +0000 (16:26 -0700)]
misa is stored in the hart now, not the target
Tim Newsome [Thu, 14 Sep 2017 19:59:08 +0000 (12:59 -0700)]
When spike fails to launch, display its output.
Tim Newsome [Wed, 13 Sep 2017 01:48:44 +0000 (18:48 -0700)]
Test debugging code with interrupts.
Tim Newsome [Tue, 12 Sep 2017 18:21:06 +0000 (11:21 -0700)]
Call postMortem() when a test fails.
Tim Newsome [Tue, 12 Sep 2017 18:20:27 +0000 (11:20 -0700)]
Clarify timeout units.
Andrew Waterman [Thu, 14 Sep 2017 18:11:44 +0000 (11:11 -0700)]
Move link options to end of gcc command line
Tim Newsome [Tue, 12 Sep 2017 16:36:34 +0000 (09:36 -0700)]
Merge pull request #69 from riscv/multicore
Proper multicore support for debug tests
Andrew Waterman [Fri, 1 Sep 2017 18:15:44 +0000 (11:15 -0700)]
Improve ma_fetch test to cover JAL and branches
Tim Newsome [Fri, 1 Sep 2017 19:31:15 +0000 (12:31 -0700)]
Add some infrastructure for multicore tests.
When compiling, define the number of harts. This means we only need to
allocate a lot of stack if there are a lot of harts.
Tim Newsome [Fri, 1 Sep 2017 19:03:40 +0000 (12:03 -0700)]
Use 32-bit link script for 32-bit target.
Tim Newsome [Mon, 28 Aug 2017 20:40:15 +0000 (13:40 -0700)]
This file isn't ready yet.
Tim Newsome [Mon, 28 Aug 2017 19:43:08 +0000 (12:43 -0700)]
Forgot to add this file.
Tim Newsome [Mon, 28 Aug 2017 19:17:37 +0000 (12:17 -0700)]
Increase remotetimeout for spike targets.
On overloaded systems, when executing compare-sections, otherwise gdb
might hit a timeout and the compare-sections code doesn't deal with it.
(You get an error message complaining that 130 is not a valid hex
digit.)
Tim Newsome [Tue, 15 Aug 2017 22:32:24 +0000 (15:32 -0700)]
Fix rebase bug.
Tim Newsome [Sun, 13 Aug 2017 20:56:44 +0000 (13:56 -0700)]
Make MemTestBlock output a more descriptive error.
Tim Newsome [Sun, 13 Aug 2017 19:50:39 +0000 (12:50 -0700)]
Fix MemTest* after sloppy rebase.
Tim Newsome [Fri, 11 Aug 2017 20:25:06 +0000 (13:25 -0700)]
Rename test to MulticoreRunHaltStepiTest.
Tim Newsome [Fri, 11 Aug 2017 19:55:25 +0000 (12:55 -0700)]
Make pylint happy.
Tim Newsome [Thu, 10 Aug 2017 18:27:04 +0000 (11:27 -0700)]
WIP multicore testing.
Tim Newsome [Mon, 7 Aug 2017 22:13:09 +0000 (15:13 -0700)]
WIP towards multiple gdb instances.
Tim Newsome [Mon, 7 Aug 2017 19:51:42 +0000 (12:51 -0700)]
Make the debug tests aware of multicore.
Targets now contain an array of harts. When running a regular test, one
hart is selected to run the test on while the remaining harts are parked
in a safe infinite loop.
There's currently only one test that tests multicore behavior, but there
could be more.
The infrastructure should be able to support heterogeneous multicore,
but I don't have a target like that to test with.
Tim Newsome [Mon, 28 Aug 2017 19:11:49 +0000 (12:11 -0700)]
Increase delay in UserInterrupt.
When a machine is very loaded, otherwise it could happen that we send
the interrupt before the resume has actually happened.
Palmer Dabbelt [Wed, 16 Aug 2017 20:42:50 +0000 (13:42 -0700)]
Merge pull request #67 from riscv/sfence_vma
Inform GCC that "sfence.vma" clobbers memory
Palmer Dabbelt [Wed, 16 Aug 2017 19:26:25 +0000 (12:26 -0700)]
Inform GCC that "sfence.vma" clobbers memory
Tim Newsome [Mon, 14 Aug 2017 22:24:41 +0000 (15:24 -0700)]
Put logfile code back so everything works again.
I don't exactly understand why it has to be the way it is, but I just
want it to work.
Also fix a pylint complaint.
Megan Wachs [Mon, 14 Aug 2017 20:33:31 +0000 (13:33 -0700)]
Merge pull request #66 from riscv/debug_user_niceness
Debug: Usability Features
Megan Wachs [Mon, 14 Aug 2017 20:26:02 +0000 (13:26 -0700)]
debug: clean up Temporary Log File messages
Megan Wachs [Mon, 14 Aug 2017 20:24:04 +0000 (13:24 -0700)]
debug: Avoid None type error
Megan Wachs [Mon, 14 Aug 2017 17:59:34 +0000 (10:59 -0700)]
debug: Revert change to print backtrace, as that is actually already printed
Megan Wachs [Mon, 14 Aug 2017 17:58:22 +0000 (10:58 -0700)]
debug: Allow OpenOCD startup timeout to be specified. Print out path to log files.
Megan Wachs [Mon, 14 Aug 2017 17:17:01 +0000 (10:17 -0700)]
When a test fails with exception, actually print out the reason why.
Tim Newsome [Sun, 13 Aug 2017 19:33:07 +0000 (12:33 -0700)]
Make MemTest* catch reading too many words.
For one of the test addresses, use the highest possible one to ensure
that OpenOCD isn't secretly reading/writing more words than requested.
Tim Newsome [Fri, 11 Aug 2017 21:56:36 +0000 (14:56 -0700)]
Show the OpenOCD log in all(?) failure cases.
Tim Newsome [Fri, 11 Aug 2017 21:33:54 +0000 (14:33 -0700)]
Print out name of logfile when debug test is run.
Tim Newsome [Fri, 11 Aug 2017 21:13:41 +0000 (14:13 -0700)]
When make fails to run a test, print out the log.
Tim Newsome [Fri, 11 Aug 2017 18:15:11 +0000 (11:15 -0700)]
Don't use `set pipefail` which is a bashism.
Instead, just give up on making the log files altogether now. Since
gdbserver.py makes its own log files it's not as necessary in any case.
This is yet another commit in an attempt to get the riscv-tools build to
actually fail if these tests fail.
Tim Newsome [Fri, 11 Aug 2017 17:48:19 +0000 (10:48 -0700)]
Don't eat errors in debug Makefile.
Tim Newsome [Thu, 10 Aug 2017 21:23:29 +0000 (14:23 -0700)]
Don't run debug tests as part of build.
Testing is a separate step.
Also fix Issue #64 by adding src_dir to the path to the targets file.
Tim Newsome [Thu, 10 Aug 2017 20:30:37 +0000 (13:30 -0700)]
Pylint target files as well.
This would have prevented some bugs I committed earlier.
Tim Newsome [Thu, 10 Aug 2017 18:43:49 +0000 (11:43 -0700)]
Give these sim targets a chance of passing.
Also make sure vsim.log makes it into the generated log file.
Palmer Dabbelt [Tue, 8 Aug 2017 22:37:26 +0000 (15:37 -0700)]
Merge pull request #62 from richardxia/only-emit-f-instructions-when-compiled-for-f
rv64[ms]i-csr: Only emit F instructions when compiled for F.
Richard Xia [Mon, 7 Aug 2017 23:57:14 +0000 (16:57 -0700)]
rv64[ms]i-csr: Only emit F instructions when compiled for F.
Andrew Waterman [Fri, 4 Aug 2017 17:20:00 +0000 (10:20 -0700)]
RV32 div tests should use -2^31 for min value, not -2^63
Andrew Waterman [Fri, 4 Aug 2017 07:23:04 +0000 (00:23 -0700)]
Improve RVC test
Make the page-crossing instruction non-idempotent to detect erroneously
executing the first 16 bits of the instruction with garbage MSBs.
Tim Newsome [Mon, 31 Jul 2017 20:49:34 +0000 (13:49 -0700)]
Fix the end of MulticoreTest.
Now it actually confirms that we're talking to two different cores which
have different values in their registers. Previously it could have been
fooled if eg. the thread command was a nop.
Tim Newsome [Thu, 27 Jul 2017 20:34:54 +0000 (13:34 -0700)]
Make pylint happy.
Tim Newsome [Wed, 26 Jul 2017 14:56:35 +0000 (07:56 -0700)]
Use new OpenOCD messages to determine gdb port.
This is simpler and more reliable than playing around with lsof.
Specifically, it works if the OpenOCD command is "strace openocd" while
the previous code did not.
Tim Newsome [Fri, 21 Jul 2017 18:49:15 +0000 (11:49 -0700)]
Only clean up logfiles that we know we created.
Tim Newsome [Fri, 21 Jul 2017 03:43:18 +0000 (20:43 -0700)]
Add back code to clean up triggers in entry.S
Then for targets that can't handle this because they don't implement
hmode, add a target setting that allows that to be specified.
Tim Newsome [Tue, 18 Jul 2017 18:35:59 +0000 (11:35 -0700)]
Check all PCs after reset.
Tim Newsome [Thu, 13 Jul 2017 03:26:21 +0000 (20:26 -0700)]
Print out logs in more failure cases.
Tim Newsome [Thu, 6 Jul 2017 22:09:09 +0000 (15:09 -0700)]
Merge pull request #58 from riscv/fpga_reset_halt
debug: Make the 'out of reset' tests apply reset
mwachs5 [Thu, 6 Jul 2017 22:04:27 +0000 (15:04 -0700)]
debug: Make the 'out of reset' tests actually apply reset
Tim Newsome [Mon, 3 Jul 2017 17:48:58 +0000 (10:48 -0700)]
Add gdb_setup to target for arbitrary gdb commands
I'm using this for a target where misa is at an old address, to
set riscv use_compressed_breakpoints off
Tim Newsome [Mon, 3 Jul 2017 17:36:03 +0000 (10:36 -0700)]
Don't clear triggers during execution.
This shouldn't affect triggers set by the debugger, because running code
can't change those. When it does affect them, it breaks Hwbp1 which sets
the breakpoint before running the program.
Tim Newsome [Tue, 27 Jun 2017 17:53:16 +0000 (10:53 -0700)]
Tolerate missing misa register.
At least in the test programs. There are other places where this causes
trouble as well.
Tim Newsome [Tue, 27 Jun 2017 17:28:10 +0000 (10:28 -0700)]
Merge pull request #55 from riscv/debug
Test gdb/OpenOCD during regular test run.
Tim Newsome [Tue, 27 Jun 2017 17:27:41 +0000 (10:27 -0700)]
Merge pull request #56 from riscv/config
Move target definition into individual files.
Tim Newsome [Mon, 26 Jun 2017 17:00:34 +0000 (10:00 -0700)]
Move target definition into individual files.
Instead of defining each target in targets.py, now each target gets its
own .py file. This means people can easily keep their own target files
around that they may not want to put into the main test source. As part
of that, I removed the freedom-u500-sim target since I assume it's only
used internally at SiFive.
Added a few cleanups as well:
* Update README examples, mostly --sim_cmd instead of --cmd.
* Allow defining misa in a target, to skip running of ExamineTarget.
* Rename target.target() to target.create(), which is less confusing.
* Default --sim_cmd to `spike`
* Got rid of `use_fpu`, instead looking at F or D in $misa.