virgl: stricter usage of compressed 3d textures

Using RGTC, ETC1, ETC2 or S3TC for 3D-textures isn't alowed by any of
OpenGL 4.6, OpenGL ES 3.2, ARB_texture_compression_rgtc,
EXT_texture_compression_rgtc, OES_compressed_ETC1_RGB8_texture,
S3_s3tc or EXT_texture_compression_s3tc specifications.

So let's not allow any of those compressed 3d-textures at all. It's not
going to work once it hits the OpenGL driver in virglrenderer.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>

virgl: do not allow compressed formats for buffers

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>

dri3: Return the current swap interval from glXGetSwapIntervalMESA().

We were caching only the value set with glXSwapIntervalSGI(), missing out
on the default setting of the swap interval by the loader.  This fixes
glxgears's warning about being vblank synchronized by default.

Fixes: 9777c4234b0e ("loader: drop the [gs]et_swap_interval callbacks")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

intel: Add support for Comet Lake

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

iris: Adapt to variable ppGTT size

Not all hardware is made equal and some does not have the full
complement of 48b of address space. Ask what the actual size of virtual
address space allocated for contexts, and bail if that is not enough to
satisfy our static partitioning needs.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

radv: partially enable VK_KHR_shader_float16_int8

Only 8-bit integers for now, float16 requires a bit more work.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac: add 8-bit and 64-bit support to ac_build_bitfield_reverse()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac: add 8-bit support to ac_build_umsb()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac: add 8-bit support to ac_find_lsb()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac: add 8-bit support to ac_build_bit_count()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac/nir: add support for nir_op_b2i8

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radeonsi: implement ARB/KHR_parallel_shader_compile callbacks

util/queue: add util_queue_adjust_num_threads

for ARB_parallel_shader_compile

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

util/queue: hold a lock when reading num_threads in util_queue_finish

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

util/queue: add ability to kill a subset of threads

for ARB_parallel_shader_compile

util/queue: move thread creation into a separate function

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

gallium: implement ARB/KHR_parallel_shader_compile

mesa: implement ARB/KHR_parallel_shader_compile

Tested by piglit.

radeonsi: fix assertion failure by using the correct type

src/gallium/drivers/radeonsi/si_state_viewport.c:196: si_emit_guardband:
Assertion `vp_as_scissor.maxx <= max_viewport_size[vp_as_scissor.quant_mode]
&& vp_as_scissor.maxy <= max_viewport_size[vp_as_scissor.quant_mode]' failed.

The comparison was unsigned, so negative maxx or maxy would fail.

Fixes: 3c540e0a7488 "radeonsi: Fix guardband computation for large render targets"

radeon/vcn/vp9: search the render target from the whole list

The number of render targets could be more than max of references,
so we search the full list of the render pictures for the current
render target index

https://bugs.freedesktop.org/show_bug.cgi?id=109648

Signed-off-by: Leo Liu <leo.liu@amd.com>
Tested-by: James Zhu <James.Zhu@amd.com>
Acked-by: James Zhu<James.Zhu@amd.com>
Cc: <mesa-stable@lists.freedesktop.org>

radv: lower 16-bit flrp

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

ac: fix ac_build_umsb() for 16-bit integer type

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac: fix ac_find_lsb() for 16-bit integer type

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac: fix ac_build_bitfield_reverse() for 16-bit integer type

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac: fix ac_build_bit_count() for 16-bit integer type

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

ac/nir: fix nir_op_b2i16

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

meson: strip rpath from megadrivers

More specifically, use the library file that has been post-processed by Meson
when creating the hardlinks.

Bugs: https://bugs.freedesktop.org/show_bug.cgi?id=108766
Fixes: 3218056e0eb375eeda47 "meson: Build i965 and dri stack"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>

spirv: fix a compiler warning

Fixes implicit conversion from enumeration type 'SpvOp' warning.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

i965: perf: update render basic configs for big core gen9/gen10

This updates allows an MI_LRI to trigger a OA report write in the
global OA buffer. This isn't really useful for us, we just keep close
to the internal public configs.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: perf: add ring busyness metric for cfl gt2

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: perf: enable Icelake metrics

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: perf: add Icelake metrics

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: perf: sklgt2: drop programming of an unused NOA register

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: perf: hsw: drop register programming not needed on HSW

This register is flagged as IVB only in the documentation.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: perf: chv: fixup counters names

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: perf: add PMA stall metrics

These are new metrics for Gen8/9 to measure the effect of the PMA
stall workaround fix.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: perf: sklgt2: update memory write config

This rework the programming between older pre-production steppings &
new ones.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: perf: sklgt2: update compute metrics config

This unifies some of the programming between pre-production stepping
and production ones.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: perf: sklgt2: update a priority for register programming

This makes no difference in term of programming, it's just a cleanup.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

panfrost: Implement FIXED formats

Fixes crash in dEQP-GLES2.functional.draw.random.9

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost: Fix index calculation types and asserts

Fixes crash in
dEQP-GLES2.functional.draw.draw_elements.points.single_attribute.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost: Clean index state between indexed draws

Fixes subsequent tests in
dEQP-GLES2.functional.draw.draw_elements.indices.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost/decode: Print negative_start

This property slipped through..

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost: Implement missing texture formats

 - Implements RGB565/RGBA5551 formats
 - Don't advertise support for flipped RGBA5551 and ETC

Fixes remaining tests in dEQP-GLES2.functional.texture.format.* which is
now at 36/36.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost: Extend tiling for cubemaps

transfer_unmap now tiles for any tiled resource, not just TEXTURE_2D,
which should more than just cubemaps!

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost: Implement command stream for linear cubemaps

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost/midgard: Emit cubemap coordinates

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost: Include all cubemap faces in bitmap list

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost/decode: Decode all cubemap faces

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost: Preliminary work for cubemaps

Again, not yet functional, but this sets up the memory management for
cube maps.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost/midgard: Add L/S op for writing cubemap coordinates

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost/midgard: Disassemble `cube` texture op

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

panfrost: Fix vertex buffer corruption

Fixes crash in dEQP-GLES2.functional.buffer.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

iris: fix set_sampler_view

Update to match docs.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

gallium/docs: clarify set_sampler_views (v2)

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

freedreno/ir3: convert to "new style" frag inputs

Add support for load_barycentric_pixel, load_interpolated_input, and
friends.  For now, this retains support for old-style inputs, which can
probably be dropped with some ttn work.

Prep work for sample-shading support.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: add pass to move varying loads

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: rework varying packing

Originally we kept track of a table of inputs.  But with new-style frag
inputs this becomes awkward.  Re-work it so that initially we assigned
un-packed varying locations, and then after the shader is compiled scan
to find actual used inputs, and re-pack.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: re-indent comment

Make it more clear that it applies to the following 'case' statements,
rather than the previous one.

Signed-off-by: Rob Clark <robdclark@gmail.com>

nir: add lower_all_io_to_elements

I need this part of lower_all_io_to_temps but without the actual
lowering to temps part.

Signed-off-by: Rob Clark <robdclark@gmail.com>

nir: print var name for load_interpolated_input too

Signed-off-by: Rob Clark <robdclark@gmail.com>
Acked-by: Karol Herbst <kherbst@redhat.com>

i965,iris/blorp: do not blit 0-sizes

Seems there is no sense in blitting 0-sized sources
or destinations.
Additionaly it may cause segfaults for i965.

v2: Function call replaced with inline check

v3: Added check to avoid devision by zero (L. Landwerlin)

v4: Added simillar check for Iris (L. Landwerlin)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110239
Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

gallium: Fix autotools build with libxatracker.la.

  CXXLD    libxatracker.la
/usr/bin/ld: ../../../../src/gallium/auxiliary/.libs/libgallium.a(tgsi_to_nir.o): in function `ttn_finalize_nir':
src/gallium/auxiliary/nir/tgsi_to_nir.c:2111: undefined reference to `gl_nir_lower_samplers_as_deref'
/usr/bin/ld: src/gallium/auxiliary/nir/tgsi_to_nir.c:2113: undefined reference to `gl_nir_lower_samplers'

Fixes: 9a834447d652 ("tgsi_to_nir: Produce optimized NIR for a given pipe_screen.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109929
Signed-off-by: Vinson Lee <vlee@freedesktop.org>

gallium: fix autotools build of pipe_msm.la

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Fixes: 9a834447d652 ("tgsi_to_nir: Produce optimized NIR for a given pipe_screen.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109929

nir: Lock around validation fail shader dumping

This prevents getting mixed-up results if a multi-threaded app has two
validation errors in different threads.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

util: no-op __builtin_types_compatible_p() for non-GCC compilers

__builtin_types_compatible_p() is GCC-specific and breaks the
MSVC build.

This intrinsic has been in u_vector_foreach() for a long time, but
that macro has only recently been used in code
(nir/nir_opt_comparison_pre.c) that's built with MSVC.

Fixes: 2cf59861a ("nir: Add partial redundancy elimination for compares")
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

iris: Clean up compiler warnings about unused

Removed a few unused variables and iris_getparam_boolean().
Kept 'name' around since there's a commented debug that make use of it.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

egl: hide entrypoints that shouldn't be exported when using glvnd

From GLVND author:
> From a functional standpoint, exporting additional symbols doesn't
> really matter, since libglvnd will load the vendor libraries with
> RTLD_LOCAL.

Suggested-by: Kyle Brenneman <kbrenneman@nvidia.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Kyle Brenneman <kbrenneman@nvidia.com>

nir/validate: validate that tex deref sources are actually derefs

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/print: fix printing the image_array intrinsic index

Fixes: 0de003be0363 ("nir: Add handle/index-based image intrinsics")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

Revert "ac/nir: use new LLVM 8 intrinsics for SSBO atomic operations"

This reverts commit 29132af2347ede46a6d02422295a5fadbe5fe788.

It seems the new intrinsic causes a hang on radeonsi (VEGA) when running the
piglit test:

tests/spec/arb_shader_storage_buffer_object/execution/ssbo-atomicCompSwap-int.shader_test

ac: fix return type for llvm.amdgcn.frexp.exp.i32.64

This fixes the following piglit with RadeonSI
tests/spec/arb_gpu_shader_fp64/execution/built-in-functions/fs-frexp-dvec4.shader_test

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

virgl: Add a caps feature check version

When we add new feature checks on the host side that is used to
enable a cap conditionally that was enabled unconditionally before
we might end up with a feature regression when a new mesa version
is used with an old virglrenderer version that doesn't check for
that cap.

To work around this problem add a version id to the caps that corresponds
to the features that are actually checked on the host and check that
version too when enabling the cap.

Fixes: 2ee197d6e84aa37638d423363aca183952816067
    virgl: Enable mixed color FBO attachemnets only when the host supports it

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Pohsien Wang <pwang@chromium.org>

radv: do not always initialize HTILE in compressed state

Especially when performing a transtion from UNDEFINED->GENERAL,
the driver shouldn't initialize HTILE metadata in compressed
state because it doesn't decompress when the src layout is
GENERAL.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110259
Fixes: 3a2e93147f7 ("radv: always initialize HTILE when the src layout is UNDEFINED")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

iris: Print the memzone name when allocating BOs with INTEL_DEBUG=buf

This gives me an idea of what kinds of buffers are being allocated on
the fly which could help inform our cache decisions.

nir: use {0} initializer instead of {} to fix MSVC build

Trivial change.

Fixes: c6ee46a75 ("nir: Add nir_alu_srcs_negative_equal")

intel/compiler: Use partial redundancy elimination for compares

Almost all of the hurt shaders are repeated instances of the same shader
in synmark's compilation speed tests.

shader-db results:

All Gen6+ platforms had similar results. (Skylake shown)
total instructions in shared programs: 15256840 -> 15256389 (<.01%)
instructions in affected programs: 54137 -> 53686 (-0.83%)
helped: 288
HURT: 0
helped stats (abs) min: 1 max: 15 x̄: 1.57 x̃: 1
helped stats (rel) min: 0.06% max: 26.67% x̄: 1.99% x̃: 0.74%
95% mean confidence interval for instructions value: -1.76 -1.38
95% mean confidence interval for instructions %-change: -2.47% -1.50%
Instructions are helped.

total cycles in shared programs: 372286583 -> 372283851 (<.01%)
cycles in affected programs: 833829 -> 831097 (-0.33%)
helped: 265
HURT: 16
helped stats (abs) min: 2 max: 74 x̄: 11.81 x̃: 4
helped stats (rel) min: 0.04% max: 9.07% x̄: 0.99% x̃: 0.35%
HURT stats (abs)   min: 2 max: 130 x̄: 24.88 x̃: 8
HURT stats (rel)   min: <.01% max: 12.31% x̄: 1.44% x̃: 0.27%
95% mean confidence interval for cycles value: -12.30 -7.15
95% mean confidence interval for cycles %-change: -1.06% -0.64%
Cycles are helped.

Iron Lake and GM45 had similar results. (GM45 shown)
total instructions in shared programs: 5038653 -> 5038495 (<.01%)
instructions in affected programs: 13939 -> 13781 (-1.13%)
helped: 50
HURT: 1
helped stats (abs) min: 1 max: 15 x̄: 3.18 x̃: 4
helped stats (rel) min: 0.33% max: 13.33% x̄: 2.24% x̃: 1.09%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 0.83% max: 0.83% x̄: 0.83% x̃: 0.83%
95% mean confidence interval for instructions value: -3.73 -2.47
95% mean confidence interval for instructions %-change: -3.16% -1.21%
Instructions are helped.

total cycles in shared programs: 128118922 -> 128118228 (<.01%)
cycles in affected programs: 134906 -> 134212 (-0.51%)
helped: 50
HURT: 0
helped stats (abs) min: 2 max: 60 x̄: 13.88 x̃: 18
helped stats (rel) min: 0.06% max: 3.19% x̄: 0.74% x̃: 0.70%
95% mean confidence interval for cycles value: -16.54 -11.22
95% mean confidence interval for cycles %-change: -0.95% -0.53%
Cycles are helped.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

nir: Add partial redundancy elimination for compares

This pass attempts to dectect code sequences like

    if (x < y) {
        z = y - x;
...
    }

and replace them with sequences like

    t = x - y;
    if (t < 0) {
        z = -t;
...
    }

On architectures where the subtract can generate the flags used by the
if-statement, this saves an instruction.  It's also possible that moving
an instruction out of the if-statement will allow
nir_opt_peephole_select to convert the whole thing to a bcsel.

Currently only floating point compares and adds are supported.  Adding
support for integer will be a challenge due to integer overflow.  There
are a couple possible solutions, but they may not apply to all
architectures.

v2: Fix a typo in the commit message and a couple typos in comments.
Fix possible NULL pointer deref from result of push_block().  Add
missing (-A + B) case.  Suggested by Caio.

v3: Fix is_not_const_zero to work correctly with types other than
nir_type_float32.  Suggested by Ken.

v4: Add some comments explaining how this works.  Suggested by Ken.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

nir: Add nir_alu_srcs_negative_equal

v2: Move bug fix in get_neg_instr from the next patch to this patch
(where it was intended to be in the first place).  Noticed by Caio.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

nir: Add nir_const_value_negative_equal

v2: Rebase on 1-bit Boolean changes.

Reviewed-by: Thomas Helland <thomashelland90@gmail.com> [v1]
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

nir/algebraic: Add missing 16-bit extract_[iu]8 patterns

No shader-db changes on any Intel platform.

v2: Use a loop to generate patterns.  Suggested by Jason.

v3: Fix a copy-and-paste bug in the extract_[ui] of ishl loop that would
replace an extract_i8 with and extract_u8.  This broke ~180 tests.  This
bug was introduced in v2.

Reviewed-by: Matt Turner <mattst88@gmail.com> [v1]
Reviewed-by: Dylan Baker <dylan@pnwbakers.com> [v2]
Acked-by: Jason Ekstrand <jason@jlekstrand.net> [v2]

nir/algebraic: Add missing 64-bit extract_[iu]8 patterns

No shader-db changes on any Intel platform.

v2: Use a loop to generate patterns.  Suggested by Jason.

v3: Fix a copy-and-paste bug in the extract_[ui] of ishl loop that would
replace an extract_i8 with and extract_u8.  This broke ~180 tests.  This
bug was introduced in v2.

Reviewed-by: Matt Turner <mattst88@gmail.com> [v1]
Reviewed-by: Dylan Baker <dylan@pnwbakers.com> [v2]
Acked-by: Jason Ekstrand <jason@jlekstrand.net> [v2]

nir/algebraic: Remove redundant extract_[iu]8 patterns

No shader-db changes on any Intel platform.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>

nir/algebraic: Fix up extract_[iu]8 after loop unrolling

Skylake, Broadwell, and Haswell had similar results. (Skylake shown)
total instructions in shared programs: 15256840 -> 15256837 (<.01%)
instructions in affected programs: 4713 -> 4710 (-0.06%)
helped: 3
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.06% max: 0.08% x̄: 0.06% x̃: 0.06%

total cycles in shared programs: 372286583 -> 372286583 (0.00%)
cycles in affected programs: 198516 -> 198516 (0.00%)
helped: 1
HURT: 1
helped stats (abs) min: 10 max: 10 x̄: 10.00 x̃: 10
helped stats (rel) min: <.01% max: <.01% x̄: <.01% x̃: <.01%
HURT stats (abs)   min: 10 max: 10 x̄: 10.00 x̃: 10
HURT stats (rel)   min: 0.01% max: 0.01% x̄: 0.01% x̃: 0.01%

No changes on any other Intel platform.

v2: Use a loop to generate patterns.  Suggested by Jason.

v3: Fix a copy-and-paste bug in the extract_[ui] of ishl loop that would
replace an extract_i8 with and extract_u8.  This broke ~180 tests.  This
bug was introduced in v2.

Reviewed-by: Matt Turner <mattst88@gmail.com> [v1]
Reviewed-by: Dylan Baker <dylan@pnwbakers.com> [v2]
Acked-by: Jason Ekstrand <jason@jlekstrand.net> [v2]

nir/deref: fix struct wrapper casts. (v3)

llvm/spir-v spits out some struct a { struct b {} }, but it
doesn't deref, it casts (struct a) to (struct b), reconstruct
struct derefs instead of casts for these.

v2: use ssa_def_rewrite uses, rework the type restrictions (Jason)
v3: squish more stuff into one function, drop unused temp (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965/blorp: Remove unused parameter from blorp_surf_for_miptree.

It seems pretty useless nowadays.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

iris/icl: Add WA_2204188704 to disable pixel shader panic dispatch

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

iris/icl: Set Enabled Texel Offset Precision Fix bit

h/w specification requires this bit to be always set.
See Mesa commit 5eb173304bd.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

freedreno/ir3: align const size to vec4

This is no longer true since PIPE_CAP_PACKED_UNIFORMS was enabled.

Fixes: 3c8779af325 freedreno/ir3: Enable PIPE_CAP_PACKED_UNIFORMS
Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: reads/writes to unrelated arrays are not dependent

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: sched fix

Not sure why new-style frag inputs start triggering this.  But we
probably shouldn't consider src's from other blocks.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a6xx: small cleanup

Signed-off-by: Rob Clark <robdclark@gmail.com>

iris: Fix blits with S8_UINT destination

For depth and stencil blits, we always want the main mask to be Z, and
the secondary pass mask to be S.  If asked to blit Z+S to S, we should
handle the blit in the second pass which properly gets the stencil
resources.

Before, we were trying to handle S as the main mask, and accidentally
blitting a Z source to a S destination, which doesn't work out well.

Fixes Piglit's "framebuffer-blit-levels {draw,read} stencil" tests.

st/mesa: Fix blitting from GL_DEPTH_STENCIL to GL_STENCIL_INDEX

Fixes assertion failures in Piglit's "framebuffer-blit-levels
{draw,read} stencil" tests on iris.  Also fixes assert failures in
frameretrace, which tries to ReadPixels the stencil values (only)
from a Z24S8 depth/stencil attachment.

Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>

freedreno/ir3: Add workaround for VS samgq

This instruction needs a workaround when used from vertex shaders.

Fixes:

  dEQP-GLES3.functional.shaders.texture_functions.texturegradoffset.sampler2dshadow_vertex
  dEQP-GLES3.functional.shaders.texture_functions.texturegradoffset.sampler3d_fixed_vertex
  dEQP-GLES3.functional.shaders.texture_functions.texturegradoffset.sampler3d_float_vertex
  dEQP-GLES3.functional.shaders.texture_functions.textureprojgradoffset.sampler2dshadow_vertex
  dEQP-GLES3.functional.shaders.texture_functions.textureprojgradoffset.sampler3d_fixed_vertex
  dEQP-GLES3.functional.shaders.texture_functions.textureprojgradoffset.sampler3d_float_vertex
  dEQP-GLES3.functional.shaders.texture_functions.textureprojgrad.sampler2dshadow_vertex

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: Don't access beyond available regs

emit_cat5() needs to check if the last optional reg is there before it
accesses it.

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>

util/disk_cache: close fd in the fallback path

There are multiple `goto path_fail` with an open fd, but none that go to
`fail:` without going through `path_fail:` first, so let's just move the
`close(fd)` there.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

radv: skip updating depth/color metadata for conditional rendering

I don't think we should update metadata when conditional rendering
is enabled. For some reasons, some CTS breaks only on SI.

This fixes the following CTS on SI:
dEQP-VK.conditional_rendering.draw_clear.clear.depth.*

Cc: 19.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

st/nir: Free the GLSL IR after linking.

i965 does this, and st's tgsi path does this.  st/nir did not.

Cuts 138MB of memory from a DiRT Rally trace, which is about 44%
of the total GLSL IR memory.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radv: enable VK_AMD_gpu_shader_int16

This extension allows 16-bit support to Frexp/FrexpStruct.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>