arch-riscv: fault on mstatus accesses from lower privilege modes.

Change-Id: If2e35445770eaa52f5af6f9ef02fb5e11bef8da4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25652
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

arch-riscv: ignore writes to SXL/UXL fields in status register.

We currently only support SXL=UXL=2 (64 bit). These fields are WARL,
so that we have to make sure that no other value can be set.

Change-Id: I62ddc7d68b8c31ca655ba1ccee7a294912f46b09
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25651
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

arch-riscv: added (un)serialization of miscRegFile.

Change-Id: I127dbf4a6bb4a144eaee05a87495830dce82eb58
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25650
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

arch-riscv: show names of MiscRegs on accesses.

Printing the number of the MiscRegs makes it hard to debug problems.
Therefore, this commit adds a name table and prints the name of the
register.

Change-Id: Icd53d5524a5d5daf3e50f253cdda56341663f26e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25649
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

arch-riscv: fixed read of {M,S,U}TVEC.

As stated in 4.1.4 of the privileged ISA manual, the BASE field in the
STVEC register contains the bits [SXLEN-1:2] of the base address, not
the base address shifted left by 2.

Change-Id: I799ec0dc1cbd7b271b91b53adb033a5d1ca3306f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25648
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

configs: added bare metal FS support for RISC-V.

Change-Id: Id412186d868680b9af97503a5337fc394fd84f68
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26989
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu,configs: let RISC-V use the PT walker cache.

Change-Id: I19b1dd9e3c55c433c897988d36e6715017273c66
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26988
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

arch-riscv: fixed formatting.

Change-Id: I134993a4aced07e75bf62fec56081b0f9d8fc18c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26986
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

arch-riscv: implement RemoteGDB::acc for FS mode.

Change-Id: I78b37db43fbb16d4dafa74294117e8beba62f903
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26985
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

arch-riscv: implement sfence.vma to flush TLBs.

Change-Id: I424123d3c94c9673269f922cd6755f0bbf5b6cc0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26984
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv: make sure only supported modes can be set in SATP.

Change-Id: I37c67e491d64bf03d1125e23db28611fa0b16038
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26983
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

arch-riscv: added TLB and page table walker.

That is, RISC-V has now a TLB and page table walker for Sv39 paging
according to the privileged ISA 1.11.

Both the TLB and PT walker are based on x86 (the code duplication of the
page table walkers will be reduced by a separate commit).

Change-Id: I5e29683bdd40c0d32c06e4d75a8382bf313f2086
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25647
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Add a unit test for some aspects of the aapcs64 ABI.

This test covers the templates which attempt to classify types, but not the
actual gathering of arguments of distribution of return values. As before, we
can't really use standard C++ to accurately test for HFAs and HVAs, so we stick
with approximating them by detecting arrays of the right types.

For example, I think technically we should also accept a struct with only 4
float members, but c++ templates aren't able to match against types in that way
as far as I know.

Change-Id: I1d7756a964a86c0c5ea13e068a5fc74603e14e30
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28268
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Fix some bugs in the aapcs64 implementation.

The templates which checked for short vectors, and our approximation of
HFA, HVA and HXA types were not correct. This change actually simplifies
them along with getting them to produce correct results. In the case of
HXA, there was a logic bug where an && was used where an || was
intended.

There may still be bugs in the actual collection of arguments and
setting of return values since those aspects are harder to test.

Change-Id: Ice3177205a98c678ecb43ba600813b3909c44e6b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28267
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Add missing requestToMemory MessageBuffers

In commit 53b6e21 two protocol config files were missed when the new
requestToMemory MessageBuffers were added. This fixes the issue such
that all Ruby protocols are working again.

Change-Id: Iaa04c792eaf6d659ba13c19f003e7e31b71ffdb4
JIRA: https://gem5.atlassian.net/browse/GEM5-468
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28187
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix clasta/b and lasta/b simd&fp instructions

The simd&fp version of this instructions required zeroing the result
vector except for the first element, that contains the result.

Change-Id: I231ad3c44d89f34acae26d299ab676e2ed09acdc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28247
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Do not require args.kernel to be set in baremetal.py

This is allowing to us run baremetal.py with the --dtb-gen option
without needing to specify a --kernel argument

Change-Id: I98f1bc865d2f4e2230b1a85453efe83d95ec8a55
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28148
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim, arch-arm: Restore capability of running without a kernel

The following patch:

https://gem5-review.googlesource.com/c/public/gem5/+/24283

Removed the capability of starting a gem5 simulation without
a kernel object. This patch is restoring it

Change-Id: I6d751bac386cbb250b3593bb12463140dc964ab3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28147
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add an abstraction layer for call types in the m5 utility.

These make the calling code in m5.c a little bit more generic. Each call
type will have a function to check the arguments and see if that type is
being requested and/or has any additional options set in the arguments.
If so, those are processed, and argc and argv are adjusted.

Then another function returns the appropriate dispatch table to use for
that invocation scheme. This is behind a function instead of, for
instance, a global variable because it gives the call type a little bit
more control over what's happening, for instance if it would use
different implementations in slightly different circumstances.

Change-Id: I661cf202ec657466496767cbdf331fe27995ab26
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27241
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

util: Add a helpful macro for merging two tokens to m5ops.h.

I've needed this type of macro often when writing code which uses the
M5OP_FOREACH macro, and so rather than re-write it each time, lets just
put a version here. This is such a common type of macro to need that
you'd think it would be part of a standard header somewhere, but to my
knowledge it isn't.

Change-Id: I0df0d9d2fd7ce1b9e6c355d6e4db197ccfff7c35
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27239
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

util: Use a dispatch table to call ops in the m5 utility.

This way different implementations can be substituted in depending on
how the low level ops should actually be triggered (inst, addr,
semihosting, (etc?)).

Change-Id: I7c6eab7d87cc973d0bc9c1889037a0f89ce057e8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27238
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

misc,util: Remove explicit ';'s from M5OP_FOREACH.

It may be the case that each item M5OP_FOREACH iterates over should end
in a ',' and not a ';', for instance when putting each item into an
array or initializing a structure. If the caller still wants a ';', they
can add it into the definition of the M5OP macro.

Change-Id: Idd6538b0aad27df39658c3f749c6ff5e4fe55e6d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27237
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Add the SE mode m5 ops to m5ops.h.

These shouldn't be called in fs mode through the m5 utility and
probably shouldn't be called directly either, but this makes them
consistent with the other functions which are mentioned in
asm/generic/m5ops.h.

Change-Id: I80df8b4d507350bc6d2763e770e38e0370931632
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27236
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim,misc: Rename M5OP_ANNOTATE to M5OP_RESERVED1.

The M5OP_ANNOTATE constant is unused and treated as a reserved op in
gem5. Rename it to make it official and consistent.

Change-Id: Id5fe6a3aa402a2e0cd187503abff9b09e81b3724
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27235
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

misc: Tidy up M5OP_FOREACH and the constants in m5ops.h.

Make sure all the operations that have constants (and aren't deprecated
or reserved) and present in M5OP_FOREACH in order of their constants.
Also move M5OP_ANNOTATE up so that all the constants are also in order.

Change-Id: I8d9f69b020aeb39311a24606a286a76de10a51cc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27234
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Delete the execfile m5 utility command.

This command was just a thin wrapper around the readfile command, and
can be easily duplicated by piping the output of that command to
/tmp/execfile and then running it.

Change-Id: Ib77166ee9f07571d57e4d21e9615def55e5391a8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27233
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

util: Eliminate the sw99param m5 utility command.

This is a small additional layer on top of the initparam command and
just breaks the returned value into 12 bit chunks. It presumes that
there is some particular meaning to the default initparam value which
may or may not be true. It's not entirely clear what the 12 bit chunks
that this command returns are actually good for, and it's been around
long enough that there isn't really any good documentation about what
it's intended purpose was.

Change-Id: I21af0e0cf7501f47026a6dd31920d46cfccff167
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27232
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

util: Improve the usage text of the m5 utility.

Make sure there *is* help text for every command, alphabetize the
commands, explain all the arguments and what the command as a whole
does.

Change-Id: Icf74f8c638545c8658c99169dce728f7b1127806
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27231
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

util: Further simplify the initParam implementation.

Take advantage of string comparisons when looking up what to do with a
given key.

Convert the key_str[12] registers from little endian to host endian.
This matches a corresponding change in the m5 utility to pack the
registers in little endian order, regardless of what the actual guest
endianness is.

Absorb the initparam_keys.hh header into sim/pseudo_inst.cc, and convert
its constants to c++ strings. The constants defined in it might be
useful to guest code calling into the m5 ops, but not for gem5 itself.
By merging them into the .cc file, we also don't have to do any tricks to
try to avoid them having multiple definitions.

Change-Id: I3a450ad7f9c4dca25f79c7835d7f9c167c02ae98
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27230
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

misc: Replace a deprecated method in protoio.cc.

A warning says that ByteSize is now deprecated, and should be replaced
with ByteSizeLong. This change does that.

Change-Id: I0b1aef733c509a73a0af9c39b359d39579d1fd37
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28185
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Refactor the string->register packing function in the m5 utility.

This change removes the responsibility for checking the number of
arguments and handing the default of no string back into init_param and
out of the function which packs strings into registers. It also renames
the function to more closely match its purpose, and rewrites it to be a
bit simpler and (IMHO) easier to follow.

Importantly, rather than doing a hand implemented strcpy which would
follow the endianness of the target/simulated platform, this change
makes this function pack the registers explicitly in little endian byte
order. This way on the consuming end in gem5, the initParam function
doesn't have to care what the guest endianness is, it can just translate
them from little endian to whatever the host endianness is (very likely
also little endian).

Change-Id: Ie9f79ecb8d4584c6e47a2793a31ccaa8c7c15986
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27229
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Simplify collecting the key value in initParam.

If the first register is all zeroes, it doesn't really matter what the
other register is. If the first register has the entire string, we still
don't care what the other register has in it. There's no reason to
complicate the code with these extra checks.

Change-Id: I22ad521b9ace915ccb75f15934fc6b3d650d5293
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27228
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>

util: Correct some help text for the initparam m5 utility command.

The "key" value passed to the initparam command can be at most 16
characters long, but the text said it had to be shorter than 16
characters.

Change-Id: Ic98dc87feb868b44c4210ae16cb5b0dad2a67d88
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27227
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Remove the "pin" command from the m5 utility.

This command did not use any m5 ops, does the same thing as the
"taskset" command under Linux:

https://linux.die.net/man/1/taskset

and might even have introduced a build error if compiled for any other
OS since that would have left a trailing comma in the mainfuncs array.

While the last problem would be easy to correct, this is not related to
the purpose of this utility (giving access to m5 ops), and is redundant
with an existing standard utility provided with Linux.

Change-Id: Ie72b9310f5e6264f6035013f47ebe74a27464abb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27226
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add missing functions to the java wrapper for m5 ops.

Change-Id: I9bdef3cb78cc01b0743ea38eec6f6d28cd2f6765
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27225
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Use a const char * in the m5op m5_add_symbol.

The symbol name is not modified by the m5 op, so a const char * is more
accurate and gives the caller more flexibility as far as what they can
pass in.

Change-Id: Iee567bceef501643175dd5c65551a4c8554a6e3b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27224
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>

util: Update the java wrapper names for m5 ops.

These were regularized a while ago, but not updated in the java wrapper.
There are also missing ops, but these will be added in another change.

Change-Id: Iaef281249c26d446709ba2b214ee37d574f6b72c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27223
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>

misc: Get rid of constants used for critical path annotation.

The constant for the critical path annotation function itself is still
used in gem5 along with the M5OP_RESERVED opcodes to signal
unimplemented functions.

Change-Id: I71c7a56d0346f8aafe23e733a1eea703dda1af92
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27222
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Get rid of the m5op_flags.h header.

This held flags for use with the critical path annotation instructions
which are no longer accessible through the m5 utility and so not used.

Change-Id: Ifee85ce78bb33c4a3e8c0db845974f17d8867199
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27221
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Remove m5a_ (critical path annotation) prototypes from m5ops.h.

This mechanism is still available within gem5 as far as I can tell, but
it's not accessible through the pseudo instruction interface.

Change-Id: I69bd3c92239721a6d1049cee66eb7a0c1bdbc272
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27220
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Convert the other architecture's m5 utility builds to scons.

Because I don't have a canonical toolchain to set SPARC's defaults to,
it will by default build for Linux instead of Solaris like it used to.
This will make it hard to test, but without a compiler there's not much
I can do.

This also coincidentally brings the SPARC version more in line with the
other variants which all target Linux.

Change-Id: Ie19217e988782da124306160920f40ef168840e4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27219
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

arch-arm: Fix Sve Fcmla indexed instruction

Sve implementation of FCMLA indexed instruction was
incorrectly typed. This instruction is design to be used for
half-precision and single precision.

Change-Id: Ie529e21140ce5b26a8e72ac869a5422d32eba864
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28227
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: SVE instructions do not use AHP format

SVE half-precision floating-point instructions support only IEEE
754-2008 half-precision format and ignore the value of the FPCR.AHP bit,
behaving as if it has an Effective value of 0.

This patch is addressing this by masking the FPSCR.AHB bit before
passing it to fplib.

Change-Id: I1432fc3f7fefb81445fe042ae7d681f5cec40e64
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28108
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Do not increment exponent if FPSCR.FZ in fplib

If flushing to zero, the exponent shouldn't be incremented since
we are supposed to produce a 0 value and not a denormal number

Change-Id: Ib6dd594a6555b2fd9a20a52b59cbf1f5f94c2eb5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28107
Reviewed-by: Jordi Vaquero <jordi.vaquero@metempsy.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add some additional flags for files in the m5 util.

When compiling static objects, disable pie with the -no-pie linker flag.
This is necessary for x86, and doesn't seem to hurt anything for the
other variants.

When compiling shared objects, particularly the assembly files which
can't rely on the compiler to generate position independent code, define
M5OP_PIC so that the assembly code can configure itself correctly.

Change-Id: I80d1ea7a7704666027e74228036af5e0e4b9eac2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27218
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc,tests: Updated and generalized the resource url for tests

As we are now going to maintain different bundles of resources for each
gem5 release, the resources have been archived to
http://dist.gem5.org/dist/current for gem5 19. The development branch
will use http://dist.gem5.org/dist/develop going forward. New releases
will follow the format http://dist.gem5.org/dist/{VERSION}.

This patch makes the resources url a command-line parameter, set to the
"correct" url by default. This will be updated to the correct, archived,
version subdirectory upon release of a new gem5 version. E.g.:
http://dist.gem5.org/dist/v20 for the gem5 20 release.

Some Make files have been cleaned up to no longer fetch and push to
remote locations. As gem5-resources is implemented, sources will be
moved to the gem5-resources resository and compiled binaries, etc.
pulled from our Google Cloud bucket from the tests themselves.

Change-Id: Ia16c496be3a60283ecc431ffaa5b059e1932b526
Issue-on: https://gem5.atlassian.net/browse/GEM5-431
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27987
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Removed unneeded Doxygen pages

These removed doxygen files have already been migrated to the gem5
website.

inside-minor.doxygen:
www.gem5.org/documentation/general_docs/cpu_models/minor_cpu

memory_system.doxygen:
www.gem5.org/documentation/general_docs/memory_system/gem5_memory_system

power_thermal_model.doxygen:
www.gem5.org/documentation/general_docs/thermal_model

Issue-on: https://gem5.atlassian.net/browse/GEM5-229
Change-Id: Ib36c364def2dae06a0efbedd3d398763ae7d4e21
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27487
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

tests: Removed "tests/quick"

Tests/resources contained within "tests/quick" have been migrated to the
testlib framework.

Change-Id: I49f2a469905f6fca5a36af433f84a5de4ec5c74f
Issue-on: https://gem5.atlassian.net/browse/GEM5-109
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27727
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

tests: Removed "tests/long"

Tests/resources contained within "tests/long" have been migrated to the
testlib framework.

Change-Id: I014edfac72f5d0df22abf4d4c7a69976b57d785a
Issue-on: https://gem5.atlassian.net/browse/GEM5-109
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27630
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

arch: Fix VecReg container alignement to 128bits view

This Patch will fix the alignment problem that appears sometimes
when we try to create a view of 128 bits over the VecRegContainer
object.

That container is initially created as std::array<uint8_t, SIZE>, so
there is no obligation to be aligned to 16 bytes. This patches forces
all containers to be aligned to 16 bytes.

The problem has been observed in the Jira Issue:
https://gem5.atlassian.net/browse/GEM5-320

Change-Id: Id9fdd427bd7a4dc904edd519f31cc29c5b29c5e6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27968
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Use workloads.py in baremetal.py

Change-Id: I806b771df448241a7a61f496ac22c29d5bc6b84c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27971
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Produce list of workload types in workloads.py

Change-Id: I3f585e006704e671775af8d66d241e555d34cb08
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27970
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Add an example workloads module

This will be a collection of Workload types.
At the moment we provide the following:

* ArmBaremetal: modelling a simple baremetal workload
* ArmTrustedFirmware: modelling the arm trusted firmware workload

Change-Id: Ib46286c03a1c952f981b172c1ea6aa4a6668757e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27969
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: Add hsub instructions to x86

Implemented hsubpd and hsubps instructions from x86.

Issue-on: https://gem5.atlassian.net/browse/GEM5-181
Change-Id: I62919017d3c00119123bda89b2f99cb3bf0b55a8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26123
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Fix Ruby handling of functional requests

This patch addresses multiple cases:

- When a controller has read/write permissions while others have read
  only permissions, the one with r/w permissions performs the read as
  the others may have stale data
- When controllers only have lines with stale or busy access permissions,
  a valid copy of the line may be in a message in transit in the network
  or in a message buffer (not seen by the controller yet). In this case,
  we forward the functional request accordingly.
- Sequencer messages should not accept functional reads
- Functional writes also update the packet data on the sequencer
  outstanding request lists and the cpu-side response queue.

Change-Id: I6b0656f1a2b81d41bdcf6c783dfa522a77393981
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22022
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: John Alsop <johnathan.alsop@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

mem-ruby: SimpleNetwork implementation of functional reads

Change-Id: Id362d992cbf178f15294f0a5e9060a1de2beb394
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22021
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Add functionalReadBuffers to AbstractController

Forwards a functional read accesses to all message buffers, similar to
functionalWriteBuffers.

Change-Id: I54b0ba16aab84575e4c9d6102f6c519b309aa95b
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22020
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

mem-ruby: Allow MessageBuffer functional reads

Valid lines withing unhandled messages may need to be checked when the
line is in a transient state.

Change-Id: I433e9bb960680348c25bf19ace2d405109380241
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22019
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

base,misc: Added version to code

This version ID string can be accessed from elsewhere in the CPP
codebase using `extern const char *gem5Version;`. The python variable
"gem5Version" may be accessed in by importing the generated
"defines.py". When gem5 now runs it will output the version
currently being used to the CLI.

Change-Id: I4feb6b7317cd2922c56eb8ce3e532b0bfa0e6ed3
Issue-on: https://gem5.atlassian.net/browse/GEM5-411
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27787
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base,arch,sim,cpu: Move object file loader components into a namespace.

The components in base/loader were moved into a namespace called
Loader. This will make it easier to add loader components with fairly
short natural names which don't invite name collisions.

gem5 should use namespaces more in general for that reason and to make
it easier to write independent components without having to worry about
name collisions being added in the future.

Unfortunately this namespace has the same name as a class used to load
an object file into a process object. These names can be disambiguated
because the Process loader is inside the Process scope and the Loader
namespace is at global scope, but it's still confusing to read.

Fortunately, this shouldn't last for very long since the responsibility
for loading Processes is going to move to a fake OS object which will
expect to load a particular type of Process, for instance, fake 64 bit
x86 linux will load either 32 or 64 bit x86 processes.

That means that the capability to feed any binary that matches the
current build into gem5 and have gem5 figure out what to do with it
will likely be going away in the future. That's likely for the best,
since it will force users to be more explicit about what they're trying
to do, ie what OS they want to try to load a given binary, and also
will prevent loading two or more Processes which are for different OSes
to the same system, something that's possible today as far as I know
since there are no consistency checks.

Change-Id: Iea0012e98f39f5e20a7c351b78cdff9401f5e326
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24783
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs,arch,sim: Move fixFuncEventAddr into the Workload class.

This is specialized per arch, and the Workload class is the only thing
actually using it. It doesn't make any sense to dispatch those calls
over to the System object, especially since that was, in most cases,
the only reason an ISA specific system class even still existed.

After this change, only ARM still has an architecture specific System
class.

Change-Id: I81b6c4db14b612bff8840157cfc56393370095e2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24287
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch,sim,kern,dev,cpu: Create a Workload SimObject.

This generalized Workload SimObject is not geared towards FS or SE
simulations, although currently it's only used in FS. This gets rid
of the ARM specific highestELIs64 property (from the workload, not the
system) and replaces it with a generic getArch.

The old globally accessible kernel symtab has been replaced with a
symtab accessor which takes a ThreadContext *. The parameter isn't used
for anything for now, but in cases where there might be multiple
symbol tables to choose from (kernel vs. current user space?) the
method will now be able to distinguish which to use. This also makes
it possible for the workload to manage its symbol table with whatever
policy makes sense for it.

That method returns a const SymbolTable * since most of the time the
symbol table doesn't need to be modified. In the one case where an
external entity needs to modify the table, two pseudo instructions,
the table to modify isn't necessarily the one that's currently active.
For instance, the pseudo instruction will likely execute in user space,
but might be intended to add a symbol to the kernel in case something
like a module was loaded.

To support that usage, the workload has a generic "insertSymbol" method
which will insert the symbol in the table that "makes sense". There is
a lot of ambiguity what that means, but it's no less ambiguous than
today where we're only saved by the fact that there is generally only
one active symbol table to worry about.

This change also introduces a KernelWorkload SimObject class which
inherits from Workload and adds in kernel related members for cases
where the kernel is specified in the config and loaded by gem5 itself.
That's the common case, but the base Workload class would be used
directly when, for instance, doing a baremetal simulation or if the
kernel is loaded by software within the simulation as is the case for
SPARC FS.

Because a given architecture specific workload class needs to inherit
from either Workload or KernelWorkload, this change removes the
ability to boot ARM without a kernel. This ability should be restored
in the future.

To make having or not having a kernel more flexible, the kernel
specific members of the KernelWorkload should be factored out into
their own object which can then be attached to a workload through a
(potentially unused) property rather than inheritance.

Change-Id: Idf72615260266d7b4478d20d4035ed5a1e7aa241
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24283
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Add --machine-type option to baremetal.py

Change-Id: Ie5d81b455b86f456a49ba91aa231169be319fa73
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27952
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Add --semi-path option to baremetal.py

This is to make it possible to configure the semihosting
root directory via commandline.

Change-Id: If5167abc19eb8d78db37ebc854c336fe778a8a6f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27951
Tested-by: kokoro <noreply+kokoro@google.com>

dev,cpu: Make two very generic enums ScopedEnums.

Two python Enum parameter types had some very generic elements which
both include one named "none". When headers for both are included that
creates a conflict which breaks the build. Enums which such extremely
generic names need to be scoped so that they don't invite these sorts
of collisions.

This change converts them from Enum to ScopedEnum in python, and also
makes a few small changes to where they're used in c++ to match.

Issue-on: https://gem5.atlassian.net/browse/GEM5-447

Change-Id: Ibda6e6cfcd700a618f8c68d174f33ec1e178b9ac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27950
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Rename the ruby Prefetcher class RubyPrefetcher.

A new Prefetcher namespace was added which holds the gem5 prefetchers
and means they don't all need a "Prefetcher" in their name. Unfortunately
that means that there is now both a Prefetcher namespace and a
Prefetcher class which conflict with each other.

This change tries to resolve the conflict with as little disruption as
possible by simply renaming the c++ ruby Pretcher class RubyPrefetcher,
leaving the python name alone so that configs aren't affected.

Issue-on: https://gem5.atlassian.net/browse/GEM5-447

Change-Id: I7afdf5dbc57dbf46d82552113c52f3a9207870f2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27949
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Use six.input instead of raw_input.

raw_input is not defined in python 3.x and has been replaced by "input".
The "six" compatiblity module defines its own "input" method which
figures out which to use under the covers.

Change-Id: I13a885dd45ec0160c7b46e334b06aae239e3c836
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27948
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Import "sys" which is used in an exception handler.

If the call to "raw_input" fails (it does in python 3.x), then the
"except" runs and will also fail because sys hasn't been imported.

Change-Id: Ibf5778a893a5bd8aad17f4aee544ddcfe5085cab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27947
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Enable semihosting, including pseudo insts.

It is assumed that the semihosting configuration uses the semihosting
number which includes gem5's pseudo insts.

Given the complexity and likely limitted value of letting the user
arbitrarily configure fast model's semihosting, and the fact that that
semihosting implementation would compete with gem5's own, those
parameters should be removed from python and set purely within C++.

Also note that if this semihosting support is used, the System object
needs to have an ArmSemihosting object installed to handle the calls.

Change-Id: I8e1de7717c9784dc7873795acd0a06389ec527b1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25623
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch-sparc: MAP_32BIT does not exist on solaris

Judging by the mmap documentation for solaris:

https://docs.oracle.com/cd/E88353_01/html/E37841/mmap-2.html

MAP_32BIT is not defined. Instead it is using a MAP_LOW32 field
which is explicitly described as different from the MAP_32BIT
field in Linux distributions.

The patch is removing the mapping since:

* As mentioned solaris doesn't implement MAP_32BIT (Target)
* Not every host supports MAP_32BIT.
    ** http://man7.org/linux/man-pages/man2/mmap.2.html

In fact, assuming a Linux host, MAP_32BIT is defined for
x86-64 only, which means it is not possible to compile
gem5-SPARC on a (e.g.) Arm host.

Change-Id: Ibf234754941ae915e728db5fbc4ba1db3aaa1c81
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27647
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Use off_t for mmap offset arguments

The GuestABI used to call the system-calls infers the size of values
read from the registers based on the function signature of the system
call. For mmap this was causing offset to be truncated to a 32-bit
value. In the GPUComputeDriver mmap, the offset must be a 64-bit
value. This fixes a bug where the doorbell memory was not setup and
causing GPU applications to fail.

Change-Id: I75d9b32c0470d1907c68826ef81cf6cd46f60ea7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27367
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

mem-cache: Create Prefetcher namespace

Create a namespace for the Prefetcher classes.

As a side effect the Prefetcher suffix has been removed from the
C++'s classes names, and the memory leaking destructor overrides
have been fixed.

Change-Id: I9bae492d2fd4734bcdfb68c164345898e65102b2
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24537
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-se: add missing path redirection to mmap createObjectFile

The redirection call was mistakenly removed at:
Ide158e69cdff19bc81157e3e9826bcabc2a51140 and that breaks running
cross compiled dynamically linked executables in SE.

JIRA: https://gem5.atlassian.net/browse/GEM5-430

Change-Id: I33419c78fbf183cda0bba98f7035a2b25ebc6fa3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27887
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

configs: make --disk-images optional in fs.py

The main applications are to run baremetal programs and initramfs Linux
kernel.

Before this patch, disks() calls in makeArmSystem would throw:

IOError: Can't find file 'linux-aarch32-ael.img' on M5_PATH.

In order to achieve this, this commit also removes the default hardcoded
disk image basenames.

For example, before this commit, running without a --disk-image in X86
would automatically search for an image with basename x86root.img in
M5_PATH, which means we would either have to ignore any disk image error,
or else running without disk images would fail.

After this commit, you would have to pass --disk-image x86root.img to
achieve the old behaviour.

Change-Id: I0ae8c4b3b93d0074fd4fca0d5ed52181c50b6c04
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27867
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

sparc,configs: Initialize ROMs directly, not with the workload.

This simplifies the SPARC FS workload significantly, and removes
assumptions about what ROMs exist, where they go, etc. It removes
other components from the loop which don't have anything to contribute
as far as setting up the ROMs.

One side effect of this is that there isn't specialized support for
adding PC based events which would fire in the ROMs, but that was never
done and the files that were being used were flat binary blobs with no
symbols in the first place.

This also necessitates building a unified image which goes into the single
8MB ROM that is located at address 0xfff0000000. That is simply done
with the following commands:

dd if=/dev/zero of=t1000_rom.bin bs=1024 count=8192
dd if=reset_new.bin of=t1000_rom.bin
dd if=q_new.bin of=t1000_rom.bin bs=1024 seek=64
dd if=openboot_new.bin of=t1000_rom.bin bs=1024 seek=512

This results in an 8MB blob which can be loaded verbatim into the ROM.
Alternatively, and with some extra effort, an ELF file could be
constructed which had each of these components as segments, offset to the
right location in the ELF header. That would be slightly more work to set up,
but wouldn't waste space on regions of the image that are all zeroes.

Change-Id: Id4e08f4e047e7bd36a416c197a36be841eba4a15
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27268
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>

mem: Support initializing a memory with an image file.

This is particularly useful for ROMs. It avoids forcing other components
of the simulation (the System object, the Workload object) from having
to know what ROMs exist, where they are, and what goes on them, and
leaves that to the config script.

Change-Id: Ibbcffffcb82e0d289f0b3942728c30b8f69d28ba
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27267
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add config files for crosstool-ng toolchains.

There is one for each arch gem5 supports, except RISCV which is not
supported by crosstool-ng at the moment. All configs are for Linux, also
because that's what crosstool-ng tends to support.

Change-Id: I898a9e8c7b144c3d690c232fd4fb20ede5430def
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27758
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch-x86: Change insertBits in TLB translateFunctional

x86 TLB::translateFunctional inserts one too many bits from the virtual
address leading to an incorrect physical address occasionally.

Change-Id: I2cc551c496f7ce729ea440ef01a680c0de257269
JIRA: https://gem5.atlassian.net/browse/GEM5-442
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27827
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util,scons: Generalize the aarch64 scons for the m5 util.

Slightly parameterize it so it can be used with the other versions of
the utility.

All build products for a given variant will now go under
build/${VARIANT}. The primary build outputs will go under
build/${VARIANT}/out so that they're easy to distinguish.

Change-Id: Idd244cc2a6c08ec8e4d67de3d0bae604c0611220
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27217
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Run realview(64) tests with VExpress_GEM5_Foundation

This patch is updating the arm regression configs so that the newer
VExpress_GEM5_Foundation platform is used instead VExpress_GEM5_V1
for running regressions.
The platform has the same memory map as V1, except for a different
position of PCI regions in the memory map and more importantly
the use of GICv3 instead of GICv2

Change-Id: I48ff56dce38d482be7f1acf162f17725286f54fe
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27714
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>

arch-arm: Override ISA::takeOverFrom for the Arm ISA

This is fixing switcheroo tests when using a PMU/GICv3.  When you switch
cpus you usually instantiate multiple cpus at the beginning and you
switch them at runtime with the m5.switchCpus function.

Every cpu will have its own set of ThreadContexts/ISAs.
When you switch cpu/tc/isa, you need to update the tc/isa pointer
cached in the device model otherwise those will still reference
the switched out cpu.

Change-Id: I3aeee890286851189c3a8a4d378c83f32e973361
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27713
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch, cpu: Add a takeOverFrom method for switching ISAs

This will be used by architectures to handle the m5.switchCpus at the
ISA level since some ISA specific fields might need to be aware of the
TC change.

Change-Id: If8d50c5c80bc3458d5f1d14cf93ae107314c98cf
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27712
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Remove unnecessary haveGICv3CPUInterface

This is not needed since the ISA class could just check if
the gicv3CpuInterface ptr is different than nullptr

Change-Id: I6d562a5d9ff2568774b6958f03f04d878266ca8f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27711
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: In build_cross_gcc, set LIMITS_H_TEST=true.

This forces a test in the gcc Makefile to pick the right answer, where
its own check will not. Without this fix, installing libsanitizer fails
to build while installing the c++ headers because it can't find a
definition for PATH_MAX. Disabling building libsanitizer seems to work
around the problem, but other problems crop up later when using the
cross compiler, specifically when trying to build the googletest
library.

The chrome authors apparently ran into a similar problem when building
the native client tool chain as described in this bug:

https://bugs.chromium.org/p/nativeclient/issues/detail?id=3190

The CL which fixed the issue is here:

https://codereview.chromium.org/11462002/patch/1/2.

With a similar fix applied to build_cross_gcc.py, the cross compilers
build without issue, and are then able to build the googletest library
without issue.

Change-Id: Ia6869d3dc523cb0d964e82bb300f8b092693739b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27489
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

tests: Fail checkpoint regressions if no cpt has been taken

This is to avoid the scenario where a wrong interval is chosen
and no checkpoint is taken.

Change-Id: I524d797048ab04799555aaf7a051241b2917ad95
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27710
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>

tests: Reduce checkpoint interval used by realview regressions

With the current interval, the realview(64)-simple-atomic-checkpoint
regressions are not actually checkpointing since they finish boot
(and hit m5 exit) before creating the first checkpoint.

Change-Id: I297864ccb7ec8a818c9eccd94406b69d89d1f8d3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27709
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Fix checkpointing for the GenericTimer

The revamp of the GenericTimer was not taking into account:

* The name of the variable will be printed on the checkpoint to label the
data. It is not possible to use different variable names when
serializing/unserializing, and it is not possible to use the same
temporary variable to serialize/unserialize different values.

* the serializeSection is creating a new sub section in the
checkpoint. Doing the following:

void
GenericTimerFrame::serialize(CheckpointOut &cp) const
{
    physTimer.serializeSection(cp, "phys_timer");
    virtTimer.serializeSection(cp, "virt_timer");
    SERIALIZE_SCALAR(accessBits);
}

will serialize the accessBits under the virt_timer subsection
rather than the parent generic_timer_frame.

JIRA: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-426

Change-Id: I7676309965a33156789d2ef13e966c7a4ad88a71
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27708
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Handle empty object_file scenario in ArmFsWorkload

At the moment it is actually possible to pass en empty object file
to the ArmFsWorkload (OsKernel) class. We need to handle this
situation as well.
In case no bootloader nor object file is passed, we default to
AArch64 (default value for ArmFsWorkload)

Change-Id: I3b4aa8b8d61a8fac08da218125984b3bb1d38fb9
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27707
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>

util: Move m5op_arm_A64.S into an aarch64 subdirectory.

Also rename it to m5op.S. These files will be distinguished by what
directory they're in, rather than by their name.

Change-Id: I3a89d529bb5b760579df22234cf9bf870711b56e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27216
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Delete the aarch64 Makefile for the m5 utility.

Change-Id: I202f2b0986ef12ddb076045673d80405b1afb54a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27215
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util,scons: Detect java and lua51 in the m5 utility scons files.

These will enable or disable the java and lua51 m5 op wrappers depending
on whether the required tools are available on the host system.

Change-Id: I2b11a13a39b2dfd5d45a9ed57702d2e225ef7d2e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27214
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

util: Add SCons build files for the aarch64 verson of the m5 utility.

These are currently specific to aarch64, but will be expanded to cover
all other versions of the utility as well.

The intention of these new files is to centralize the build mechanism
for the different versions of the utility so that they have consistent
features, mechanisms, and targets, and so that new features will
automatically be shared by all versions without having to be implemented
in each.

This also sets up a separate build directory which will keep the source
tree clean, and will (with some more development) make it possible to
build multiple versions of the m5 utility at the same time without them
running into each other.

Change-Id: I10018eef6beb4af30a8d3bbab8b82cabd2b3f22c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27213
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: Do not fixup faults in TLB

Faults in the TLB ought to cause a page walk. Force that by removing
the fixup in X86 TLB.

This fixes rare race conditions where a timing page walk is
intercepted by a TLB miss which fixes up the fault resulting in
double calls to allocateMem in Process class.

Change-Id: Iaef4d636cd2997144d8bc5012cd7c2a0a97102e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27507
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

mem: Modify DRAM controller for flexibility and new memories

This change includes:
1) Verify available command bandwidth
2) Add support for multi-cycle commands
3) Add new timing parameters
4) Add ability to interleave bursts
5) Add LPDDR5 configurations

The DRAM controller historically does not verify contention on the
command bus and if there is adaquate command bandwidth to issue a
new command. As memory technologies evolve, multiple cycles are becoming
a requirement for some commands.  Depending on the burst length, this
can stress the command bandwidth. A check was added to verify command
issue does not exceed a maximum value within a defined window. The
default window is a burst, with the maximum value defined based on the
burst length and media clocking characteristics. When the command bandwidth
is exceeded, commands will be shifted to subsequent burst windows.

Added support for multi-cycle commands, specifically Activate, which
requires a larger address width as capacities grow.  Additionally,
added support for multi-cycle Read / Write bursts for low power
DRAM cases in which additional CLK synchronization may be required
to run at higher speeds.

To support emerging memories, added the following new timing parameters.
1) tPPD -- Precharge-to-Precharge delay
2) tAAD -- Max delay between Activate-1 and Activate-2 commands

I/O data rates are continuing to increase for DRAM but the core frequency
is still fairly stagnant for many technologies. As we increase the burst
length, either the core prefetch needs to increase (for a seamless burst)
or the burst will be transferred with gaps on the data bus. To support
the latter case, added the ability to interleave 2 bursts across bank
groups.

Using the changes above, added an initial set of LPDDR5 configurations.

Change-Id: I1b14fed221350e6e403f7cbf089fe6c7f033c181
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26236
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Add VExpress_GEM5_Foundation platform

A new VExpress_GEM5_Foundation platform has been added in order to match
the FVP Armv8-A Foundation Platform described in:

Armv8-A Foundation Platform - User Guide - Version 11.8

The VExpress_GEM5_V1/V2 are already loosely based on the Foundation
platform, however there are some differences in the PCI regions (V1/V2)
and the GICv3 regions (V2).
We hence introduce the VExpress_GEM5_Foundation to match closely the
FVP Foundation Platform

Change-Id: I1604c64ce566308d888c3a630019494b9fae7acf
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27388
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>

configs: add option for memory channel intlv.

Current memory channel interleave is hard-coded to be maximum between 128
and system's cache line size. Making this value configurable enables use
cases with DMA masters accessing at higher than 128 block granularity.

Change-Id: I8123fa307efd3fd8f16c815ee74a84844bb51edb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27629
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

util: Implement PIC assembly for the aarch64.

When accessing m5_mem and building PIC code, we need to get the address
of m5_mem out of the global offset table, and then load the value from
there. If we try to load from m5_mem directly, the assembled code has a
relocation type the linker can't handle when building a shared object.

Change-Id: Ieb19c3d17c37ef810559ee24b68886b18ddcc869
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27212
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Replace SLICC queueMemory calls with enqueue

Calls to queueMemoryRead and queueMemoryWrite do not consider the size
of the queue between ruby directories and DRAMCtrl which causes infinite
buffering in the queued port between the two. This adds a MessageBuffer
in between which uses enqueues in SLICC and is therefore size checked
before any SLICC transaction pushing to the buffer can occur, removing
the infinite buffering between the two.

Change-Id: Iedb9070844e4f6c8532a9c914d126105ec98d0bc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27427
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>

arch-arm, dev-arm: Autogen PSCI node in DTB

This is controlled via the python only _have_psci parameter
This flag will be checked when auto-generarting a PSCI node. A client
(e.g Linux) would then be able to know if it can use the PSCI APIs

Change-Id: I16c4a67bd358eca3dfff6c98ab8a602a31e1c751
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27387
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: CNTHCTL trap to EL2 only if ARMv8.6-ECV implemented

In condGenericTimerCommonEL1SystemAccessTrapEL2 we were trapping
accesses to the EL1 virtual timer/counter registers to EL2, not
considering that this feature is part of ARMv8.6-ECV only
(not supported at the moment)

Change-Id: Ic03bcae436a105fb139a74126881b665ee08c912
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27408
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>