mesa.git
4 years agopanfrost: Fill in SCALED formats to format table
Alyssa Rosenzweig [Tue, 19 May 2020 21:25:14 +0000 (17:25 -0400)]
panfrost: Fill in SCALED formats to format table

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>

4 years agopanfrost: Remove deadcode
Alyssa Rosenzweig [Tue, 19 May 2020 21:12:13 +0000 (17:12 -0400)]
panfrost: Remove deadcode

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>

4 years agopanfrost: Keep cached BOs mmap'd
Alyssa Rosenzweig [Tue, 19 May 2020 19:06:52 +0000 (15:06 -0400)]
panfrost: Keep cached BOs mmap'd

It doesn't make sense to munmap/mmap repeatedly; they're mapped GPU-side
anyway. So just munmap on free, which will happen in low-mem regardless.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5124>

4 years agopanfrost: Guard experimental fp16 behind debug flag
Alyssa Rosenzweig [Wed, 6 May 2020 23:48:05 +0000 (19:48 -0400)]
panfrost: Guard experimental fp16 behind debug flag

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Pack 8-bit swizzles in 16-bit ops
Alyssa Rosenzweig [Wed, 13 May 2020 22:24:25 +0000 (18:24 -0400)]
pan/mdg: Pack 8-bit swizzles in 16-bit ops

Let's inch closer to 8-bit.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Implement condense_writemask for 8-bit
Alyssa Rosenzweig [Thu, 14 May 2020 17:29:54 +0000 (13:29 -0400)]
pan/mdg: Implement condense_writemask for 8-bit

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Implement vector constant printing for 8-bit
Alyssa Rosenzweig [Thu, 14 May 2020 17:30:05 +0000 (13:30 -0400)]
pan/mdg: Implement vector constant printing for 8-bit

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Use shifts instead of division for RA sizes
Alyssa Rosenzweig [Wed, 20 May 2020 20:14:17 +0000 (16:14 -0400)]
pan/mdg: Use shifts instead of division for RA sizes

We're only dealing with powers-of-two, so this eliminates potential
issues with divisions-by-zero that are otherwise hacked around. Probably
faster too.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Pack barriers correctly
Alyssa Rosenzweig [Wed, 13 May 2020 15:05:49 +0000 (11:05 -0400)]
pan/mdg: Pack barriers correctly

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Fix type checking issues with compute
Alyssa Rosenzweig [Wed, 13 May 2020 15:05:34 +0000 (11:05 -0400)]
pan/mdg: Fix type checking issues with compute

SSBO and barriers.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Separately pack constants to the upper half
Alyssa Rosenzweig [Mon, 11 May 2020 20:05:48 +0000 (16:05 -0400)]
pan/mdg: Separately pack constants to the upper half

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Only combine 16-bit constants to lower half
Alyssa Rosenzweig [Mon, 11 May 2020 19:58:58 +0000 (15:58 -0400)]
pan/mdg: Only combine 16-bit constants to lower half

We can't swizzle both halves simultaneously.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Factor out mir_adjust_constant
Alyssa Rosenzweig [Mon, 11 May 2020 19:52:18 +0000 (15:52 -0400)]
pan/mdg: Factor out mir_adjust_constant

Each source is semi-independent, we don't need the extra indentation
when the logic is already so complex.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Print constant vectors less wrong
Alyssa Rosenzweig [Mon, 11 May 2020 19:33:43 +0000 (15:33 -0400)]
pan/mdg: Print constant vectors less wrong

For !32-bit types, we need to pay attention to rep_low/high/half to
determine the effective swizzle.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Round up bytemasks when spilling
Alyssa Rosenzweig [Mon, 11 May 2020 17:49:03 +0000 (13:49 -0400)]
pan/mdg: Round up bytemasks when spilling

So we can pack the spills for <32-bit types.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Print mask when dest=0
Alyssa Rosenzweig [Mon, 11 May 2020 16:56:43 +0000 (12:56 -0400)]
pan/mdg: Print mask when dest=0

Forgot this convention differs from Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Set RA bounds for fp16
Alyssa Rosenzweig [Mon, 11 May 2020 19:07:25 +0000 (15:07 -0400)]
pan/mdg: Set RA bounds for fp16

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Eliminate load_64
Alyssa Rosenzweig [Mon, 11 May 2020 19:06:53 +0000 (15:06 -0400)]
pan/mdg: Eliminate load_64

It can always be inferred from the types.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Use type size to determine alignment
Alyssa Rosenzweig [Mon, 11 May 2020 19:05:27 +0000 (15:05 -0400)]
pan/mdg: Use type size to determine alignment

Generally, f16 needs to be aligned to 16-bit, f32 to 32-bit, ...

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/lcra: Allow per-variable bounds to be set
Alyssa Rosenzweig [Mon, 11 May 2020 19:03:58 +0000 (15:03 -0400)]
pan/lcra: Allow per-variable bounds to be set

Different variables need to respect different bounds. In general,
16-bytes is okay, but for 4-channel 16-bit vectors, we can't cross 8
byte boundaries (else the swizzles will not be packable after), so we
update LCRA to allow this more general form.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/lcra: Remove unused alignment parameters
Alyssa Rosenzweig [Wed, 6 May 2020 22:17:02 +0000 (18:17 -0400)]
pan/lcra: Remove unused alignment parameters

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Ignore dest.type when offseting load swizzle
Alyssa Rosenzweig [Mon, 11 May 2020 19:02:10 +0000 (15:02 -0400)]
pan/mdg: Ignore dest.type when offseting load swizzle

It's always as-if 32-bit.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Don't generate conversions for fp16 LUTs
Alyssa Rosenzweig [Thu, 7 May 2020 19:43:21 +0000 (15:43 -0400)]
pan/mdg: Don't generate conversions for fp16 LUTs

We can just set the register mode appropriately and then we don't have
to care anywhere else, and there's no extra NIR to chew through. Make
sure we include sqrt too.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Implement b2f16
Alyssa Rosenzweig [Fri, 8 May 2020 21:42:40 +0000 (17:42 -0400)]
pan/mdg: Implement b2f16

...as iand

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Streamline dest_override handling
Alyssa Rosenzweig [Fri, 8 May 2020 21:41:49 +0000 (17:41 -0400)]
pan/mdg: Streamline dest_override handling

We can pass it all off to emit time, and let the types in the IR do the
heavylifting in the meantime, which is a lot easier to get right.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Remove redundant redundancy
Alyssa Rosenzweig [Thu, 7 May 2020 23:11:38 +0000 (19:11 -0400)]
pan/mdg: Remove redundant redundancy

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Defer modifier packing until emit time
Alyssa Rosenzweig [Thu, 21 May 2020 16:38:27 +0000 (12:38 -0400)]
pan/mdg: Defer modifier packing until emit time

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Remove promote_float pass
Alyssa Rosenzweig [Thu, 21 May 2020 16:32:20 +0000 (12:32 -0400)]
pan/mdg: Remove promote_float pass

Now unused.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Promote imov to fmov on a NIR level
Alyssa Rosenzweig [Thu, 21 May 2020 16:31:40 +0000 (12:31 -0400)]
pan/mdg: Promote imov to fmov on a NIR level

Avoids dedicated MIR promote_fmov pass which is unnecessary.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Identify scalar integer mods
Alyssa Rosenzweig [Thu, 21 May 2020 16:24:42 +0000 (12:24 -0400)]
pan/mdg: Identify scalar integer mods

Symmetric with vector mods, except for normal which is packed as
sign-extend. (flag 2 never seen in the wild)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Use type to determine triviality of a move
Alyssa Rosenzweig [Thu, 21 May 2020 16:19:56 +0000 (12:19 -0400)]
pan/mdg: Use type to determine triviality of a move

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Use src_types to determine size in scheduling
Alyssa Rosenzweig [Thu, 21 May 2020 16:16:48 +0000 (12:16 -0400)]
pan/mdg: Use src_types to determine size in scheduling

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Add abs/neg/shift modifiers to IR
Alyssa Rosenzweig [Thu, 21 May 2020 16:15:09 +0000 (12:15 -0400)]
pan/mdg: Add abs/neg/shift modifiers to IR

Rather than twiddling them into the ALU packed field.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Explain ld/st sign/zero extension
Alyssa Rosenzweig [Thu, 21 May 2020 16:13:38 +0000 (12:13 -0400)]
pan/mdg: Explain ld/st sign/zero extension

Now we know why there are duplicates :-)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Respect !32-bit sizes in RA
Alyssa Rosenzweig [Thu, 7 May 2020 20:10:09 +0000 (16:10 -0400)]
pan/mdg: Respect !32-bit sizes in RA

So we can take advantage of mediump.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Handle dest up/lower correctly with swizzles
Alyssa Rosenzweig [Thu, 7 May 2020 20:09:47 +0000 (16:09 -0400)]
pan/mdg: Handle dest up/lower correctly with swizzles

During emit time.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Include more types
Alyssa Rosenzweig [Thu, 7 May 2020 17:43:13 +0000 (13:43 -0400)]
pan/mdg: Include more types

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Remove mir_get_alu_src
Alyssa Rosenzweig [Thu, 7 May 2020 17:06:26 +0000 (13:06 -0400)]
pan/mdg: Remove mir_get_alu_src

Unused.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Remove mir_*size routines
Alyssa Rosenzweig [Thu, 7 May 2020 14:12:38 +0000 (10:12 -0400)]
pan/mdg: Remove mir_*size routines

We'd rather use the actual type information than inferring modes all
over the place.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Fix constant combining crash
Alyssa Rosenzweig [Thu, 7 May 2020 14:13:35 +0000 (10:13 -0400)]
pan/mdg: Fix constant combining crash

We need to round up.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agopan/mdg: Handle comparisons in fp16 path
Alyssa Rosenzweig [Thu, 7 May 2020 14:12:24 +0000 (10:12 -0400)]
pan/mdg: Handle comparisons in fp16 path

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>

4 years agoaco: sign-extend the input and identity for 8-bit subgroup operations
Samuel Pitoiset [Wed, 20 May 2020 09:32:50 +0000 (11:32 +0200)]
aco: sign-extend the input and identity for 8-bit subgroup operations

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>

4 years agoaco: use a temporary SGPR for 8-bit/16-bit literal reduction identities
Samuel Pitoiset [Mon, 18 May 2020 14:00:10 +0000 (16:00 +0200)]
aco: use a temporary SGPR for 8-bit/16-bit literal reduction identities

Otherwise, the compiler overwrites s0 which contains the exec mask.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>

4 years agoaco: implement 8-bit/16-bit nir_intrinsic_quad_*
Samuel Pitoiset [Wed, 8 Apr 2020 07:30:47 +0000 (09:30 +0200)]
aco: implement 8-bit/16-bit nir_intrinsic_quad_*

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>

4 years agoaco: implement 8-bit/16-bit nir_intrinsic_{shuffle,_read_invocation}
Samuel Pitoiset [Wed, 8 Apr 2020 07:24:36 +0000 (09:24 +0200)]
aco: implement 8-bit/16-bit nir_intrinsic_{shuffle,_read_invocation}

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>

4 years agoaco: implement 8-bit/16-bit nir_intrinsic_read_first_invocation
Samuel Pitoiset [Wed, 8 Apr 2020 07:17:38 +0000 (09:17 +0200)]
aco: implement 8-bit/16-bit nir_intrinsic_read_first_invocation

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>

4 years agoaco: validate 8-bit/16-bit VGPR operands for readfirstlane/readlane/writelane
Samuel Pitoiset [Wed, 8 Apr 2020 06:53:47 +0000 (08:53 +0200)]
aco: validate 8-bit/16-bit VGPR operands for readfirstlane/readlane/writelane

I would expect it to just work as intended and other solutions,
like v_and_b32 to make sure the upper bits are 0, might have some
overhead.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>

4 years agoaco: implement 8-bit/16-bit reductions
Samuel Pitoiset [Wed, 8 Apr 2020 06:39:28 +0000 (08:39 +0200)]
aco: implement 8-bit/16-bit reductions

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>

4 years agoaco: declare 8-bit/16-bit reduce operations
Samuel Pitoiset [Wed, 8 Apr 2020 06:39:08 +0000 (08:39 +0200)]
aco: declare 8-bit/16-bit reduce operations

The 8-bit float variants are only for consistency but are unused.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4494>

4 years agono_extern_c.h: fix typo in comment
Eric Engestrom [Tue, 7 Apr 2020 13:38:30 +0000 (15:38 +0200)]
no_extern_c.h: fix typo in comment

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5145>

4 years agodocs: fix broken release-calendar
Erik Faye-Lund [Thu, 21 May 2020 12:19:56 +0000 (14:19 +0200)]
docs: fix broken release-calendar

This also removed the branch-row, which is needed to keep things sane.

Fixes: 34718070ef8 ("docs: update calendar for 20.1.0-rc4")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5143>

4 years agoaco: fix typo in insert_waitcnt's kill()
Rhys Perry [Wed, 20 May 2020 17:15:36 +0000 (18:15 +0100)]
aco: fix typo in insert_waitcnt's kill()

No shader-db changes

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3004
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5126>

4 years agoaco: don't allow unaligned subdword accesses on GFX6/7
Daniel Schürmann [Wed, 6 May 2020 10:00:24 +0000 (11:00 +0100)]
aco: don't allow unaligned subdword accesses on GFX6/7

There are no SDWA instructions which means that only
full registers can be accessed.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5070>

4 years agoaco: fix corner case in register allocation
Daniel Schürmann [Sat, 16 May 2020 16:14:30 +0000 (17:14 +0100)]
aco: fix corner case in register allocation

We mark dead operands in the register file when searching for
a register for a definition. Only do so, if this space has not
yet been taken by a different definition.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5070>

4 years agoaco: don't move create_vector subdword operands to unsupported register offsets
Daniel Schürmann [Fri, 8 May 2020 15:18:15 +0000 (16:18 +0100)]
aco: don't move create_vector subdword operands to unsupported register offsets

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5070>

4 years agoaco: restrict copying of create_vector operands to GFX9+
Daniel Schürmann [Fri, 8 May 2020 14:52:47 +0000 (15:52 +0100)]
aco: restrict copying of create_vector operands to GFX9+

This improves code size for Polaris and earlier due to less register swapping

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5070>

4 years agoclover: Address unnecessary copy warnings
Pierre Moreau [Thu, 7 May 2020 08:38:48 +0000 (10:38 +0200)]
clover: Address unnecessary copy warnings

Signed-off-by: Pierre Moreau <dev@pmoreau.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4943>

4 years agoclover/api: Address missing braces for subobj init
Pierre Moreau [Thu, 7 May 2020 08:38:35 +0000 (10:38 +0200)]
clover/api: Address missing braces for subobj init

Signed-off-by: Pierre Moreau <dev@pmoreau.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4943>

4 years agomeson: Disable GCC's dead store elimination for memory zeroing custom new
Danylo Piliaiev [Tue, 19 May 2020 17:35:49 +0000 (20:35 +0300)]
meson: Disable GCC's dead store elimination for memory zeroing custom new

Some classes use custom new operator which zeroes memory, however gcc does
aggressive dead-store elimination which threats all writes to the memory
before the constructor as "dead stores".

For now we disable this optimization.

The new operators in question are declared via:
 DECLARE_RZALLOC_CXX_OPERATORS
 DECLARE_LINEAR_ZALLOC_CXX_OPERATORS

The issue was found with lto builds, however there is no guarantee that
it didn't happen with ordinary ones.

CC: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2977
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/1358
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5104>

4 years agoradv/winsys: remove useless free in radv_amdgpu_create_bo_list()
Samuel Pitoiset [Wed, 20 May 2020 18:04:34 +0000 (20:04 +0200)]
radv/winsys: remove useless free in radv_amdgpu_create_bo_list()

free(NULL) is fine but let's remove it.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3008
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5131>

4 years agoradv: fix duplicated expression in ac_setup_rings()
Samuel Pitoiset [Wed, 20 May 2020 17:59:50 +0000 (19:59 +0200)]
radv: fix duplicated expression in ac_setup_rings()

Probably a search&replace mistake when that common struct was
introduced.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3006
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5130>

4 years agoradv: fix missing break in radv_GetPhysicalDeviceFeatures2()
Samuel Pitoiset [Wed, 20 May 2020 17:52:34 +0000 (19:52 +0200)]
radv: fix missing break in radv_GetPhysicalDeviceFeatures2()

Wow, missed that one.

Fixes: 57e796a12a8 - ("radv: Implement VK_EXT_custom_border_color")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5128>

4 years agoaco: fix missing break in label_instruction()
Samuel Pitoiset [Wed, 20 May 2020 17:55:56 +0000 (19:55 +0200)]
aco: fix missing break in label_instruction()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5129>

4 years agollvmpipe: compute shaders work better with all the threads.
Dave Airlie [Thu, 21 May 2020 03:38:03 +0000 (13:38 +1000)]
llvmpipe: compute shaders work better with all the threads.

I got to benchmarking some vulkan compute benchmark and wondered
why my CPUs weren't being saturated, helps if you actually wake up
all the threads in the threadpool.

Fixes: 1b24e3ba756b (llvmpipe: add compute threadpool + mutex)
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5138>

4 years agodri_util: Update internal_format to GL_RGB8 for MESA_FORMAT_R8G8B8X8_UNORM
Nataraj Deshpande [Wed, 13 May 2020 21:32:13 +0000 (14:32 -0700)]
dri_util: Update internal_format to GL_RGB8 for MESA_FORMAT_R8G8B8X8_UNORM

The commit helps to resolve GL_INVALID_OPERATION error returned
during CTS test when Android format RGBX8888 fallback to RGBA8888
and then set color with glTexSubImage2D(format=GL_RGB).

Fixes android.hardware.nativehardware.cts.AHardwareBufferNativeTests:
 #SingleLayer_ColorTest_GpuSampledImageCanBeSampled_R8G8B8X8_UNORM

Cc: <mesa-stable@lists.freedesktop.org>
Fixes: bf576772ab4d ("dri_util: add driImageFormatToSizedInternalGLFormat function")
Signed-off-by: Nataraj Deshpande <nataraj.deshpande@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5034>

4 years agofreedreno/a6xx: Avoid stalling for occlusion queries
Kristian H. Kristensen [Fri, 15 May 2020 19:23:18 +0000 (12:23 -0700)]
freedreno/a6xx: Avoid stalling for occlusion queries

If we postpone computing the counter delta until after each tile (or
sysmem pass), we don't have to stall in the middle of the draw stream.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5064>

4 years agofreedreno/a6xx: Emit VFD setup as array writes
Kristian H. Kristensen [Fri, 15 May 2020 22:11:55 +0000 (15:11 -0700)]
freedreno/a6xx: Emit VFD setup as array writes

We can use only one PKT4 for each of VFD_FETCH, VFD_DECODE and
VFD_DEST_CNTL and write all the elements if we split the loop into
three loops.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5064>

4 years agofreedreno/a6xx: Allocate ringbuffer based on VFD count
Kristian H. Kristensen [Fri, 15 May 2020 21:52:01 +0000 (14:52 -0700)]
freedreno/a6xx: Allocate ringbuffer based on VFD count

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5064>

4 years agofreedreno/a6xx: Map inputs to VFD entries up front
Kristian H. Kristensen [Fri, 15 May 2020 20:55:07 +0000 (13:55 -0700)]
freedreno/a6xx: Map inputs to VFD entries up front

Break this logic out of the loop in preperation for splitting the VFD
state emit loop up.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5064>

4 years agofreedreno/a6xx: Create shader dependent streamout state at compile time
Kristian H. Kristensen [Fri, 15 May 2020 20:07:38 +0000 (13:07 -0700)]
freedreno/a6xx: Create shader dependent streamout state at compile time

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5064>

4 years agocompiler: delete leftover autotools test wrapper
Eric Engestrom [Tue, 19 May 2020 23:35:03 +0000 (01:35 +0200)]
compiler: delete leftover autotools test wrapper

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5114>

4 years agogit_sha1_gen.py: fix whitespace
Eric Engestrom [Tue, 19 May 2020 23:23:35 +0000 (01:23 +0200)]
git_sha1_gen.py: fix whitespace

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5112>

4 years agogit_sha1_gen.py: fix code style
Eric Engestrom [Tue, 19 May 2020 23:22:42 +0000 (01:22 +0200)]
git_sha1_gen.py: fix code style

Bare `except` are bad form as per PEP8.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5112>

4 years agogit_sha1_gen.py: fix out-of-date comment
Eric Engestrom [Tue, 19 May 2020 23:22:01 +0000 (01:22 +0200)]
git_sha1_gen.py: fix out-of-date comment

This hasn't been true since 7088622e5fb506b64c90 ("buildsys: move file
regeneration logic to the script itself") almost 3 years ago.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5112>

4 years agoanv: disable VK_EXT_calibrated_timestamps when the timestamp register is unreadable
Eric Engestrom [Wed, 15 May 2019 10:30:36 +0000 (11:30 +0100)]
anv: disable VK_EXT_calibrated_timestamps when the timestamp register is unreadable

When running in a virtual context, the timestamp register is unreadable
on Gen12+.
While we could work around this, that would result in very inaccurate
results for an extension where the whole point is accuracy, so let's
just disable the extension.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2797>

4 years agoanv: replace magic `| 1` with already #define'd name
Eric Engestrom [Tue, 21 May 2019 17:05:34 +0000 (18:05 +0100)]
anv: replace magic `| 1` with already #define'd name

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2797>

4 years agoanv: pass the fd directly to anv_gem_reg_read()
Eric Engestrom [Wed, 15 May 2019 10:20:06 +0000 (11:20 +0100)]
anv: pass the fd directly to anv_gem_reg_read()

This allows its use without the need for an anv_device.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2797>

4 years agoci: Make a530's GLES3/31 fractional runs much more complete.
Eric Anholt [Tue, 19 May 2020 23:44:14 +0000 (16:44 -0700)]
ci: Make a530's GLES3/31 fractional runs much more complete.

Now that we don't get scheduled to any 19mhz CPUs, the old GLES3 job went
from 12 minutes of deqp-runner runtime to 54s.  Increase how much of the
testsuite we cover in exchange, still keeping the runtime at 3-6 min
(compared to previous 10-17 min).  Since the tests we're running changed,
reset the xfails list.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5115>

4 years agoci: Disable SMP on the a5xx boards.
Eric Anholt [Tue, 19 May 2020 23:33:10 +0000 (16:33 -0700)]
ci: Disable SMP on the a5xx boards.

CPU0 comes up at some plausible freq, but the rest are at 19Mhz waiting
for cpufreq to come up, which has not been upstreamed.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5115>

4 years agoi965/vec4: Ignore swizzle of VGRF for use by var_range_end()
Andrii Simiklit [Thu, 7 May 2020 09:46:28 +0000 (12:46 +0300)]
i965/vec4: Ignore swizzle of VGRF for use by var_range_end()

Issue description from Matt's commit e7c376ad:
 "var_range_end(v, n) loops over the n components of variable number v and
  finds the maximum value, giving the last use of any component of v.
  Therefore it expects v to correspond to the variable associated with the
  .x channel of the VGRF.

  var_from_reg() however returns the variable for the first channel of the
  VGRF, post-swizzle.

  So, if the last register had a swizzle with y, z, or w in the swizzle
  component, we would read out of bounds. For any other register, we would
  read liveness information from the next register.

  The fix is to convert the src_reg to a dst_reg in order to call the
  dst_reg version of var_from_reg() that doesn't consider the swizzle."

Closes: #3003
Fixes: 48dfb30f ('intel/compiler: Move all live interval analysis results into vec4_live_variables')
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Andrii Simiklit <asimiklit.work@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4941>

4 years agor600/sfn: fix nop channel assignment.
Dave Airlie [Tue, 19 May 2020 23:07:21 +0000 (09:07 +1000)]
r600/sfn: fix nop channel assignment.

this fixes a bunch of asserting tests on cayman

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5113>

4 years agodocs: update calendar for 20.1.0-rc4
Eric Engestrom [Wed, 20 May 2020 19:37:25 +0000 (21:37 +0200)]
docs: update calendar for 20.1.0-rc4

Adding another release candidate next week.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5134>

4 years agoanv/gen11+: Disable object level preemption
D Scott Phillips [Tue, 19 May 2020 20:42:26 +0000 (13:42 -0700)]
anv/gen11+: Disable object level preemption

An unknown issue is causing vs push constants to become corrupted
during object-level preemption. For now, restrict to command
buffer level preemption to avoid rendering corruption.

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5110>

4 years agofreedreno: add adreno 650
Jonathan Marek [Wed, 13 May 2020 02:01:40 +0000 (22:01 -0400)]
freedreno: add adreno 650

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4611>

4 years agofreedreno/a6xx: use RESOLVE_TS event
Jonathan Marek [Fri, 17 Apr 2020 17:01:16 +0000 (13:01 -0400)]
freedreno/a6xx: use RESOLVE_TS event

This is required on a650 to flush the GMEM store.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4611>

4 years agofreedreno: reduce extra height alignment in a6xx layout
Jonathan Marek [Wed, 13 May 2020 01:58:20 +0000 (21:58 -0400)]
freedreno: reduce extra height alignment in a6xx layout

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4611>

4 years agofreedreno/a6xx: split up gmem/tile alignment requirements
Jonathan Marek [Wed, 13 May 2020 01:56:53 +0000 (21:56 -0400)]
freedreno/a6xx: split up gmem/tile alignment requirements

RB_BLIT has a granularity of 16x4, but tile sizes must be 32x16 aligned.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4611>

4 years agofreedreno/a6xx: don't use gmem_alignw for imported buffers
Jonathan Marek [Wed, 13 May 2020 01:31:52 +0000 (21:31 -0400)]
freedreno/a6xx: don't use gmem_alignw for imported buffers

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4611>

4 years agofreedreno/a5xx: remove unused reference to gmem_alignw in layout code
Jonathan Marek [Tue, 21 Jan 2020 22:08:54 +0000 (17:08 -0500)]
freedreno/a5xx: remove unused reference to gmem_alignw in layout code

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4611>

4 years agofreedreno: move a4xx specific layout code to a4xx code
Jonathan Marek [Tue, 21 Jan 2020 21:51:17 +0000 (16:51 -0500)]
freedreno: move a4xx specific layout code to a4xx code

Every other gen has its own setup_slices

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4611>

4 years agotests: Make tests aware of meson test wrapper
Dylan Baker [Thu, 14 May 2020 22:36:36 +0000 (15:36 -0700)]
tests: Make tests aware of meson test wrapper

Meson 0.55.0 will set the MESON_EXE_WRAPPER environment variable to the
joined version of that wrapper if it is needed. Our tests that take
compiled targets as arguments can use that information to run cross
built binaries, or if there isn't a wrapper and we get an ENOEXEC, we
can skip the tests gracefully.

We try to use mesonlib.split_args, which handles windows arguments
better than python's builtin shlex module, but fall back to that if the
meson module isn't available for some reason.

Cc: 20.0 20.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5103>

4 years agogallium/auxiliary/vl: Fix compute shader scale_y for interlaced videos
Thong Thai [Tue, 19 May 2020 22:06:55 +0000 (18:06 -0400)]
gallium/auxiliary/vl: Fix compute shader scale_y for interlaced videos

Signed-off-by: Thong Thai <thong.thai@amd.com>
Fixes: 494b7ef0c1a ("gallium/auxiliary/vl: Fix compute shader scaling for non-square pixels")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5121>

4 years agopan/mdg: Optimize liveness computation in DCE
Alyssa Rosenzweig [Wed, 6 May 2020 21:34:09 +0000 (17:34 -0400)]
pan/mdg: Optimize liveness computation in DCE

Rather than recompute liveness every block, compute it just once for the
whole shader, which ends up more efficient.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5123>

4 years agopan/mdg: Precompute mir_special_index
Alyssa Rosenzweig [Wed, 6 May 2020 20:06:54 +0000 (16:06 -0400)]
pan/mdg: Precompute mir_special_index

Rather than O(N) each call, we can precompute the whole set - also O(N)
- and then subsequent checks are O(1).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5123>

4 years agopan/mdg: Optimize pipelining logic
Alyssa Rosenzweig [Wed, 6 May 2020 19:36:38 +0000 (15:36 -0400)]
pan/mdg: Optimize pipelining logic

The test and rewrite were both accidentally O(N) to the shader size when
they should be O(1), so overall this takes the pass from O(N^2) to O(N).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5123>

4 years agopan/mdg: Emit fcsel when beneficial
Alyssa Rosenzweig [Mon, 4 May 2020 19:45:47 +0000 (15:45 -0400)]
pan/mdg: Emit fcsel when beneficial

If there are floating point modifiers, we emit fcsel instead of icsel
(and likewise if integer modifiers, icsel instead of fcsel) to minimize
redundant instructions.

total instructions in shared programs: 3628 -> 3626 (-0.06%)
instructions in affected programs: 139 -> 137 (-1.44%)
helped: 2
HURT: 0

total bundles in shared programs: 1886 -> 1885 (-0.05%)
bundles in affected programs: 19 -> 18 (-5.26%)
helped: 1
HURT: 0

total quadwords in shared programs: 3319 -> 3317 (-0.06%)
quadwords in affected programs: 127 -> 125 (-1.57%)
helped: 2
HURT: 0

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5123>

4 years agointel/aub_error_decoder: print driver identifier if found
Lionel Landwerlin [Tue, 24 Dec 2019 01:34:07 +0000 (03:34 +0200)]
intel/aub_error_decoder: print driver identifier if found

You can find it right before the application batch :

HuC firmware: i915/kbl_huc_ver02_00_1810.bin
        status: fetch NONE, load NONE
        version: wanted 2.0, found 0.0
        header: offset 0, size 0
        uCode: offset 0, size 0
        RSA: offset 0, size 0
Driver identifier: i965 20.0.0-devel
--- batch buffer (rcs0 (submitted by glxgears [44455])) at 0x0000fffe ec000000
0xfffeec000000:  0x70000007:  MEDIA_VFE_STATE
0xfffeec000000:  0x70000007 : Dword 0
    DWord Length: 7
0xfffeec000004:  0x00000000 : Dword 1
    Per Thread Scratch Space: 0

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3203>

4 years agoanv: add identifier BO
Lionel Landwerlin [Wed, 25 Dec 2019 21:26:48 +0000 (23:26 +0200)]
anv: add identifier BO

A buffer added to all execbufs so that we can attribute a batch that
caused a hang to a particular driver.

v2: Reuse workaround BO

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3203>

4 years agoi965: add identifier BO
Lionel Landwerlin [Tue, 24 Dec 2019 01:13:52 +0000 (03:13 +0200)]
i965: add identifier BO

A buffer added to all execbufs so that we can attribute a batch that
caused a hang to a particular driver.

v2: Reuse workaround BO

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3203>

4 years agoiris: add identifier BO
Lionel Landwerlin [Tue, 24 Dec 2019 00:41:10 +0000 (02:41 +0200)]
iris: add identifier BO

A buffer added to all execbufs so that we can attribute a batch that
caused a hang to a particular driver.

v2: Reuse workaround BO

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3203>