mesa.git
4 years agofreedreno: Fix leak of binning shader variants.
Eric Anholt [Thu, 9 Apr 2020 20:32:45 +0000 (13:32 -0700)]
freedreno: Fix leak of binning shader variants.

The v->binning variant is never added to shader->variants, so just free
each one as we free the nonbinning variant.

Noticed from drm-shim mode running out of open fds, since each bo ends up
with an fd.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4502>

4 years agofreedreno/ir3: Fix sz vs class confusion
Kristian H. Kristensen [Thu, 9 Apr 2020 22:57:41 +0000 (15:57 -0700)]
freedreno/ir3: Fix sz vs class confusion

Add bounds checking to make sure we don't silently access out of
bounds again.

Fixes: 90f7d12236c ("freedreno/ir3/ra: pick higher numbered scalars in first pass")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4503>

4 years agopan/decode: Print Bifrost blend descriptor
Alyssa Rosenzweig [Fri, 10 Apr 2020 04:26:11 +0000 (00:26 -0400)]
pan/decode: Print Bifrost blend descriptor

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>

4 years agopan/bi: Let !b2b imply branch_cond
Alyssa Rosenzweig [Fri, 10 Apr 2020 04:25:34 +0000 (00:25 -0400)]
pan/bi: Let !b2b imply branch_cond

Like the blob. Probably doesn't matter.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>

4 years agopanfrost: Fix BI_BLEND packing
Alyssa Rosenzweig [Fri, 10 Apr 2020 03:04:41 +0000 (23:04 -0400)]
panfrost: Fix BI_BLEND packing

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>

4 years agopan/bi: Fix backwards registers ports
Alyssa Rosenzweig [Wed, 8 Apr 2020 23:06:27 +0000 (19:06 -0400)]
pan/bi: Fix backwards registers ports

Will matter when packing multiple instructions per bundle.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>

4 years agopanfrost: Pass compiler-appropriate options
Alyssa Rosenzweig [Wed, 8 Apr 2020 23:05:57 +0000 (19:05 -0400)]
panfrost: Pass compiler-appropriate options

FMAs need to fuse for Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>

4 years agopanfrost: Move uniform_count to pan_assemble
Alyssa Rosenzweig [Wed, 8 Apr 2020 18:44:31 +0000 (14:44 -0400)]
panfrost: Move uniform_count to pan_assemble

Again, not Midgard specific.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>

4 years agopanfrost: Move varying linking to cmdstream
Alyssa Rosenzweig [Wed, 8 Apr 2020 17:54:17 +0000 (13:54 -0400)]
panfrost: Move varying linking to cmdstream

This isn't ISA/compiler specific, it's just looking at the NIR. So let's
move it from midgard to pan_assemble.c so it runs for Bifrost too.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>

4 years agopan/midgard: Remove unused max_varying variable
Alyssa Rosenzweig [Wed, 8 Apr 2020 17:43:59 +0000 (13:43 -0400)]
pan/midgard: Remove unused max_varying variable

I don't know why this was here.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>

4 years agopan/bi: Fix nondeterministic register packing
Alyssa Rosenzweig [Wed, 8 Apr 2020 17:35:34 +0000 (13:35 -0400)]
pan/bi: Fix nondeterministic register packing

Uninitialized read.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>

4 years agopanfrost: Call the Bifrost compiler on bi devices
Alyssa Rosenzweig [Mon, 6 Apr 2020 20:44:17 +0000 (16:44 -0400)]
panfrost: Call the Bifrost compiler on bi devices

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>

4 years agopanfrost: Set mfbd.msaa.sample_locations on Bifrost
Alyssa Rosenzweig [Mon, 6 Apr 2020 23:44:58 +0000 (19:44 -0400)]
panfrost: Set mfbd.msaa.sample_locations on Bifrost

And mfbd.shared_memory only on Midgard.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>

4 years agopanfrost: On Bifrost, set the right tiler descriptor
Tomeu Vizoso [Wed, 8 Apr 2020 13:58:42 +0000 (15:58 +0200)]
panfrost: On Bifrost, set the right tiler descriptor

On both fragment and tiler jobs.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>

4 years agopanfrost: Don't emit write_value jobs on Bifrost
Tomeu Vizoso [Tue, 7 Apr 2020 16:29:53 +0000 (18:29 +0200)]
panfrost: Don't emit write_value jobs on Bifrost

As on Bifrost GPUs there's a different mechanism for reusing the tiler
data structures.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>

4 years agopanfrost: Pass IS_BIFROST to pandecode_jc
Tomeu Vizoso [Tue, 7 Apr 2020 16:22:37 +0000 (18:22 +0200)]
panfrost: Pass IS_BIFROST to pandecode_jc

So we can decode the right structures on Bifrost hw.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>

4 years agopanfrost: Remove most usage of midgard_payload_vertex_tiler
Tomeu Vizoso [Wed, 8 Apr 2020 08:55:28 +0000 (10:55 +0200)]
panfrost: Remove most usage of midgard_payload_vertex_tiler

By passing the prefix and postfix structs around, we can use most of the
cmdstream functions as well for bifrost, as those structs haven't
changed between midgard and bifrost.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>

4 years agopanfrost: Unify vertex/tiler structures
Alyssa Rosenzweig [Tue, 7 Apr 2020 00:31:32 +0000 (20:31 -0400)]
panfrost: Unify vertex/tiler structures

Some fields were shuffled but these are essentially the same across the
generations.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>

4 years agopanfrost: Staticize a few cmdstream functions
Alyssa Rosenzweig [Tue, 7 Apr 2020 00:14:23 +0000 (20:14 -0400)]
panfrost: Staticize a few cmdstream functions

They are only used within the same source file.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>

4 years agopanfrost: Populate bifrost-specific structs within mali_shader_meta
Alyssa Rosenzweig [Mon, 6 Apr 2020 21:50:38 +0000 (17:50 -0400)]
panfrost: Populate bifrost-specific structs within mali_shader_meta

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>

4 years agopanfrost: Add IS_BIFROST quirk
Alyssa Rosenzweig [Mon, 6 Apr 2020 20:44:04 +0000 (16:44 -0400)]
panfrost: Add IS_BIFROST quirk

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4505>

4 years agoetnaviv: remove the "active" member of queries
Christian Gmeiner [Sun, 5 Apr 2020 19:46:55 +0000 (21:46 +0200)]
etnaviv: remove the "active" member of queries

The state tracker only gets to begin/query/destroy when !active and end
when active, so we have no need to try to track this ourselves.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4456>

4 years agoetnaviv: change begin_query(..) to a void function
Christian Gmeiner [Sun, 5 Apr 2020 19:33:26 +0000 (21:33 +0200)]
etnaviv: change begin_query(..) to a void function

We always return true.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4456>

4 years agoetnaviv: drop redundant calls to etna_acc_query_suspend(..)
Christian Gmeiner [Sun, 5 Apr 2020 19:42:10 +0000 (21:42 +0200)]
etnaviv: drop redundant calls to etna_acc_query_suspend(..)

Introduced by accident during rebase.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4456>

4 years agov3d: Primitive Counts Feedback needs an extra 32-bit padding.
Jose Maria Casanova Crespo [Wed, 8 Apr 2020 18:51:52 +0000 (20:51 +0200)]
v3d: Primitive Counts Feedback needs an extra 32-bit padding.

Store Primitive Counts operations write 7 counters in 32-bit words
but also a padding 32-bit with 0. So we need 8 32-bit words instead
of the current 7 allocated.

This was causing an corruption in the next buffer when Transform
Feedback was enabled that were exposed on tests like:
dEQP-GLES3.functional.transform_feedback.*.points.*

This patch fixes 196 tests that were failing when they were run isolated
but they were passing when run using cts-runner.

Fixes: 0f2d1dfe65bf ("v3d: use the GPU to record primitives written to transform feedback")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2674
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4501>

4 years agoaco: make some reg_file helpers private and fix their uses
Daniel Schürmann [Wed, 8 Apr 2020 14:27:34 +0000 (15:27 +0100)]
aco: make some reg_file helpers private and fix their uses

Fixes various subdword RA issues

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4492>

4 years agoaco: rename aco_lower_bool_phis() -> aco_lower_phis()
Daniel Schürmann [Tue, 7 Apr 2020 11:20:52 +0000 (12:20 +0100)]
aco: rename aco_lower_bool_phis() -> aco_lower_phis()

We also lower subdword phis, now.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4492>

4 years agoaco: lower subdword phis with SGPR operands
Daniel Schürmann [Tue, 7 Apr 2020 11:16:57 +0000 (12:16 +0100)]
aco: lower subdword phis with SGPR operands

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4492>

4 years agoaco: don't constant-propagate into subdword PSEUDO instructions
Daniel Schürmann [Tue, 7 Apr 2020 09:46:37 +0000 (10:46 +0100)]
aco: don't constant-propagate into subdword PSEUDO instructions

PSEUDO instructions are lowered using SDWA, and thus,
cannot take literals and before GFX9 cannot take constants
at all. As the in-register representation differs between
32bit and 16bit floats, we first need to ensure correct
behavior.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4492>

4 years agoaco: ensure correct bit representation of subdword constants
Daniel Schürmann [Tue, 7 Apr 2020 09:37:25 +0000 (10:37 +0100)]
aco: ensure correct bit representation of subdword constants

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4492>

4 years agoaco: setup subdword regclasses for ssa_undef & load_const
Daniel Schürmann [Tue, 7 Apr 2020 09:24:36 +0000 (10:24 +0100)]
aco: setup subdword regclasses for ssa_undef & load_const

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4492>

4 years agoaco: implement nir_op_b2f16/nir_op_i2f16/nir_op_u2f16
Samuel Pitoiset [Fri, 3 Apr 2020 13:26:15 +0000 (15:26 +0200)]
aco: implement nir_op_b2f16/nir_op_i2f16/nir_op_u2f16

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>

4 years agoaco: implement 16-bit comparisons
Samuel Pitoiset [Fri, 3 Apr 2020 13:12:17 +0000 (15:12 +0200)]
aco: implement 16-bit comparisons

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>

4 years agoaco: implement 16-bit nir_op_fmax3/nir_op_fmin3/nir_op_fmed3
Samuel Pitoiset [Sat, 4 Apr 2020 08:07:03 +0000 (10:07 +0200)]
aco: implement 16-bit nir_op_fmax3/nir_op_fmin3/nir_op_fmed3

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>

4 years agoaco: implement 16-bit nir_op_ldexp
Samuel Pitoiset [Fri, 3 Apr 2020 13:40:35 +0000 (15:40 +0200)]
aco: implement 16-bit nir_op_ldexp

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>

4 years agoaco: implement 16-bit nir_op_f2i32/nir_op_f2u32
Samuel Pitoiset [Fri, 3 Apr 2020 13:40:18 +0000 (15:40 +0200)]
aco: implement 16-bit nir_op_f2i32/nir_op_f2u32

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>

4 years agoaco: implement 16-bit nir_op_bcsel
Samuel Pitoiset [Fri, 3 Apr 2020 13:12:12 +0000 (15:12 +0200)]
aco: implement 16-bit nir_op_bcsel

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>

4 years agoaco: implement 16-bit nir_op_fsign
Samuel Pitoiset [Fri, 3 Apr 2020 12:55:01 +0000 (14:55 +0200)]
aco: implement 16-bit nir_op_fsign

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>

4 years agoaco: implement 16-bit nir_op_fsat
Samuel Pitoiset [Fri, 3 Apr 2020 12:18:37 +0000 (14:18 +0200)]
aco: implement 16-bit nir_op_fsat

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>

4 years agoaco: implement 16-bit nir_op_fmul
Samuel Pitoiset [Fri, 3 Apr 2020 11:44:40 +0000 (13:44 +0200)]
aco: implement 16-bit nir_op_fmul

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>

4 years agoaco: implement 16-bit nir_op_fcos/nir_op_fsin
Samuel Pitoiset [Fri, 3 Apr 2020 11:40:28 +0000 (13:40 +0200)]
aco: implement 16-bit nir_op_fcos/nir_op_fsin

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>

4 years agoaco: implement 16-bit nir_op_fsub/nir_op_fadd
Samuel Pitoiset [Fri, 3 Apr 2020 11:34:18 +0000 (13:34 +0200)]
aco: implement 16-bit nir_op_fsub/nir_op_fadd

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>

4 years agoaco: implement 16-bit nir_op_fabs/nir_op_fneg
Samuel Pitoiset [Fri, 3 Apr 2020 10:24:41 +0000 (12:24 +0200)]
aco: implement 16-bit nir_op_fabs/nir_op_fneg

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>

4 years agoaco: implement 16-bit nir_op_fmax/nir_op_fmin
Samuel Pitoiset [Fri, 3 Apr 2020 10:09:41 +0000 (12:09 +0200)]
aco: implement 16-bit nir_op_fmax/nir_op_fmin

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>

4 years agoaco: implement 16-bit nir_op_ffloor/nir_op_fceil
Samuel Pitoiset [Fri, 3 Apr 2020 09:47:54 +0000 (11:47 +0200)]
aco: implement 16-bit nir_op_ffloor/nir_op_fceil

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>

4 years agoaco: implement 16-bit nir_op_fsqrt/nir_op_frcp/nir_op_frsq
Samuel Pitoiset [Fri, 3 Apr 2020 09:37:56 +0000 (11:37 +0200)]
aco: implement 16-bit nir_op_fsqrt/nir_op_frcp/nir_op_frsq

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>

4 years agoaco: implement 16-bit nir_op_ftrunc/nir_op_fround_even
Samuel Pitoiset [Fri, 3 Apr 2020 09:19:52 +0000 (11:19 +0200)]
aco: implement 16-bit nir_op_ftrunc/nir_op_fround_even

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>

4 years agoaco: implement 16-bit nir_op_fexp2/nir_op_flog2
Samuel Pitoiset [Fri, 3 Apr 2020 09:12:21 +0000 (11:12 +0200)]
aco: implement 16-bit nir_op_fexp2/nir_op_flog2

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>

4 years agoaco: implement 16-bit nir_op_ffract
Samuel Pitoiset [Fri, 3 Apr 2020 09:07:24 +0000 (11:07 +0200)]
aco: implement 16-bit nir_op_ffract

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>

4 years agoaco: implement 16-bit nir_op_frexp_sig/nir_op_frexp_exp
Samuel Pitoiset [Fri, 3 Apr 2020 08:41:17 +0000 (10:41 +0200)]
aco: implement 16-bit nir_op_frexp_sig/nir_op_frexp_exp

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4452>

4 years agointel/compiler: Remove cs_prog_data->threads
Caio Marcelo de Oliveira Filho [Fri, 27 Mar 2020 15:29:09 +0000 (08:29 -0700)]
intel/compiler: Remove cs_prog_data->threads

At this point all drivers are doing this math on their own -- since
most of them need to cover the variable group size case, in which at
compile time the group size (and number of threads) is not defined.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4504>

4 years agoiris: Stop using cs_prog_data->threads
Caio Marcelo de Oliveira Filho [Thu, 9 Apr 2020 23:54:25 +0000 (16:54 -0700)]
iris: Stop using cs_prog_data->threads

This is a preparation for dropping this field since this value is
expected to be calculated by the drivers now for variable group size
case.  And also the field would get in the way of brw_compile_cs
producing multiple SIMD variants (like FS).

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4504>

4 years agoanv: Stop using cs_prog_data->threads
Caio Marcelo de Oliveira Filho [Fri, 27 Mar 2020 15:18:00 +0000 (08:18 -0700)]
anv: Stop using cs_prog_data->threads

Move the calculation to helper functions -- similar to what GL already
needs to do.

This is a preparation for dropping this field since this value is
expected to be calculated by the drivers now for variable group size
case.  And also the field would get in the way of brw_compile_cs
producing multiple SIMD variants (like FS).

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4504>

4 years agoi965: Implement ARB_compute_variable_group_size
Plamena Manolova [Mon, 12 Nov 2018 14:29:51 +0000 (16:29 +0200)]
i965: Implement ARB_compute_variable_group_size

This patch adds the implementation of ARB_compute_variable_group_size
for i965. We do this by storing the local group size in a push constant.

Additional changes made by Caio Marcelo de Oliveira Filho.

Signed-off-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4504>

4 years agointel/compiler: Add support for variable workgroup size
Plamena Manolova [Mon, 12 Nov 2018 14:29:51 +0000 (06:29 -0800)]
intel/compiler: Add support for variable workgroup size

Add new builtin parameters that are used to keep track of the group
size.  This will be used to implement ARB_compute_variable_group_size.

The compiler will use the maximum group size supported to pick a
suitable SIMD variant.  A later improvement will be to keep all SIMD
variants (like FS) so the driver can select the best one at dispatch
time.

When variable workgroup size is used, the small workgroup optimization
is disabled as it we can't prove at compile time that the barriers
won't be needed.

Extracted from original i965 patch with additional changes by
Caio Marcelo de Oliveira Filho.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4504>

4 years agointel/compiler: Replace cs_prog_data->push.total with a helper
Caio Marcelo de Oliveira Filho [Sat, 21 Mar 2020 04:02:06 +0000 (21:02 -0700)]
intel/compiler: Replace cs_prog_data->push.total with a helper

The push.total field had three values but only one was directly
used (size).  Replace it with a helper function that explicitly takes
the cs_prog_data and the number of threads -- and use that in the
drivers.

This is a preparation for ARB_compute_variable_group_size where the
number of threads (hence the total size for push constants) is not
defined at compile time (not cs_prog_data->threads).

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4504>

4 years agoswr/rasterizer: Use private functions for min/max to avoid namespace issues.
Vinson Lee [Tue, 17 Mar 2020 05:49:39 +0000 (22:49 -0700)]
swr/rasterizer: Use private functions for min/max to avoid namespace issues.

This is a similiar fix as bb2287ccdf46 ("gallivm/tessellator: use
private functions for min/max to avoid namespace issues").

Fixes: ab5570820071 ("swr/rasterizer: Add tessellator implementation to the rasterizer")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
Tested-by: Jan Zielinski <jan.zielinski@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4208>

4 years agotu: Implement descriptor set update templates
Connor Abbott [Tue, 24 Mar 2020 17:01:15 +0000 (18:01 +0100)]
tu: Implement descriptor set update templates

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>

4 years agotu: Add missing code for immutable samplers
Connor Abbott [Tue, 24 Mar 2020 17:00:21 +0000 (18:00 +0100)]
tu: Add missing code for immutable samplers

Actually fill out the samplers, based on the radv implementation.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>

4 years agotu: Emit CP_LOAD_STATE6 for descriptors
Connor Abbott [Mon, 23 Mar 2020 16:23:32 +0000 (17:23 +0100)]
tu: Emit CP_LOAD_STATE6 for descriptors

This restores the pre-loading of descriptor state, using the new
SS6_BINDLESS method that allows us to pre-load bindless resources.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>

4 years agotu: Switch to the bindless descriptor model
Connor Abbott [Mon, 16 Mar 2020 10:49:19 +0000 (11:49 +0100)]
tu: Switch to the bindless descriptor model

Under the bindless model, there are 5 "base" registers programmed with a
64-bit address, and sam/ldib/ldc and so on each specify a base register
and an offset, in units of 16 dwords. The base registers correspond to
descriptor sets in Vulkan. We allocate a buffer at descriptor set
creation time, hopefully outside the main rendering loop, and then
switching descriptor sets is just a matter of programming the base
registers differently. Note, however, that some kinds of descriptors
need to be patched at command recording time, in particular dynamic
UBO's and SSBO's, which need to be patched at CmdBindDescriptorSets
time, and input attachments which need to be patched at draw time based
on the the pipeline that's bound. We reserve the fifth base register
(which seems to be unused by the blob driver) for these, creating a
descriptor set on-the-fly and combining all the dynamic descriptors from
all the different descriptor sets. This way, we never have to copy the
rest of the descriptor set at draw time like the blob seems to do. I
mostly chose to do this because the infrastructure was already there in
the form of dynamic_descriptors, and other drivers (at least radv) don't
cheat either when implementing this.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>

4 years agoir3: Rewrite UBO push analysis to support bindless
Connor Abbott [Mon, 23 Mar 2020 17:54:57 +0000 (18:54 +0100)]
ir3: Rewrite UBO push analysis to support bindless

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>

4 years agoir3: Plumb through bindless support
Connor Abbott [Thu, 19 Mar 2020 13:15:26 +0000 (14:15 +0100)]
ir3: Plumb through bindless support

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>

4 years agoir3: LDC also has a destination
Connor Abbott [Fri, 20 Mar 2020 14:25:59 +0000 (15:25 +0100)]
ir3: LDC also has a destination

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>

4 years agoir3: Also don't propagate immediate offset with LDC
Connor Abbott [Fri, 20 Mar 2020 14:25:11 +0000 (15:25 +0100)]
ir3: Also don't propagate immediate offset with LDC

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>

4 years agoir3: Plumb through support for a1.x
Connor Abbott [Wed, 18 Mar 2020 17:06:41 +0000 (18:06 +0100)]
ir3: Plumb through support for a1.x

This will need to be used in some cases for the upcoming bindless
support, plus ldc.k instructions which push data from a UBO to const
registers.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>

4 years agoir3: Add bindless instruction encoding
Connor Abbott [Fri, 6 Mar 2020 17:06:06 +0000 (18:06 +0100)]
ir3: Add bindless instruction encoding

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>

4 years agofreedreno/a6xx: Add registers for the bindless model
Connor Abbott [Fri, 6 Mar 2020 10:29:54 +0000 (11:29 +0100)]
freedreno/a6xx: Add registers for the bindless model

In Vulkan, descriptors for samplers, SSBO's, etc. are collected into
descriptor sets, and shaders can use multiple descriptor sets. At
command-recording time, users can swap out only some of the descriptor
sets, and the driver is supposed to do the minimum amount necessary to
update any internal binding tables, knowing that only some of the
descriptors have changed.

With the old binding model, focused on GL, where there are separate
tables for each type of resource, we can do somewhat better than now by
preserving descriptors from lower descriptor sets when switching higher
descriptor sets. However we still have to copy around descriptors before
each draw.

At least for a6xx, qualcomm went further, essentially copying the Vulkan
binding model as an alternate way to load resources. There's an array of
registers (actually an array for compute and one for everything else),
where each register holds a pointer to a descriptor set that can contain
various different descriptor types. The descriptors are padded out to 16
dwords, so that every instruction can use an index instead of a dword
offset. It's called "bindless", I think, because it can also be used to
implement the old GL bindless extensions (presumably it allows more
samplers and textures than the old model).

This commit adds the register and cmdstream parts. Next up will be the
instruction encoding.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>

4 years agofreedreno/a6xx: Add UBO size field
Connor Abbott [Fri, 6 Mar 2020 10:27:46 +0000 (11:27 +0100)]
freedreno/a6xx: Add UBO size field

Verified with the vulkan blob, which uses ldc and UBO descriptors, and
turnip will too soon.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>

4 years agotu: ir3: Emit push constants directly
Connor Abbott [Wed, 18 Mar 2020 12:12:31 +0000 (13:12 +0100)]
tu: ir3: Emit push constants directly

Carve out some space at the beginning for push constants, and push them
directly, rather than remapping them to a UBO and then relying on the
UBO pushing code. Remapping to a UBO is easy now, where there's a single
table of UBO's, but with the bindless model it'll be a lot harder. I
haven't removed all the code to move the remaining UBO's over by 1,
though, because it's going to all get rewritten with bindless anyways.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>

4 years agotu: Dump out shader assembly when requested
Connor Abbott [Thu, 26 Mar 2020 14:35:11 +0000 (15:35 +0100)]
tu: Dump out shader assembly when requested

We don't use the ir3 variant machinery, so we have to do this ourselves.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4358>

4 years agoaco: RA - move all std::function objects into proper functions
Daniel Schürmann [Tue, 7 Apr 2020 16:15:35 +0000 (17:15 +0100)]
aco: RA - move all std::function objects into proper functions

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4130>

4 years agoaco: move all needed helper containers to ra_ctx
Daniel Schürmann [Tue, 7 Apr 2020 15:46:58 +0000 (16:46 +0100)]
aco: move all needed helper containers to ra_ctx

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4130>

4 years agoaco: change live_out variables to std::unordered_set
Daniel Schürmann [Wed, 11 Mar 2020 10:02:20 +0000 (11:02 +0100)]
aco: change live_out variables to std::unordered_set

Improves performance of live_var_analysis for larger shaders

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4130>

4 years agoaco: change some std::map to std::unordered_map in register_allocation
Daniel Schürmann [Wed, 11 Mar 2020 09:47:07 +0000 (10:47 +0100)]
aco: change some std::map to std::unordered_map in register_allocation

This improves compile times slightly for larger shaders

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4130>

4 years agoaco: refactor try_remove_trivial_phi() in RA
Daniel Schürmann [Wed, 11 Mar 2020 07:38:48 +0000 (08:38 +0100)]
aco: refactor try_remove_trivial_phi() in RA

Minor refactoring to avoid some pointer chasing.
This patch also changes the live_out argument to be
passed by reference to avoid an unnecessary copy.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4130>

4 years agoaco: improve speed of live_var_analysis
Daniel Schürmann [Tue, 10 Mar 2020 12:39:42 +0000 (13:39 +0100)]
aco: improve speed of live_var_analysis

by merging live_sgprs and live_vgprs sets.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4130>

4 years agoaco: during RA only insert into renames table if a variable got renamed
Daniel Schürmann [Tue, 10 Mar 2020 11:41:02 +0000 (12:41 +0100)]
aco: during RA only insert into renames table if a variable got renamed

This improves the speed of register allocation.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4130>

4 years agoaco: replace assignment hashmap by std::vector in register allocation
Daniel Schürmann [Tue, 10 Mar 2020 10:47:30 +0000 (11:47 +0100)]
aco: replace assignment hashmap by std::vector in register allocation

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4130>

4 years agoaco: improve register assignment when live-range splits are necessary
Daniel Schürmann [Tue, 10 Mar 2020 10:50:41 +0000 (11:50 +0100)]
aco: improve register assignment when live-range splits are necessary

When finding a good place for a register, we can ignore
killed operands.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4130>

4 years agoaco: improve hashing for value numbering
Daniel Schürmann [Tue, 10 Mar 2020 09:00:32 +0000 (10:00 +0100)]
aco: improve hashing for value numbering

An improved hashing greatly reduces the number of collisions,
and thus, increases the speed for lookups in the hash table.
The hash function now uses Murmur3 written by Austin Appleby.

This patch also pre-reserves space for the hashmap to avoid rehashing.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4130>

4 years agoaco: add explicit padding for all Instruction sub-structs
Daniel Schürmann [Mon, 30 Mar 2020 16:25:00 +0000 (17:25 +0100)]
aco: add explicit padding for all Instruction sub-structs

This patch also adds static_asserts on the size of Instructions
to ensure no internal padding is present.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4130>

4 years agoaco: guarantee that Temp fits in 4 bytes
Daniel Schürmann [Wed, 11 Mar 2020 12:12:08 +0000 (13:12 +0100)]
aco: guarantee that Temp fits in 4 bytes

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4130>

4 years agoturnip: new clear/blit implementation with shader path fallback
Jonathan Marek [Fri, 13 Mar 2020 15:57:23 +0000 (11:57 -0400)]
turnip: new clear/blit implementation with shader path fallback

The shader path is used to implement the following cases:
* stencil aspect mask on D24S8 (for image_to_buffer,buffer_to_image)
* clear/copy msaa destination (2D engine can't have msaa dest)

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>

4 years agoturnip: add vk_format_is_snorm/is_float
Jonathan Marek [Wed, 8 Apr 2020 14:56:30 +0000 (10:56 -0400)]
turnip: add vk_format_is_snorm/is_float

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>

4 years agoturnip: rework format helpers
Jonathan Marek [Wed, 8 Apr 2020 14:56:16 +0000 (10:56 -0400)]
turnip: rework format helpers

* Take tile_mode as input directly
* tu6_format_gmem to tu6_base_format, use may not be limited to GMEM
* Add new helpers that will return the correct tile_mode as for image level
  as part of the format.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>

4 years agoturnip: use dirty bits for dynamic viewport/scissor state
Jonathan Marek [Wed, 8 Apr 2020 03:25:12 +0000 (23:25 -0400)]
turnip: use dirty bits for dynamic viewport/scissor state

CmdClearAttachments shader path will overwrite this state, so it needs to
be re-emitted with dirty bits in that case.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>

4 years agoturnip: save attachment samples in renderpass state
Jonathan Marek [Wed, 8 Apr 2020 02:23:27 +0000 (22:23 -0400)]
turnip: save attachment samples in renderpass state

This is needed to be able to know the number of samples during
CmdClearAttachments which can be used while the framebuffer is unknown.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>

4 years agoturnip: disable 8x msaa
Jonathan Marek [Wed, 8 Apr 2020 02:20:10 +0000 (22:20 -0400)]
turnip: disable 8x msaa

Not everything supports 8x msaa, and the blob doesn't support it at all.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>

4 years agoturnip: fix nir validate failure from push constant lowering
Jonathan Marek [Wed, 8 Apr 2020 01:39:40 +0000 (21:39 -0400)]
turnip: fix nir validate failure from push constant lowering

Fixes newly added checks in nir validate failing.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>

4 years agoturnip: split up gmem/tile alignment
Jonathan Marek [Tue, 18 Feb 2020 13:54:15 +0000 (08:54 -0500)]
turnip: split up gmem/tile alignment

Note: the x1/y1 align in tu6_emit_blit_scissor was broken

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>

4 years agoturnip: RB_CCU_CNTL fixes
Jonathan Marek [Fri, 13 Mar 2020 15:47:15 +0000 (11:47 -0400)]
turnip: RB_CCU_CNTL fixes

* Correct bypass value for a618
* Bypass value for blitter
* Don't set RB_CCU_CNTL again unnecessarily in tu6_emit_binning_pass

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>

4 years agofreedreno/a6xx: set bypass RB_CCU_CNTL value for blitter
Jonathan Marek [Fri, 13 Mar 2020 14:20:23 +0000 (10:20 -0400)]
freedreno/a6xx: set bypass RB_CCU_CNTL value for blitter

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>

4 years agofreedreno/registers: add RB_CCU_CNTL bitfields
Jonathan Marek [Fri, 13 Mar 2020 14:09:11 +0000 (10:09 -0400)]
freedreno/registers: add RB_CCU_CNTL bitfields

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3783>

4 years agoradv: allow TC-compat HTILE with GENERAL outside of render loops
Samuel Pitoiset [Thu, 9 Apr 2020 09:37:27 +0000 (11:37 +0200)]
radv: allow TC-compat HTILE with GENERAL outside of render loops

This gives +8% with Wolfeinstein Youngblood on my Vega64, and
according to someone else, it also improves performance with Doom
2016 and Wolfenstein 2 (and probably other ID Tech games).

This improvement is because Youngblood uses GENERAL for the main
depth-only pass and TC-compat HTILE is now enabled with GENERAL if
we know that we are outside of a render loop. This obviously also
reduces the number of HTILE decompressions from/to GENERAL.

Note that Youngblood violates the Vulkan spec regarding render loops
because they are only allowed with input attachments. Expect possible
rendering issues if apps use render loops with the wrong way (ie.
without input attachmens) because HTILE might not be coherent if
a depth-stencil texture is sampled and rendered in the same draw.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2704
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4391>

4 years agoradv: only enable TC-compat HTILE for images readable by a shader
Samuel Pitoiset [Tue, 31 Mar 2020 08:35:00 +0000 (10:35 +0200)]
radv: only enable TC-compat HTILE for images readable by a shader

If no texture fetches happen it's useless to enable TC-compat HTILE.

Because the driver currently doesn't support TC-compat HTILE for
storage images we don't have to check.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4497>

4 years agoradv: only expose fp16 control features for chips with double rate fp16
Samuel Pitoiset [Sun, 5 Apr 2020 07:42:50 +0000 (09:42 +0200)]
radv: only expose fp16 control features for chips with double rate fp16

This disables all fp16 shader control features on GFX8 because only
GFX9+ supports double rate packed math.

This improves consistency regarding other AMD Vulkan drivers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4453>

4 years agoradv: only expose storageInputOutput16 for chips with double rate fp16
Samuel Pitoiset [Sun, 5 Apr 2020 07:33:43 +0000 (09:33 +0200)]
radv: only expose storageInputOutput16 for chips with double rate fp16

This feature allows to use both 16-bit integers and 16-bit floats
as inputs/outputs.

This disables storageInputOutput16 on GFX8 because only GFX9+ supports
double rate packed math.

This improves consistency regarding other AMD Vulkan drivers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4453>

4 years agoradv: only expose shaderFloat16 for chips with double rate fp16
Samuel Pitoiset [Sun, 5 Apr 2020 07:25:18 +0000 (09:25 +0200)]
radv: only expose shaderFloat16 for chips with double rate fp16

This disables shaderFloat16 on GFX8 because only GFX9+ supports
double rate packed math.

This improves consistency regarding other AMD Vulkan drivers and
it makes no sense to enable that feature without packed math.

This also reduces performance with Wolfeinstein Youngblood if
fp16 is forced enabled on GFX8, while it's similar on GFX9.

We might re-introduce that feature in the future with ACO support
if it ends up being faster and correct.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4453>

4 years agoac,radv: add ac_gpu_info::has_double_rate_fp16
Samuel Pitoiset [Sun, 5 Apr 2020 07:23:16 +0000 (09:23 +0200)]
ac,radv: add ac_gpu_info::has_double_rate_fp16

Only GFX9+ support double rate packed math instructions.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4453>