Luke Kenneth Casson Leighton [Tue, 14 Dec 2021 17:01:29 +0000 (17:01 +0000)]
update wb_get memory with instructions if required
this is for running TestIssuer with rom={some dictionary}"
Tobias Platen [Tue, 14 Dec 2021 15:56:28 +0000 (16:56 +0100)]
fix test_loadstore1_ifetch_multi() in test_loadstore1.py
Tobias Platen [Tue, 14 Dec 2021 14:30:35 +0000 (15:30 +0100)]
wip test case for virtual address fetch using fetch interface
Tobias Platen [Tue, 14 Dec 2021 12:27:41 +0000 (13:27 +0100)]
fix test_loadstore1_ifetch_multi()
Jonathan Neuschäfer [Mon, 13 Dec 2021 23:03:35 +0000 (00:03 +0100)]
GitLab-CI: Increase clone depth
Currently, GitLab-CI fails with this error:
error: Server does not allow request for unadvertised object
d96f737c0a53dde983060522816bbef016b449ce
Fetched in submodule path 'pinmux', but it did not contain
d96f737c0a53dde983060522816bbef016b449ce. Direct fetching of that commit failed.
Fix it by increasing the clone depth from the default of 50 to 500.
Luke Kenneth Casson Leighton [Tue, 14 Dec 2021 00:46:53 +0000 (00:46 +0000)]
MMU LOOKUP for fetch failed, priv mode is inversion of MSR.PR
Luke Kenneth Casson Leighton [Tue, 14 Dec 2021 00:44:48 +0000 (00:44 +0000)]
link MSR.PR into MMU FSM OP_FETCH_FAILED
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 22:32:24 +0000 (22:32 +0000)]
return temporarily to older version of pinmux submodule
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 18:16:31 +0000 (18:16 +0000)]
request a flush of icache to clear the instruction-fault state
when an exception is identified
g
Tobias Platen [Mon, 13 Dec 2021 18:04:40 +0000 (19:04 +0100)]
try to get multi test running
Tobias Platen [Mon, 13 Dec 2021 15:07:12 +0000 (16:07 +0100)]
comments about test_loadstore1_ifetch()
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 14:22:17 +0000 (14:22 +0000)]
fix test_loadstore1.py with MSR=PR/DR
for invalid test pr=1 but for others pr=0
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 14:19:59 +0000 (14:19 +0000)]
set pr=0 because privileged mode is pr=0 not pr=1
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 14:16:00 +0000 (14:16 +0000)]
add in missing MSRSpec import
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 14:14:33 +0000 (14:14 +0000)]
commented-out code
Tobias Platen [Mon, 13 Dec 2021 13:40:39 +0000 (14:40 +0100)]
update MMU PortInterface Test (misalign)
Tobias Platen [Mon, 13 Dec 2021 13:34:23 +0000 (14:34 +0100)]
cleanup test_ldst_pi.py
Tobias Platen [Mon, 13 Dec 2021 13:27:51 +0000 (14:27 +0100)]
update old TestMicrowattMemoryPortInterface
Tobias Platen [Mon, 13 Dec 2021 13:26:37 +0000 (14:26 +0100)]
replace msr_pr with msr
Tobias Platen [Mon, 13 Dec 2021 13:17:45 +0000 (14:17 +0100)]
cleanup test_dcbz_pi.py
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 13:08:53 +0000 (13:08 +0000)]
fix up pr/dr/sf in PortInterfaceBase
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 13:06:53 +0000 (13:06 +0000)]
pass in new MSRSpec to test_loadstore1.py not msr_pr=1
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 13:01:58 +0000 (13:01 +0000)]
convert PortInterfaceBase to pass msr not msr_pr
https://bugs.libre-soc.org/show_bug.cgi?id=756
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 13:00:54 +0000 (13:00 +0000)]
convert LoadStore1 to new msr.pr/dr/sf
https://bugs.libre-soc.org/show_bug.cgi?id=756
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 12:55:03 +0000 (12:55 +0000)]
add msr to MMU Op Subset record
Tobias Platen [Mon, 13 Dec 2021 12:53:53 +0000 (13:53 +0100)]
use NamedTuple pr in test_pi2ls
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 12:43:15 +0000 (12:43 +0000)]
still have to import MSRSpec
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 12:41:23 +0000 (12:41 +0000)]
connect up PortInterface priv_mode, virt_mode and mode_32bit
to MSR.PR, DR and SF.
https://bugs.libre-soc.org/show_bug.cgi?id=756
Tobias Platen [Mon, 13 Dec 2021 12:36:34 +0000 (13:36 +0100)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 12:35:02 +0000 (12:35 +0000)]
construct an MSRSpec in PortInterfaceBase (not used yet)
Tobias Platen [Mon, 13 Dec 2021 12:34:52 +0000 (13:34 +0100)]
remove redundant MSRSpec from pimem
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 12:32:31 +0000 (12:32 +0000)]
whoops wrong variable names
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 12:31:58 +0000 (12:31 +0000)]
rename msr_pr to priv_mode in LDSTCompUnit
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 12:29:06 +0000 (12:29 +0000)]
TODO comments about using MSRspec
Luke Kenneth Casson Leighton [Mon, 13 Dec 2021 12:26:35 +0000 (12:26 +0000)]
change PortInterface naming to msr not msr_pr in set_wr_addr
and set_rd_addr. the name-change does not affect any code at the moment
Tobias Platen [Mon, 13 Dec 2021 12:01:45 +0000 (13:01 +0100)]
add namedtuple proposed by lkcl in chat
Tobias Platen [Mon, 13 Dec 2021 10:41:24 +0000 (11:41 +0100)]
add signals to port interface as descibed in bug 756
Tobias Platen [Mon, 13 Dec 2021 09:45:50 +0000 (10:45 +0100)]
more work on test_loadstore1_ifetch_multi()
Luke Kenneth Casson Leighton [Sun, 12 Dec 2021 21:08:35 +0000 (21:08 +0000)]
set and reset instruction fault so it does not occur twice
Luke Kenneth Casson Leighton [Sun, 12 Dec 2021 20:45:49 +0000 (20:45 +0000)]
when an exception happens, if it is a fetch_failed take the
exception from the MMU not from LDST.
at some point need a much more sophisticated way of detecting which
unit created which exception
Luke Kenneth Casson Leighton [Sun, 12 Dec 2021 20:45:04 +0000 (20:45 +0000)]
delay MMU LOOKUP done by one clock so that the exception matches timing
Luke Kenneth Casson Leighton [Sun, 12 Dec 2021 20:44:26 +0000 (20:44 +0000)]
bring MMU exception out where AllFunctionUnits (and then core)
can get at it
Luke Kenneth Casson Leighton [Sun, 12 Dec 2021 20:18:46 +0000 (20:18 +0000)]
bring exception out from MMU FSM, correct "done"
signal output on OP_FETCH_FAILED
Luke Kenneth Casson Leighton [Sun, 12 Dec 2021 20:05:50 +0000 (20:05 +0000)]
add LDSTException output to MMU
Luke Kenneth Casson Leighton [Sun, 12 Dec 2021 19:10:36 +0000 (19:10 +0000)]
drat, a test inverting the instruction made it into the git history
Luke Kenneth Casson Leighton [Sun, 12 Dec 2021 18:56:13 +0000 (18:56 +0000)]
starting to hack in fetch failed (including OP_FETCH_FAILED)
going really badly as far as code-readability and clean design is concerned
but is progressing
a truly dreadful hack: OP_TRAP works (LDST Exceptions) because the
main decoder (PowerDecoder2) is used by core for the Trap pipeline.
unnnnfortunately... for MMU, a *Satellite* decoder (PowerDecodeSubset)
is used. and Satellite decoders *only* understand *instructions*.
(which they part-decode locally).
therefore a manual override of the satellite decoder insn_type
and fn_unit is required when OP_FETCH_FAILED occurs.
truly awful.
Luke Kenneth Casson Leighton [Sun, 12 Dec 2021 15:47:10 +0000 (15:47 +0000)]
print debugs established that when a wb_get memory dictionary is
passed in, trying to use setup_i_memory and setup_tst_memory will not
work.
using wb_get has to be established a different way
Luke Kenneth Casson Leighton [Sun, 12 Dec 2021 15:44:50 +0000 (15:44 +0000)]
set fetch_failed into PowerDecoder2 combinatorially
Luke Kenneth Casson Leighton [Sun, 12 Dec 2021 13:15:51 +0000 (13:15 +0000)]
in a terrible botched way, get at I-Cache and set it up
this is for adding in I-Cache and MMU into core.
Luke Kenneth Casson Leighton [Sat, 11 Dec 2021 23:49:48 +0000 (23:49 +0000)]
fix bug in unit test, forgot that wb_get mem dict is 64-bit wide data
it cannot cope with addresses non-aligned to 64-bit boundary
Luke Kenneth Casson Leighton [Sat, 11 Dec 2021 23:42:53 +0000 (23:42 +0000)]
get FetchUnitInterface I-Cache test working (sort-of)
bug in reading addresses 0xc. 0x8 and 0x10 are fine
Luke Kenneth Casson Leighton [Sat, 11 Dec 2021 23:19:34 +0000 (23:19 +0000)]
comment out broken test
Luke Kenneth Casson Leighton [Sat, 11 Dec 2021 23:19:04 +0000 (23:19 +0000)]
whoops forgot to add pspec
Tobias Platen [Sat, 11 Dec 2021 16:14:25 +0000 (17:14 +0100)]
typo fix, add missing stop statement to _test_loadstore1_ifetch_multi()
Tobias Platen [Sat, 11 Dec 2021 16:10:18 +0000 (17:10 +0100)]
add loop with multiple instructions for testing
Tobias Platen [Sat, 11 Dec 2021 16:02:51 +0000 (17:02 +0100)]
add skeleton for test_loadstore1_ifetch_multi()
Luke Kenneth Casson Leighton [Sat, 11 Dec 2021 15:47:05 +0000 (15:47 +0000)]
add start of test_loadstore1_ifetch_unit_interface()
which is supposed to use FetchUnitInterface like the imem.py unit test
unfinished
Luke Kenneth Casson Leighton [Sat, 11 Dec 2021 14:36:58 +0000 (14:36 +0000)]
connect up I-Cache to FetchUnitInterface
FetchUnitInterface may in turn need redesigning, but that is another story
Luke Kenneth Casson Leighton [Sat, 11 Dec 2021 14:18:47 +0000 (14:18 +0000)]
add new ConfigFetchUnit option "mmu_cache_wb" which connects up
directly to LoadstStore1 I-Cache
Jacob Lifshay [Fri, 10 Dec 2021 21:54:22 +0000 (13:54 -0800)]
add ternlogi to shift_rot formal test
Jacob Lifshay [Fri, 10 Dec 2021 21:32:46 +0000 (13:32 -0800)]
fix shift_rot formal proof
Jacob Lifshay [Fri, 10 Dec 2021 21:32:20 +0000 (13:32 -0800)]
add formal_test_temp to .gitignore
Tobias Platen [Fri, 10 Dec 2021 20:29:07 +0000 (21:29 +0100)]
use icache_read in one place
Tobias Platen [Fri, 10 Dec 2021 19:30:14 +0000 (20:30 +0100)]
test_loadstore1.py: begin code deduplication
Luke Kenneth Casson Leighton [Thu, 9 Dec 2021 20:47:52 +0000 (20:47 +0000)]
add some examination of the failed-fetched instruction
and check that it is a perm_error and an instruction fault
Luke Kenneth Casson Leighton [Thu, 9 Dec 2021 20:15:40 +0000 (20:15 +0000)]
add some debug string info to gtkwave
Tobias Platen [Thu, 9 Dec 2021 17:32:13 +0000 (18:32 +0100)]
implement main part of test_loadstore1_ifetch_invalid()
Tobias Platen [Thu, 9 Dec 2021 16:56:04 +0000 (17:56 +0100)]
cleanup test_loadstore1.py
Luke Kenneth Casson Leighton [Thu, 9 Dec 2021 15:45:33 +0000 (15:45 +0000)]
add I-Cache to FSM local variables
Luke Kenneth Casson Leighton [Thu, 9 Dec 2021 15:45:09 +0000 (15:45 +0000)]
wire fetch_failed from I-Cache to PowerDecoder2
informs PowerDecoder2 that an instruction fetch failed in MMU mode
Luke Kenneth Casson Leighton [Thu, 9 Dec 2021 15:06:07 +0000 (15:06 +0000)]
make icache accessible to core, working back to TestIssuer
Luke Kenneth Casson Leighton [Thu, 9 Dec 2021 09:53:25 +0000 (09:53 +0000)]
include SPR.TB in SPR FU
Jacob Lifshay [Thu, 9 Dec 2021 06:05:15 +0000 (22:05 -0800)]
add bitmanip tests
Jacob Lifshay [Thu, 9 Dec 2021 04:00:45 +0000 (20:00 -0800)]
add CommonPipeSpec.__getattr__ to forward attributes from parent_pspec
replaces CommonPipeSpec.draft_bitmanip
Jacob Lifshay [Thu, 9 Dec 2021 03:56:36 +0000 (19:56 -0800)]
add parent_pspec everywhere
Jacob Lifshay [Thu, 9 Dec 2021 03:49:42 +0000 (19:49 -0800)]
make argv handling more flexible
Jacob Lifshay [Thu, 9 Dec 2021 03:41:01 +0000 (19:41 -0800)]
format code
Luke Kenneth Casson Leighton [Wed, 8 Dec 2021 22:34:42 +0000 (22:34 +0000)]
got fed up of staring at magic constants in the MMU
created a Record RPTE from v3.0C Book III p1016 section 7.7.10.2
to interpret the page-table leaf entries in words/features rather than
magic offsets
Luke Kenneth Casson Leighton [Wed, 8 Dec 2021 21:32:03 +0000 (21:32 +0000)]
add special pagetable to ifetch_invalid with execute perms barred
Luke Kenneth Casson Leighton [Wed, 8 Dec 2021 21:30:17 +0000 (21:30 +0000)]
do not try priv_mode on the instruction fetch (not needed)
Luke Kenneth Casson Leighton [Wed, 8 Dec 2021 21:29:51 +0000 (21:29 +0000)]
add an example pagetable where executable permission is barred
Tobias Platen [Wed, 8 Dec 2021 21:03:55 +0000 (22:03 +0100)]
begin working on _test_loadstore1_ifetch_invalid() inner function
Tobias Platen [Wed, 8 Dec 2021 20:53:11 +0000 (21:53 +0100)]
more work on test_loadstore1_ifetch_invalid()
Tobias Platen [Wed, 8 Dec 2021 20:19:13 +0000 (21:19 +0100)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Wed, 8 Dec 2021 20:18:34 +0000 (21:18 +0100)]
add skeleton for test_loadstore1_ifetch_invalid()
Luke Kenneth Casson Leighton [Wed, 8 Dec 2021 20:04:45 +0000 (20:04 +0000)]
check that no exception occurs in the virtual-memory-instruction-fetch
Luke Kenneth Casson Leighton [Wed, 8 Dec 2021 19:08:32 +0000 (19:08 +0000)]
add OP_FETCH_FAILED to MMU Function Unit
Luke Kenneth Casson Leighton [Wed, 8 Dec 2021 16:43:43 +0000 (16:43 +0000)]
make LoadStore1 intsr_fault a "captured flag" - strictly speaking
there should be separate FSM states for MMU_LOOKUP_ICACHE but hey
Luke Kenneth Casson Leighton [Wed, 8 Dec 2021 16:42:32 +0000 (16:42 +0000)]
remove MSR and add CIA to MMU Input Record
Luke Kenneth Casson Leighton [Wed, 8 Dec 2021 16:09:28 +0000 (16:09 +0000)]
add instr_fault to LoadStore1 FSM
this includes stopping LoadStore1 from processing (accepting)
incoming LDST operations via its PortInterface
Luke Kenneth Casson Leighton [Wed, 8 Dec 2021 16:06:27 +0000 (16:06 +0000)]
add new PortInterfaceBase external_busy() option
this allows e.g. instruction fault to stop LD/STs from being accepted
Jacob Lifshay [Wed, 8 Dec 2021 01:55:46 +0000 (17:55 -0800)]
add comment about draft instructions
Jacob Lifshay [Wed, 8 Dec 2021 01:51:14 +0000 (17:51 -0800)]
account for Mock absurdities
Luke Kenneth Casson Leighton [Tue, 7 Dec 2021 16:07:18 +0000 (16:07 +0000)]
complete the i-cache fetch through the MMU, including doing an
instruction-side TLB lookup
Luke Kenneth Casson Leighton [Tue, 7 Dec 2021 15:51:34 +0000 (15:51 +0000)]
set separate "iside" signal in LoadStore1 to not confuse it
with instr_fault (exception flag). starting to experiment getting
instruction-side MMU requests to trigger
Luke Kenneth Casson Leighton [Tue, 7 Dec 2021 14:55:50 +0000 (14:55 +0000)]
start extending icache loadstore test
Luke Kenneth Casson Leighton [Tue, 7 Dec 2021 14:55:26 +0000 (14:55 +0000)]
whoops another serious error in the CacheTagArray
valid is of length NUM_WAYS not 1
Luke Kenneth Casson Leighton [Tue, 7 Dec 2021 14:30:12 +0000 (14:30 +0000)]
add first i-cache fetch (non-virtual), no MMU lookup, copied unit
test from basic one in soc/experiment/icache.py
Luke Kenneth Casson Leighton [Tue, 7 Dec 2021 13:37:15 +0000 (13:37 +0000)]
code-comments
Luke Kenneth Casson Leighton [Tue, 7 Dec 2021 13:32:16 +0000 (13:32 +0000)]
add in I-Cache into LoadStore1 - presently unused - so as to start on
a unit test (test_loadstore1.py). this is not a normal place to start,
but I-Cache links cross-wise into so many other dependent areas that
it is quite tricky