swrast: allocate swrast_texture_image::ImageSlices array if needed

Fixes a segmentation fault in conform divzero.c test.
This happens when glTexImage(level, width=0, height=0) is called.  We
don't allocate texture memory in that case so the ImageSlices array
was never allocated.

Cc: "10.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: José Fonseca <jfonseca@vmware.com>

swrast: Fix vertex color in _swsetup_Translate()

Straightforward fix to properly load dest->color with color data, as
opposed to position data as previously implemented.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=27499
Cc: "10.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

gallivm: Fix wrong operator in lp_exec_default.

Courtesy of MSVC static code analyser.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

mesa/st: Handle empty frame-buffers without asserting.

Fixes assertion failures with radeonsi.

Tested-by: Marek Olšák <maraeo@gmail.com>

mesa/st: Fix pipe_framebuffer_state::height for PIPE_TEXTURE_1D_ARRAY.

This prevents buffer overflow w/ llvmpipe when running piglit

  bin/gl-3.2-layered-rendering-clear-color-all-types 1d_array single_level -fbo -auto

v2: Compute the framebuffer size as the minimum size, as pointed out by
Brian;  compacted code;  ran piglit quick test list (with no
regressions.)

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

util/u_debug: Pass correct size to strncat.

Courtesy of Clang static analyzer.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

freedreno/a3xx: fix TOTALATTRTOVS

In cases where varying fetches are optimized away (just pass-through in
vertex shader, but unused in fragment shader) we need to calculate the
correct TOTALATTROVS based on the actual number of varyings fetched,
otherwise lockup.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

i965: Make Broadwell HiZ path arrange for TC flushes.

HiZ operations make the depth/render caches out of sync with the sampler
caches.  We need to arrange for a TC flush to happen before the target
buffer is used by the sampler.  Calling brw_render_cache_set_add_bo
makes that happen.

On previous generations, brw_blorp_exec took care of flushing the
texture cache by calling intel_batchbuffer_emit_mi_flush after doing
any rendering.  If we were to use the normal drawing path, then
brw_postdraw_set_buffers_need_resolve would handle this.

On Broadwell, we don't use BLORP, and we don't emit a rectangle
primitive via the normal drawing path.  The 3DSTATE_WM_HZ_OP and
PIPE_CONTROL implicitly make drawing happen.  So, none of our existing
code makes this flush happen - we need to do it directly.

Fixes 11 Piglit copyteximage subtests.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77223
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77226
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

i965: Use uint16_t for control/src index tables.

No need to use 32-bits to store 15 and 12.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

i965/disasm: Fix s/xoo/xor/ typo.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/disasm: Remove tables with obvious mappings.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa/st: enable EXT_shader_integer_mix when NativeIntegers is on

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/omx/enc: implement frame reordering and B-frames

Signed-off-by: Christian König <christian.koenig@amd.com>

st/omx/enc: replace omx buffer with texture buffer

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeonsi: Fix calculation of number of banks for SI

The way cik_num_banks() was calculating the index only makes sense for
the CIK specific macrotile mode array. For SI, we need to use the tile
mode index directly.

This happened to work most of the time because most of the SI tiling
modes use the same number of banks.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

glsl: Only allow `invariant` on shader in/out between stages.

Previously this was special-cased for VS and FS; it never got updated
when geometry shaders came along. Generalize using is_varying_var() so
this won't be broken again with tessellation.

Note that there are two copies of the logic for `invariant`: It can be
present as part of a new declaration, and also as a redeclaration of an
existing variable or block member.

Fixes the four new piglits:
   spec/glsl-1.50/compiler/invariant-qualifier-*.geom

Note for stable: This won't quite pick cleanly due to whitespace and
state->target -> state->stage renames. Should be straightforward
adjustments though.

Cc: "10.0 10.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

svga: move draw debug code into separate function

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

mesa: move declaration before code

To fix MSVC build.

mesa: Fix error code generation in glReadPixels()

Section 4.3.1, page 220, of OpenGL 3.3 specification explains
the error conditions for glreadPixels():

   "If the format is DEPTH_STENCIL, then values are taken from
    both the depth buffer and the stencil buffer. If there is
    no depth buffer or if there is no stencil buffer, then the
    error INVALID_OPERATION occurs. If the type parameter is
    not UNSIGNED_INT_24_8 or FLOAT_32_UNSIGNED_INT_24_8_REV,
    then the error INVALID_ENUM occurs."

Fixes failing Khronos CTS test packed_depth_stencil_error.test

V2: Avoid code duplication

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: Add an error condition in glGetFramebufferAttachmentParameteriv()

From the OpenGL 4.4 spec page 275:
  "If pname is FRAMEBUFFER_ATTACHMENT_COMPONENT_TYPE, param will
   contain the format of components of the specified attachment,
   one of FLOAT, INT, UNSIGNED_INT, SIGNED_NORMALIZED, or
   UNSIGNED_NORMALIZED for floating-point, signed integer,
   unsigned integer, signed normalized fixedpoint, or unsigned
   normalized fixed-point components respectively. If no data
   storage or texture image has been specified for the attachment,
   param will contain NONE. This query cannot be performed for a
   combined depth+stencil attachment, since it does not have a
   single format."

Fixes Khronos CTS test: packed_depth_stencil_parameters.test

Khronos Bug# 9170
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

libgl-gdi: silence unused variable warning when not using LLVM

docs: import 10.0.5 release notes and update links

docs: import 10.1.1 release notes, update links

mesa: fix GetStringi error message with correct function name

Signed-off-by: Benjamin Bellec <b.bellec@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Cc: <mesa-stable@lists.freedesktop.org>

st/mesa: fix invalid pointer use in st_texture_get_sampler_view()

The '**used' pointer was pointing into the stObj->sampler_views array.
If 'free' was null, we'd realloc that array, thus making the 'used'
pointer invalid.  This soon led to memory errors.

Just change the pointer to be '*used' so it points directly at the
pipe_sampler_view.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

glsl: Fix typo

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>

i965: Use ctx->Texture._MaxEnabledTexImageUnit for upper bound

Avoid looping over 32/48/96 (!!) tex image units every draw, most of
which we don't care about.

Improves performance on everyone's favorite not-a-benchmark by 2.9% on
Haswell.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: Track max enabled tex image unit

This gives us a better bound for some hot loops in the drivers than
MAX_COMBINED_TEXTURE_IMAGE_UNITS, which is ridiculously large on modern
hardware, and only getting worse as more shader stages are added.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

nouveau/codegen: add missing values for OP_TXLQ into the target arrays

Also rework things so that if someone were to add an opcode without
adjusting the values in these arrays, there will be a compilation error.

This fixes a few quadop-related piglit regressions since commit
d5faf8e78603.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: change logic for centering of eng2d blit when downsampling

We want to center the sample. The old code may have been correct given
the limited values of ms_x/y, but the new logic should be more
intuitive. Note that ms_x can only be 1/2 and ms_y can only be 0/1.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50: use 2d blit when src/dst have same number of samples

The 2D engine should be usable in more cases, but this fixes MS blits
between textures with the same MS settings. Otherwise a single sample is
selected to be the target texel value.

This allows other tests to work that render to a RB and then blit that
to a texture for input into a shader that uses sampler2DMS to verify it.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

gallium/docs: fix PIPE_CAP_ENDIANNESS delimiter, remove trailing spaces

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

mesa: update glext.h to version 20140313

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965/fs: Implement fs_inst::force_sechalf support on Broadwell.

Back when I originally wrote this code, force_sechalf was only used for
Gen4 code, so I didn't bother hooking it up.  However, it's used more
generally these days.  In particular, we use it for computing
gl_SamplePosition.

Fixes Piglit's spec/ARB_sample_shading/builtin-gl-sample-position tests.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77222
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

glsl: Allow explicit binding on atomics again

As of 943b2d52bf5, layout(binding) on an atomic would fail the assertion
here.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

radeonsi: fix num banks selection on SI for dma setup (v2)

The number of banks varies based on the tile mode index
just like CIK.

Bug:
https://bugs.freedesktop.org/show_bug.cgi?id=77533

v2: fix ordering for nbanks calculation for consistency

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

i965/fs: Reduce restrictions on interference in register coalescing.

We previously only allowed coalescing registers that interfere (i.e.,
whose live ranges overlap) if the destination register's live range was
entirely inside the source's live range. This is unnecessary -- we only
need to check for interfering writes in the intersection of their live
ranges.

total instructions in shared programs: 1639470 -> 1638453 (-0.06%)
instructions in affected programs:     84751 -> 83734 (-1.20%)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Give up in interference check if we see a WHILE.

Rather than any old control flow. Muchnick's algorithm just checks for
interfering writes between the MOV and the end of the program. Handling
this when you have backward branches is hard, so don't, but there's no
reason to bail if you see forward branches.

instructions in affected programs:     4270 -> 4248 (-0.52%)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Simplify interference scan in register coalescing.

We were starting at the beginning of the instruction list, rather than
with the MOV instruction itself. This allows us to coalesce after
control flow.

Excluding the shaders from an unreleased title, the shader-db results:

total instructions in shared programs: 1603791 -> 1594215 (-0.60%)
instructions in affected programs:     678772 -> 669196 (-1.41%)
GAINED:                                5
LOST:                                  0

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Unindent can_coalesce_vars().

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Recognize nop-MOV instructions early.

And avoid rewriting other instructions unnecessarily. Removes a few
self-moves we weren't able to handle because they were components of a
large VGRF.

instructions in affected programs:     830 -> 826 (-0.48%)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Only sweep NOPs if register coalescing made progress.

Otherwise there's nothing to do.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

r600g,radeonsi: don't skip the context flush if a fence should be returned

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77589

svga: fix comment for emit_adjusted_vertex_attribs()

svga: compute need_swvfetch in svga_create_vertex_elements_state()

This saves us doing it at state validation time.

Reviewed-by: Matthew McClure <mcclurem@vmware.com>

svga: add VS code to set attribute W component to 1

There's a few 3-component vertex attribute formats that have no
equivalent SVGA3D_DECLTYPE_x format.  Previously, we had to use
the swtnl code to handle them.  This patch lets us use hwtnl for
more vertex attribute types by fetching 3-component attributes as
4-component attributes and explicitly setting the W component to 1.

This lets us handle PIPE_FORMAT_R16G16B16_SNORM/UNORM and
PIPE_FORMAT_R8G8B8_UNORM vertex attribs without using the swtnl path.

Fixes piglit normal3b3s GL_SHORT test.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

svga: implement support for signed byte vertex attributes

There's no SVGA3D_DECLTYPE that directly corresponds to
PIPE_FORMAT_R8G8B8_SNORM.  Previously, we used the swtnl fallback
path to handle this but that's slow and causes invariance issues.
Now we fetch the attribute as SVGA3D_DECLTYPE_UBYTE4N and insert
some extra VS instructions to remap the attributes from the range
[0,1] to the range[-1,1].

Fixes Sauerbraten sw fallback.
Fixes piglit normal3b3s-invariance test.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

svga: move translated vertex declaration types into svga_velems_state

Now only translate the formats once in svga_create_vertex_elements_state().
And rename the array and use the proper SVGA3dDeclType type.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

Revert "svga: add work-around for Sauerbraten Z fighting issue"

This reverts commit c875d6e57a817bb6a8163a8a98ebd2768ee91848.

Conflicts:
src/gallium/drivers/svga/svga_context.c

This work-around will no longer be needed after the next patch
which properly supports signed-byte vertex attributes.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

svga: use new inst_token_setp() helper function

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

svga: use new inst_token_predicated() helper function

Reviewed-by: Charmaine Lee <charmainel@vmware.com>

i965: Retype pre-Gen6 varying pull load destination to UW.

This sets up the proper execution mask for sends in SIMD16 mode.

Fixes Piglit's glsl-fs-normalmatrix, glsl-fs-uniform-array-2,
glsl-fs-uniform-array-6, and glsl-fs-uniform-array-7 on Ironlake,
which regressed when I enabled SIMD16 pull parameter support in
commit b207e88b25e526d0f1ada7b19605b880a27866dc.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

mesa: Fix error condition for multisample proxy texture targets

Fixes failures in Khronos OpenGL CTS test proxy_textures_invalid_samples

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Add glBlitFramebuffer to commands affected by conditional rendering

Fixes failures in Khronos OpenGL CTS test conditional_render_test9

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

swrast: Add glBlitFramebuffer to commands affected by conditional rendering

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

i965: Fix component mask and varying_to_slot mapping for gl_ViewportIndex

gl_ViewportIndex doesn't get its own varying slot. It is stored
in VARYING_SLOT_PSIZ.z. This patch fixes the issue for both gen7
and gen8 because gen7_upload_3dstate_so_decl_list() is shared
between them.

Fixes failures in OpenGL Khronos CTS test transform_feedback_builtins.
Makes new piglit test glsl-1.50-transform-feedback-builtins pass for
'gl_ViewportIndex'.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Fix component mask and varying_to_slot mapping for gl_Layer

gl_Layer doesn't get its own varying slot. It is stored in
VARYING_SLOT_PSIZ.y. This patch fixes the issue for both gen7
and gen8 because gen7_upload_3dstate_so_decl_list() is shared
between them.

Fixes failures in OpenGL Khronos CTS test transform_feedback_builtins.
Makes new piglit test glsl-1.50-transform-feedback-builtins pass for
'gl_Layer'.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Put an assertion to check valid varying_to_slot[varying]

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

radeonsi: Added Diag Handler to receive LLVM Error messages

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

winsys/radeon: remove some unused code

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

winsys/radeon: remove is_handle_added array

Use index -1 if a buffer is not added.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

winsys/radeon: remove local variable reloc from radeon_get_reloc

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

winsys/radeon: remove parameter reloc from radeon_get_reloc

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

util: Add __declspec(noreturn) to _debug_assert_fail().

Mostly for consistency; as MSVC's static source code analysis doesn't
seem to rely on assertions, but instead on different kind of source
annotations( http://msdn.microsoft.com/en-us/library/hh916383.aspx ).

Reviewed-by: Brian Paul <brianp@vmware.com>

auxiliary/os,auxiliary/util: Fix the `‘noreturn’ function does return` warning.

Now that _debug_assert_fail() has the noreturn attribute, it is better
that execution truly never returns.  Not just for sake of silencing the
warning, but because the code at the return IP address may be invalid or
lead to inconsistent results.

This removes support for the GALLIUM_ABORT_ON_ASSERT debugging
environment variable, but between the usefulness of
GALLIUM_ABORT_ON_ASSERT and better static code analysis I think better
static code analysis wins.

Reviewed-by: Brian Paul <brianp@vmware.com>

scons: Enable building through Clang Static Analyzer.

Same intent as commit a45a50a4828e1357e9555474bc127c5585b3a420,
but this the C compiler is detected via C-preprocessor macros,
similar to how autotools do it, as that seems to be the most
reliable method.

Reviewed-by: Brian Paul <brianp@vmware.com>

gallium glsl: Fix crash with piglit fs-deref-literal-array-of-structs.shader_test

This allows the following shader code to work without a weird crash:

struct Foo {
  int value[1];
};

int actual_value = Foo[2](Foo(int[1](100)), Foo(int[1](200)))[i].value[0];

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>

nouveau/vdec: small fixes to h264 handling

nouveau_vp3_inter_sizes requires sliec_count as argument just
as the other places that call it from h264 code do. Hopefully
fixes something.

Fix the status_vp code to allow status == 0 too, when processing
hasn't started yet.

set h264->second_field correctly.

st/xa: Cache render target surface

Otherwise it will trick the gallium driver into thinking that the render
target has actually changed (due to different pipe_surface pointing to
same underlying pipe_resource).  This is really badness for tiling GPUs
like adreno.

This also appears to fix a rendering error with Motif on vmwgfx.
Why that is is still under investigation.

Based on an idea by Rob Clark.

Cc: "10.0 10.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Rob Clark <robclark@freedesktop.org>

st/xa: scissor to help tilers

Keep track of the maximal bounds of all the operations and set scissor
accordingly.  For tiling GPU's this can be a big win by reducing the
memory bandwidth spent moving pixels from system memory to tile buffer
and back.

You could imagine being more sophisticated and splitting up disjoint
operations.  But this simplistic approach is good enough for the common
cases.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>

st/xa: remove unneeded args

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>

glsl: Small optimization for constant conditionals

Once the relevant branch has been identified do not iterate over the
instructions in the branch, do a linked list insertion instead to avoid the
loop.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl: Fix incorrect indentation.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>

meta: Clip src/dest rects in BlitFramebuffer, using the scissor

Fixes piglit's fbo-blit-stretch test on drivers which use the meta path.
(i965: should fix Broadwell, but also fixes Sandybridge/Ivybridge/Haswell
since this test falls off the blorp path now due to format conversion)

V2: Use scissor instead of just mangling the rects, to avoid texcoord
rounding problems. (Thanks Marek)

V3: Rebase on Eric's CTSI meta changes; re-add _mesa_update_state in the
CTSI path so that _mesa_clip_blit sees the correct bounds.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77414
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Tested-by: Anuj Phogat <anuj.phogat@gmail.com>

mesa: fix check for dummy renderbuffer in _mesa_FramebufferRenderbufferEXT()

According to the spec:
<renderbuffertarget> must be RENDERBUFFER and <renderbuffer>
should be set to the name of the renderbuffer object to be
attached to the framebuffer.  <renderbuffer> must be either
zero or the name of an existing renderbuffer object of type
<renderbuffertarget>, otherwise an INVALID_OPERATION error is
generated.

This patch changes the previous returned GL_INVALID_VALUE to
GL_INVALID_OPERATION.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76894

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>

i965: Don't make instructions with a null dest a barrier to scheduling.

Now that we properly track accumulator dependencies, the scheduler is
able to schedule instructions between the mach and mov in the common
the integer multiplication pattern:

   mul  acc0, x, y
   mach null, x, y
   mov  dest, acc0

Since a null destination implies no dependency on the destination, we
can also safely schedule instructions (that don't write the accumulator)
between the mul and mach.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Change fs_visitor::emit_lrp to use MAC for gen<6

This allows us to emit ADD/MUL/MAC instead of MUL/ADD/MUL/ADD,
saving one instruction and two temporary registers.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

i965/fs: Add support for the MAC instruction.

This allows us to generate the MAC (multiply-accumulate) instruction,
which can be used to implement some expressions in fewer instructions
than doing a series of MUL and ADDs.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

i965/vec4: Change vec4_visitor::emit_lrp to use MAC for gen<6

This allows us to emit ADD/MUL/MAC instead of MUL/ADD/MUL/ADD,
saving one instruction and two temporary registers.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

i965/vec4: Add support for the MAC instruction.

This allows us to generate the MAC (multiply-accumulate) instruction,
which can be used to implement some expressions in fewer instructions
than doing a series of MUL and ADDs.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

i965: Add writes_accumulator flag

Our hardware has an "accumulator" register, which can be used to store
intermediate results across multiple instructions.  Many instructions
can implicitly write a value to the accumulator in addition to their
normal destination register.  This is enabled by the "AccWrEn" flag.

This patch introduces a new flag, inst->writes_accumulator, which
allows us to express the AccWrEn notion in the IR.  It also creates a
n ALU2_ACC macro to easily define emitters for instructions that
implicitly write the accumulator.

Previously, we only supported implicit accumulator writes from the
ADDC, SUBB, and MACH instructions.  We always enabled them on those
instructions, and left them disabled for other instructions.

To take advantage of the MAC (multiply-accumulate) instruction, we
need to be able to set AccWrEn on other types of instructions.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

i965: Add is_accumulator() function.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

i965: Add reads_accumulator_implicitly() function.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: Add error condition for integer formats in glGetTexImage()

OpenGL 4.0 spec, page 306 suggests an INVALID_OPERATION in glGetTexImage
if :
   "format is one of the integer formats in table 3.3 and the internal
    format of the texture image is not integer, or format is not one of
    the integer formats in table 3.3 and the internal format is integer."

V2: Use helper function _mesa_is_format_integer()

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Add helper function _mesa_is_format_integer()

This function will be used in the following patch.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Fix glGetVertexAttribi(GL_VERTEX_ATTRIB_ARRAY_SIZE)

mesa currently returns 4 when GL_VERTEX_ATTRIB_ARRAY_SIZE is queried
for a vertex array initially set up with size=GL_BGRA. This patch
makes changes to return size=GL_BGRA as required by the spec.

Fixes Khronos OpenGL CTS test: vertex_array_bgra_basic.test

V2: Use array->Format instead of adding a new variable

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>

glsl: Fix copy-paste error in linker_warning()

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

r600g: Disable LLVM by default at runtime for graphics

For graphics, the LLVM compiler backend currently has many shortcomings
compared to the non-LLVM one. E.g. it can't handle geometry shaders yet,
but that's just the tip of the iceberg.

So building Mesa with --enable-r600-llvm-compiler is currently not
recommended for anyone who doesn't want to work on fixing those issues.
However, for protection of users who end up enabling it anyway for some
reason, let's disable the LLVM backend at runtime by default. It can be
enabled with the environment variable R600_DEBUG=llvm.

Cc: "10.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

gallivm: fix compilation with llvm 3.5 r206241+

Just adjust to the ever-changing API, pass in MCContext when creating the
MCDisassembler.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

Revert "scons: Enable building through Clang Static Analyzer."

This reverts commit a45a50a4828e1357e9555474bc127c5585b3a420.

Unfortunately gcc dumps argv[0] as the first word of --version, so it is
unreliable for detecting gcc.

In particular `cc --version` and `i686-w64-mingw32-gcc --version` give
wrong results.

A better solution needs to be found -- most likely using C-preprocessing
like autotools does.  Revert for now.

r600g,radeonsi: share some of gfx flush code

Reviewed-by: Christian König <christian.koenig@amd.com>

r600g,radeonsi: share r600_flush_from_st

Reviewed-by: Christian König <christian.koenig@amd.com>

r600g: merge r600_flush with r600_context_flush

Reviewed-by: Christian König <christian.koenig@amd.com>

radeonsi: merge si_flush with si_context_flush

This also removes si_flush_gfx_ring.

Reviewed-by: Christian König <christian.koenig@amd.com>

gallium/radeon: create and return a fence in the flush function

All flush functions get a fence parameter. cs_create_fence is removed.

Reviewed-by: Christian König <christian.koenig@amd.com>

r600g: remove redundant r600_flush_dma_from_winsys

Reviewed-by: Christian König <christian.koenig@amd.com>

winsys/radeon: fold cs_set_flush_callback into cs_create

Reviewed-by: Christian König <christian.koenig@amd.com>

radeonsi: cleanup redundant computation of flush flags and rename a function

Reviewed-by: Christian König <christian.koenig@amd.com>

r600g: remove redundant r600_flush_from_winsys

Reviewed-by: Christian König <christian.koenig@amd.com>

winsys/radeon: remove cs_write_reloc, add simpler cs_get_reloc

The only difference is that it doesn't write to the CS and only returns
the index.

Reviewed-by: Christian König <christian.koenig@amd.com>