mesa.git
5 years agoradeonsi/gfx10: fix the legacy pipeline by storing as_ngg in the shader cache
Marek Olšák [Tue, 20 Aug 2019 17:20:07 +0000 (13:20 -0400)]
radeonsi/gfx10: fix the legacy pipeline by storing as_ngg in the shader cache

It could load an NGG shader when we want a legacy shader and vice versa.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
5 years agoiris: Delete dead prototype
Kenneth Graunke [Tue, 27 Aug 2019 20:14:53 +0000 (13:14 -0700)]
iris: Delete dead prototype

5 years agoRevert "panfrost: Free all block/instruction objects before leaving midgard_compile_s...
Boris Brezillon [Tue, 27 Aug 2019 18:07:03 +0000 (20:07 +0200)]
Revert "panfrost: Free all block/instruction objects before leaving midgard_compile_shader_nir()"

This reverts commit 5882e0def97a47aff050f5a3f412b97a7f440e27.

This commit causes a segfault.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
5 years agopanfrost: Make sure bundle.instructions[] contains valid instructions
Boris Brezillon [Tue, 27 Aug 2019 09:12:02 +0000 (11:12 +0200)]
panfrost: Make sure bundle.instructions[] contains valid instructions

Add an assert() in schedule_bundle() to make sure all instruction
pointers in bundle.instructions[] are valid.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopanfrost: Free all block/instruction objects before leaving midgard_compile_shader_nir()
Boris Brezillon [Tue, 13 Aug 2019 23:56:30 +0000 (01:56 +0200)]
panfrost: Free all block/instruction objects before leaving midgard_compile_shader_nir()

Right now we're leaking all block and instruction objects allocated by
the compiler. Let's clean things up before leaving
midgard_compile_shader_nir().

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopanfrost: Free the instruction object in mir_remove_instruction()
Boris Brezillon [Tue, 13 Aug 2019 23:54:24 +0000 (01:54 +0200)]
panfrost: Free the instruction object in mir_remove_instruction()

To avoid memory leaks.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agoscons: add support for MAJOR_IN_{MKDEV,SYSMACROS}
Eric Engestrom [Thu, 22 Aug 2019 11:12:20 +0000 (12:12 +0100)]
scons: add support for MAJOR_IN_{MKDEV,SYSMACROS}

src/gallium/winsys/svga/drm/vmw_screen.c: In function ‘vmw_dev_compare’:
src/gallium/winsys/svga/drm/vmw_screen.c:48:12: warning: implicit declaration of function ‘major’ [-Wimplicit-function-declaration]
   48 |    return (major(*(dev_t *)key1) == major(*(dev_t *)key2) &&
      |            ^~~~~
src/gallium/winsys/svga/drm/vmw_screen.c:49:12: warning: implicit declaration of function ‘minor’ [-Wimplicit-function-declaration]
   49 |            minor(*(dev_t *)key1) == minor(*(dev_t *)key2)) ? 0 : 1;
      |            ^~~~~

That file (and many others) already has the proper #include with their
respective guards, but scons wasn't defining them, resulting in implicit
functions being used instead (and an always-true check that's probably
breaking something down the line).

Note that I'm cheating a bit here because Scons doesn't seem to have
a clean way to detect the existence of major() et al. as functions or
macros, so I'm taking the shortcut of just detecting the presence of the
header and assuming its contents is what we expect.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-By: Jose Fonseca <jfonseca@vmware.com>
5 years agoradv: make use of has_ls_vgpr_init_bug
Samuel Pitoiset [Fri, 23 Aug 2019 06:55:53 +0000 (08:55 +0200)]
radv: make use of has_ls_vgpr_init_bug

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoac: add has_ls_vgpr_init_bug to ac_gpu_info
Samuel Pitoiset [Fri, 23 Aug 2019 06:52:07 +0000 (08:52 +0200)]
ac: add has_ls_vgpr_init_bug to ac_gpu_info

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoac: add has_msaa_sample_loc_bug to ac_gpu_info
Samuel Pitoiset [Fri, 23 Aug 2019 06:50:06 +0000 (08:50 +0200)]
ac: add has_msaa_sample_loc_bug to ac_gpu_info

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoac: add rbplus_allowed to ac_gpu_info
Samuel Pitoiset [Wed, 21 Aug 2019 09:32:25 +0000 (11:32 +0200)]
ac: add rbplus_allowed to ac_gpu_info

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoac: add has_tc_compat_zrange_bug to ac_gpu_info
Samuel Pitoiset [Wed, 21 Aug 2019 09:21:05 +0000 (11:21 +0200)]
ac: add has_tc_compat_zrange_bug to ac_gpu_info

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoac: add has_gfx9_scissor_bug to ac_gpu_info
Samuel Pitoiset [Tue, 20 Aug 2019 15:38:43 +0000 (17:38 +0200)]
ac: add has_gfx9_scissor_bug to ac_gpu_info

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoac: add cpdma_prefetch_writes_memory to ac_gpu_info
Samuel Pitoiset [Tue, 20 Aug 2019 15:20:42 +0000 (17:20 +0200)]
ac: add cpdma_prefetch_writes_memory to ac_gpu_info

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoac: add has_out_of_order_rast to ac_gpu_info
Samuel Pitoiset [Tue, 20 Aug 2019 15:16:41 +0000 (17:16 +0200)]
ac: add has_out_of_order_rast to ac_gpu_info

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoac: add has_load_ctx_reg_pkt to ac_gpu_info
Samuel Pitoiset [Tue, 20 Aug 2019 15:15:46 +0000 (17:15 +0200)]
ac: add has_load_ctx_reg_pkt to ac_gpu_info

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoac: add has_rbplus to ac_gpu_info
Samuel Pitoiset [Fri, 2 Aug 2019 10:21:04 +0000 (12:21 +0200)]
ac: add has_rbplus to ac_gpu_info

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoac: add has_dcc_constant_encode to ac_gpu_info
Samuel Pitoiset [Fri, 2 Aug 2019 10:16:54 +0000 (12:16 +0200)]
ac: add has_dcc_constant_encode to ac_gpu_info

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoac: add has_distributed_tess to ac_gpu_info
Samuel Pitoiset [Fri, 2 Aug 2019 10:13:20 +0000 (12:13 +0200)]
ac: add has_distributed_tess to ac_gpu_info

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoac: add has_clear_state to ac_gpu_info
Samuel Pitoiset [Fri, 2 Aug 2019 10:10:43 +0000 (12:10 +0200)]
ac: add has_clear_state to ac_gpu_info

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agoac: drop llvm8 from some load/store helpers
Samuel Pitoiset [Fri, 23 Aug 2019 06:22:51 +0000 (08:22 +0200)]
ac: drop llvm8 from some load/store helpers

Cleanup.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agogallivm: fix appveyor build after images changes
Dave Airlie [Tue, 27 Aug 2019 03:36:03 +0000 (13:36 +1000)]
gallivm: fix appveyor build after images changes

5 years agodocs: add shader image extensions for llvmpipe
Dave Airlie [Sat, 20 Jul 2019 04:30:14 +0000 (14:30 +1000)]
docs: add shader image extensions for llvmpipe

v1.1: fix typo in llvmpipe name (ajax)

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
5 years agollvmpipe: enable ARB_shader_image_load_store
Dave Airlie [Sat, 20 Jul 2019 04:29:00 +0000 (14:29 +1000)]
llvmpipe: enable ARB_shader_image_load_store

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
5 years agollvmpipe: flush on api memorybarrier.
Dave Airlie [Thu, 22 Aug 2019 01:28:40 +0000 (11:28 +1000)]
llvmpipe: flush on api memorybarrier.

Until we have somewhere we can do better, just hit it with a hammer.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
5 years agogallivm: add memory barrier support
Dave Airlie [Wed, 21 Aug 2019 00:19:16 +0000 (10:19 +1000)]
gallivm: add memory barrier support

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
5 years agogallivm: add support for fences api on older llvm
Dave Airlie [Wed, 21 Aug 2019 06:43:55 +0000 (16:43 +1000)]
gallivm: add support for fences api on older llvm

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
5 years agollvmpipe: bind vertex/geometry shader images
Dave Airlie [Sat, 20 Jul 2019 04:28:45 +0000 (14:28 +1000)]
llvmpipe: bind vertex/geometry shader images

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
5 years agollvmpipe: add fragment shader image support
Dave Airlie [Sat, 20 Jul 2019 04:28:23 +0000 (14:28 +1000)]
llvmpipe: add fragment shader image support

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
5 years agodraw: add vs/gs images support
Dave Airlie [Sat, 20 Jul 2019 04:26:48 +0000 (14:26 +1000)]
draw: add vs/gs images support

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
5 years agogallivm: add image load/store/atomic support
Dave Airlie [Fri, 19 Jul 2019 09:06:48 +0000 (19:06 +1000)]
gallivm: add image load/store/atomic support

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
5 years agogallivm/tgsi: add image interface to tgsi builder
Dave Airlie [Fri, 19 Jul 2019 06:33:03 +0000 (16:33 +1000)]
gallivm/tgsi: add image interface to tgsi builder

This adds the callbacks for the driver/gallium binding for
image operations.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
5 years agollvmpipe: introduce image jit type to fragment shader jit.
Dave Airlie [Fri, 19 Jul 2019 06:29:10 +0000 (16:29 +1000)]
llvmpipe: introduce image jit type to fragment shader jit.

This adds the image type to the fragment shader jit context

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
5 years agodraw: add jit image type for vs/gs images.
Dave Airlie [Fri, 19 Jul 2019 06:28:12 +0000 (16:28 +1000)]
draw: add jit image type for vs/gs images.

This introduces the jit image type into the jit interface
for vertex/geom shaders

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
5 years agollvmpipe: move the fragment shader variant key to dynamic length.
Dave Airlie [Fri, 19 Jul 2019 06:07:47 +0000 (16:07 +1000)]
llvmpipe: move the fragment shader variant key to dynamic length.

This mirrors the vs/gs keys, and will be needed when adding images
support.

The const changes also mirror how the draw code work (as is needed
when we add images)

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
5 years agogallivm: add a basic image limit
Dave Airlie [Fri, 19 Jul 2019 05:52:14 +0000 (15:52 +1000)]
gallivm: add a basic image limit

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
5 years agollvmpipe: handle early test property.
Dave Airlie [Fri, 19 Jul 2019 05:45:22 +0000 (15:45 +1000)]
llvmpipe: handle early test property.

Also handle setting late for shaders that use stores

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
5 years agogallivm: move first/last level jit texture members.
Dave Airlie [Fri, 19 Jul 2019 05:04:55 +0000 (15:04 +1000)]
gallivm: move first/last level jit texture members.

This lets us create an image structure with the same basic
types as the texture one.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
5 years agogallivm: handle helper invocation (v2)
Dave Airlie [Thu, 4 Jul 2019 01:33:22 +0000 (11:33 +1000)]
gallivm: handle helper invocation (v2)

Just invert the exec_mask to get if this is a helper or not.

v2: get the bld mask (Roland)

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
5 years agogallivm: make lp_build_float_to_r11g11b10 take a const src
Dave Airlie [Sun, 30 Jun 2019 20:49:59 +0000 (06:49 +1000)]
gallivm: make lp_build_float_to_r11g11b10 take a const src

This allows using it with a const src later.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
5 years agollvmpipe: refactor jit type creation
Dave Airlie [Fri, 28 Jun 2019 21:34:18 +0000 (07:34 +1000)]
llvmpipe: refactor jit type creation

This just cleans the code up so the texture/sampler type
creation can be reused.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
5 years agogallivm: fix atomic compare-and-swap
Dave Airlie [Tue, 20 Aug 2019 05:44:50 +0000 (15:44 +1000)]
gallivm: fix atomic compare-and-swap

Not sure how I missed this before, but compswap was hitting an
assert here as it is it's own special case.

Fixes: b5ac381d8f ("gallivm: add buffer operations to the tgsi->llvm conversion.")
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
5 years agointel/fs: grab fail_msg from v32 instead of v16 when v32->run_cs fails
Paulo Zanoni [Wed, 14 Aug 2019 00:02:13 +0000 (17:02 -0700)]
intel/fs: grab fail_msg from v32 instead of v16 when v32->run_cs fails

Looks like a copy/paste error. This patch prevents a segfault when
running the following on BDW:

    INTEL_DEBUG=no8,no16,do32 ./deqp-vk -n \
        dEQP-VK.subgroups.arithmetic.compute.subgroupmin_dvec4

For the curious, the message we're getting is:

    CS compile failed: Failure to register allocate.  Reduce number
    of live scalar values to avoid this.

Fixes: 864737ce6cd5 ("i965/fs: Build 32-wide compute shader when needed.")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
5 years agopan/midgard: Fix invert fusing with r26
Alyssa Rosenzweig [Mon, 26 Aug 2019 19:48:14 +0000 (12:48 -0700)]
pan/midgard: Fix invert fusing with r26

The invert wasn't applying (correctly) due to the issues addressed here.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/midgard: Fold ssa_args into midgard_instruction
Alyssa Rosenzweig [Mon, 26 Aug 2019 18:58:27 +0000 (11:58 -0700)]
pan/midgard: Fold ssa_args into midgard_instruction

This is just a bit of refactoring to simplify MIR.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agogallium: Add the ASTC 3D formats.
Eric Anholt [Wed, 14 Aug 2019 19:23:46 +0000 (12:23 -0700)]
gallium: Add the ASTC 3D formats.

No driver implements them yet, but this is a long way toward gallium
having matching format enums for Mesa formats.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agogallium: Add block depth to the format utils.
Eric Anholt [Wed, 14 Aug 2019 19:16:46 +0000 (12:16 -0700)]
gallium: Add block depth to the format utils.

I decided not to update nblocks() with a depth arg as the callers
wouldn't be doing ASTC 3D.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agogallium: Add a block depth field to the u_formats table.
Eric Anholt [Wed, 14 Aug 2019 19:09:04 +0000 (12:09 -0700)]
gallium: Add a block depth field to the u_formats table.

To add ASTC 3D compression formats, we need to be able to express the
block depth.  While I'm touching every line, line up the columns of
the CSV again as they've drifted over time.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
5 years agopan/midgard: Add imov->fmov optimization
Alyssa Rosenzweig [Fri, 23 Aug 2019 23:14:13 +0000 (16:14 -0700)]
pan/midgard: Add imov->fmov optimization

When moving constants, if switching to a floating-point representation
doesn't break anything, we'd rather have an fmov than an imov,
permitting inlining the constant in many circumstances.

total quadwords in shared programs: 3408 -> 3366 (-1.23%)
quadwords in affected programs: 1188 -> 1146 (-3.54%)
helped: 41
HURT: 0
helped stats (abs) min: 1 max: 2 x̄: 1.02 x̃: 1
helped stats (rel) min: 0.19% max: 25.00% x̄: 9.65% x̃: 11.11%
95% mean confidence interval for quadwords value: -1.07 -0.98
95% mean confidence interval for quadwords %-change: -11.38% -7.93%
Quadwords are helped.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/midgard: Switch constants to uint32
Alyssa Rosenzweig [Fri, 23 Aug 2019 23:02:49 +0000 (16:02 -0700)]
pan/midgard: Switch constants to uint32

Storing constants as float doesn't make sense when we have integer
instructions; better to switch to be integer natively and coerce to/from
float rather than the opposite.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agoisl: Don't set UnormPathInColorPipe for integer surfaces.
Kenneth Graunke [Sat, 24 Aug 2019 00:32:06 +0000 (17:32 -0700)]
isl: Don't set UnormPathInColorPipe for integer surfaces.

This fixes dEQP-GLES3.functional.texture.specification subtests on iris:

- texsubimage3d_depth.depth24_stencil8_2d_array
- texsubimage3d_depth.depth32f_stencil8_2d_array
- texsubimage3d_depth.depth_component32f_2d_array
- texsubimage3d_depth.depth_component24_2d_array
- texstorage2d.format.depth24_stencil8_2d
- texstorage2d.format.depth32f_stencil8_2d
- texstorage2d.format.depth_component24_2d
- texstorage2d.format.depth_component32f_2d
- texstorage3d.format.depth24_stencil8_2d_array
- texstorage3d.format.depth32f_stencil8_2d_array
- texstorage3d.format.depth_component24_2d_array
- texstorage3d.format.depth_component32f_2d_array

Here, something appears to be going wrong with having this bit set
during blorp_copy operations for texture upload, which override the
format to R8G8B8A8_UINT.

AFAICT this bit should have no effect for integer surfaces, as it has
to do with blending, and integer blending is not a thing.  So it should
be harmless to disable it.

The Windows driver appears to be setting this bit universally, so
I am unclear why we would need to.  Perhaps they simply haven't run
into this issue.

Fixes: f741de236b5 ("isl: Enable Unorm Path in Color Pipe")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agoisl: Drop UnormPathInColorPipe for buffer surfaces.
Kenneth Graunke [Sat, 24 Aug 2019 00:32:24 +0000 (17:32 -0700)]
isl: Drop UnormPathInColorPipe for buffer surfaces.

Jason suggested I remove this in review, and he's right.  AFAICT this
affects blending, and that just isn't going to happen on buffers.

Fixes: f741de236b5 ("isl: Enable Unorm Path in Color Pipe")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agopan/midgard, bifrost: Set lower_fdph = true
Alyssa Rosenzweig [Mon, 26 Aug 2019 14:46:43 +0000 (07:46 -0700)]
pan/midgard, bifrost: Set lower_fdph = true

fdph instructions show up in some desktop GL shaders.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agoradv: add mipmap support for the clear depth/stencil values
Samuel Pitoiset [Thu, 6 Jun 2019 15:30:17 +0000 (17:30 +0200)]
radv: add mipmap support for the clear depth/stencil values

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradv: add mipmap support for the TC-compat zrange bug
Samuel Pitoiset [Thu, 6 Jun 2019 15:23:17 +0000 (17:23 +0200)]
radv: add mipmap support for the TC-compat zrange bug

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradv: allocate metadata space for mipmapped depth/stencil images
Samuel Pitoiset [Fri, 23 Aug 2019 08:48:20 +0000 (10:48 +0200)]
radv: allocate metadata space for mipmapped depth/stencil images

For each mipmaps, the driver will store the clear values (8-bytes)
and the TC-compat zrange value (4-bytes).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradv: decompress mipmapped depth/stencil images during transitions
Samuel Pitoiset [Thu, 6 Jun 2019 10:03:10 +0000 (12:03 +0200)]
radv: decompress mipmapped depth/stencil images during transitions

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradv: add mipmaps support for decompress/resummarize
Samuel Pitoiset [Thu, 6 Jun 2019 09:57:19 +0000 (11:57 +0200)]
radv: add mipmaps support for decompress/resummarize

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradv: add radv_process_depth_image_layer() helper
Samuel Pitoiset [Thu, 6 Jun 2019 09:46:21 +0000 (11:46 +0200)]
radv: add radv_process_depth_image_layer() helper

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoac/nir: Remove gfx9_stride_size_workaround_for_atomic
Connor Abbott [Fri, 23 Aug 2019 08:46:53 +0000 (10:46 +0200)]
ac/nir: Remove gfx9_stride_size_workaround_for_atomic

The workaround was entirely in common code, and it's needed in radeonsi
too so just always do it when necessary. Fixes
KHR-GL45.shader_image_load_store.advanced-allStages-oneImage on gfx9
with LLVM 8.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
5 years agoac/nir: add a workaround for viewing a slice of 3D as a 2D image
Connor Abbott [Thu, 22 Aug 2019 15:09:21 +0000 (17:09 +0200)]
ac/nir: add a workaround for viewing a slice of 3D as a 2D image

GL and Vulkan allow you to bind a single layer of a 3D texture to a 2D
image, and we weren't implementing a workaround for that on gfx9 that
TGSI was. Copy it over.

Fixes KHR-GL45.shader_image_load_store.non-layered_binding with radeonsi
NIR.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoradv: fix getting the index type size for uint8_t
Samuel Pitoiset [Fri, 23 Aug 2019 07:23:21 +0000 (09:23 +0200)]
radv: fix getting the index type size for uint8_t

16-bit and 32-bit values match hardware values but 8-bit doesn't.

This fixes dEQP-VK.pipeline.input_assembly.* with 8-bit index.

Fixes: 372c3dcfdb8 ("radv: implement VK_EXT_index_type_uint8")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl
5 years agovirgl: fix format conversion for recent gallium changes.
Dave Airlie [Thu, 22 Aug 2019 06:30:11 +0000 (16:30 +1000)]
virgl: fix format conversion for recent gallium changes.

The virgl formats are fixed in time snapshots of the gallium ones,
we just need to provide a translation table between them when
we enter the hardware.

This fixes a regression since Eric renumbered the gallium table.

Fixes: c45c33a5a2 (gallium: Remove manual defining of PIPE_FORMAT enum values.)
Bugzilla: https://bugs.freedesktop.org/111454

v1 by Dave Airlie <airlied@redhat.com>
v2: virgl: Add a number of formats to the table that are used, e.g. for vertex
    attributes
v3: cover some more missing formats from a piglit run

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
5 years agovirgl: drop unused format field
Dave Airlie [Thu, 22 Aug 2019 06:20:39 +0000 (16:20 +1000)]
virgl: drop unused format field

5 years agolima/ppir: enable vectorize optimization
Erico Nunes [Sat, 10 Aug 2019 20:46:02 +0000 (22:46 +0200)]
lima/ppir: enable vectorize optimization

pp has vector units and some operations can be optimized when bundled
together.
Benchmarking this with piglit shaders shows that the instruction count
can be greatly reduced on many examples with vectorize.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
5 years agolima/ppir: lower selects to scalars
Erico Nunes [Sat, 10 Aug 2019 20:44:22 +0000 (22:44 +0200)]
lima/ppir: lower selects to scalars

nir vec4 fcsel assumes that each component of the condition will be used
to select the same component from the options, but pp can't implement
that since it only has 1 component for the condition.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
5 years agolima: fix ppir spill stack allocation
Erico Nunes [Fri, 23 Aug 2019 04:34:36 +0000 (06:34 +0200)]
lima: fix ppir spill stack allocation

The previous spill stack was fixed and too small, and caused instability
in programs requiring spilling for roughly more than one value.
This patch adds a dynamic calculation of the buffer size based on stack
utilization and switches it to a separate allocation at flush time that
will fit the shader that requires the largest buffer.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
5 years agointel/fs: Drop the gl_program from fs_visitor
Jason Ekstrand [Fri, 23 Aug 2019 20:33:24 +0000 (15:33 -0500)]
intel/fs: Drop the gl_program from fs_visitor

It's not used by anything anymore now that so much lowering has been
moved into NIR.  Sadly, we still need on in brw_compile_gs() for
geometry shaders on Sandy Bridge.  Short of a lot of pointless work,
that one's probably not going away.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
5 years agolima: move format handling to unified place
Qiang Yu [Sat, 17 Aug 2019 08:40:49 +0000 (16:40 +0800)]
lima: move format handling to unified place

Create a unified table to handle pipe format to texture
and render target format lookup.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
5 years agoradv: Change memory type order for GPUs without dedicated VRAM
Alex Smith [Sun, 2 Jun 2019 10:32:06 +0000 (11:32 +0100)]
radv: Change memory type order for GPUs without dedicated VRAM

Put the uncached GTT type at a higher index than the visible VRAM type,
rather than having GTT first.

When we don't have dedicated VRAM, we don't have a non-visible VRAM
type, and the property flags for GTT and visible VRAM are identical.
According to the spec, for types with identical flags, we should give
the one with better performance a lower index.

Previously, apps which follow the spec guidance for choosing a memory
type would have picked the GTT type in preference to visible VRAM (all
Feral games will do this), and end up with lower performance.

On a Ryzen 5 2500U laptop (Raven Ridge), this improves average FPS in
the Rise of the Tomb Raider benchmark by up to ~30%. Tested a couple of
other (Feral) games and saw similar improvement on those as well.

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: 19.2 <mesa-stable@lists.freedesktop.org>
(Bas: CCing this to 19.2-rc due to high impact and limited complexity)

5 years agolima/ppir: print register index and components number for spilled register
Vasily Khoruzhick [Tue, 20 Aug 2019 14:30:46 +0000 (07:30 -0700)]
lima/ppir: print register index and components number for spilled register

It can be useful for debugging purposes

Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
5 years agolima/ppir: add control flow support
Vasily Khoruzhick [Mon, 19 Aug 2019 06:37:23 +0000 (23:37 -0700)]
lima/ppir: add control flow support

This commit adds support for nir_jump_instr, if and loop
nir_cf_nodes.

Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
5 years agolima/ppir: add better liveness analysis
Vasily Khoruzhick [Mon, 19 Aug 2019 06:34:22 +0000 (23:34 -0700)]
lima/ppir: add better liveness analysis

Add better liveness analysis that was modelled after one in vc4.
It uses live ranges and is aware of multiple blocks which is prerequisite
for adding CF support

Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
5 years agolima/ppir: validate shader outputs
Vasily Khoruzhick [Fri, 23 Aug 2019 04:17:23 +0000 (21:17 -0700)]
lima/ppir: validate shader outputs

Mali4x0 supports only gl_FragColor. gl_FragDepth is not supported.
Check that we don't get anything but gl_FragColor in shader outputs.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
5 years agolima/ppir: turn store_color into ALU node
Vasily Khoruzhick [Thu, 22 Aug 2019 14:42:56 +0000 (07:42 -0700)]
lima/ppir: turn store_color into ALU node

We don't have a special OP to store color in PP, all we need to do is to
store gl_FragColor into reg0, thus it's just a mov and therefore ALU node.

Yet we still need to indicate that it's store_color op so regalloc ignores
its destination.

Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
5 years agolima/ppir: create ppir block for each corresponding NIR block
Vasily Khoruzhick [Mon, 19 Aug 2019 06:30:32 +0000 (23:30 -0700)]
lima/ppir: create ppir block for each corresponding NIR block

Create ppir block for each corresponding NIR block and populate
its successors. It will be used later in liveness analysis and
in CF support

Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
5 years agolima/ppir: add dummy op
Vasily Khoruzhick [Mon, 19 Aug 2019 06:03:57 +0000 (23:03 -0700)]
lima/ppir: add dummy op

We can get following from NIR:

(1) r1 = r2
(2) r2 = ssa1

Note that r2 is read before it's assigned, so there's no node for
it in comp->var_nodes. We need to create a dummy node in this case
which sole purpose is to hold ppir_dest with reg in it.

Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
5 years agolima/ppir: add write after read deps for registers
Vasily Khoruzhick [Mon, 19 Aug 2019 05:57:54 +0000 (22:57 -0700)]
lima/ppir: add write after read deps for registers

For cases like:

(1) r1 = r2
(2) r2 = ssa1

We need to add (1) as dependency of (2), otherwise scheduler may
reorder them.

Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
5 years agolima/ppir: fix ordering deps
Vasily Khoruzhick [Mon, 19 Aug 2019 05:51:34 +0000 (22:51 -0700)]
lima/ppir: fix ordering deps

There can be several root nodes, i.e.:

(1) r0 = r1
(2) r2 = r3
(3) branch if (ssa1)

We need to make (3) depend on (1) and (2), old code added
dependency only for (2), and (1) was kept as root node since there
is no branch/discard or store color between two movs.

Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
5 years agolima/ppir: set write mask for texture loads if dest is reg
Vasily Khoruzhick [Mon, 19 Aug 2019 05:48:22 +0000 (22:48 -0700)]
lima/ppir: set write mask for texture loads if dest is reg

Destination for texture load can be a reg, so we need to
set write mask in this case

Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
5 years agolima/ppir: add support for unconditional branches and condition negation
Vasily Khoruzhick [Tue, 28 May 2019 03:02:55 +0000 (20:02 -0700)]
lima/ppir: add support for unconditional branches and condition negation

We need 'negate' modifier for branch condition to minimize branching. Idea
is to generate following:

current_block: { ...; if (!statement) branch else_block; }
then_block: { ...; branch after_block; }
else_block: { ... }
after_block: { ... }

Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
5 years agolima/ppir: clone ld_{uni,tex,var} into each block
Vasily Khoruzhick [Tue, 20 Aug 2019 03:20:12 +0000 (20:20 -0700)]
lima/ppir: clone ld_{uni,tex,var} into each block

ppir_lower_load() and ppir_lower_load_texture() assume that node
is in the same block as its successors, fix it by cloning each
ld_uni and ld_tex to every block.

It also reduces register pressure since values never cross block
boundaries and thus never appear in live_in or live_out of any block,
so do it for varyings as well.

Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
5 years agolima/ppir: refactor const lowering
Vasily Khoruzhick [Wed, 24 Jul 2019 22:33:47 +0000 (15:33 -0700)]
lima/ppir: refactor const lowering

Const nodes are now cloned for each user, i.e. const is guaranteed to have
exactly one successor, so we can use ppir_do_one_node_to_instr() and
drop insert_to_each_succ_instr()

Tested-by: Andreas Baierl <ichgeh@imkreisrum.de>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
5 years agoanv: Only re-emit non-dynamic state that has changed.
Rafael Antognolli [Tue, 20 Aug 2019 00:01:10 +0000 (17:01 -0700)]
anv: Only re-emit non-dynamic state that has changed.

On commit f6e7de41d7b, we started emitting 3DSTATE_LINE_STIPPLE as part
of the non-dynamic state. That gets re-emitted every time we bind a new
VkPipeline. But that instruction is non-pipelined, and it caused a perf
regression of about 9-10% on Dota2.

This commit makes anv_dynamic_state_copy() return a mask with only the
state that has changed when copying it. 3DSTATE_LINE_STIPPLE won't be
emitted anymore unless it has changed, fixing the problem above.

v2: Improve commit message and add documentation about skipped checks
(Jason)

Fixes: f6e7de41d7b ("anv: Implement VK_EXT_line_rasterization")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agopan/decode: Validate and quiet helper invocation flag
Alyssa Rosenzweig [Thu, 22 Aug 2019 23:36:10 +0000 (16:36 -0700)]
pan/decode: Validate and quiet helper invocation flag

We can statically determine from the disassembly if helper invocations
will be needed, so we can validate the corresponding bit in the
cmdstream and thus avoid printing the bit itself in the decode.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agopan/midgard: Analyze helper invocations
Alyssa Rosenzweig [Thu, 22 Aug 2019 23:31:03 +0000 (16:31 -0700)]
pan/midgard: Analyze helper invocations

We check for texture ops which calculate derivatives (either explicitly
via dFd* or implicitly) and mark the shader as requiring helper
invocations.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
5 years agoutil: fix compilation on macos
Lionel Landwerlin [Fri, 23 Aug 2019 08:35:13 +0000 (10:35 +0200)]
util: fix compilation on macos

timespec_get() is not available on macos, we need to pull in the
include/c11/threads_posix.h helper.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103674
Fixes: e2d761de03 ("util: drop final reference to p_compiler.h")
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
5 years agoi965: Silence brw_blorp uninitialized warning
Caio Marcelo de Oliveira Filho [Fri, 23 Aug 2019 16:12:02 +0000 (09:12 -0700)]
i965: Silence brw_blorp uninitialized warning

The variables level and start_layer are not initialized, then
initialized if we have a BUFFER_BIT_DEPTH set.  We assert on them
later using the same check.  This should be enough but GCC 9.1.1 is
not convinced, so let's initialize the variables.

Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agotgsi: Remove unused local
Caio Marcelo de Oliveira Filho [Fri, 23 Aug 2019 15:22:02 +0000 (08:22 -0700)]
tgsi: Remove unused local

Code that used it was removed in 4ebe6b2e72e ("tgsi: Drop the SSE2
constants setup that's been dead code since 2011.")

Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agoiris: Guard GEN9-only function in Iris state to avoid warning
Caio Marcelo de Oliveira Filho [Fri, 23 Aug 2019 15:12:37 +0000 (08:12 -0700)]
iris: Guard GEN9-only function in Iris state to avoid warning

Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agointel/decoders: Avoid uninitialized variable warnings
Caio Marcelo de Oliveira Filho [Fri, 23 Aug 2019 14:59:21 +0000 (07:59 -0700)]
intel/decoders: Avoid uninitialized variable warnings

Initialize `next_batch_addr` and `second_level`.  If the batch is well
formed, those values will be overriden, if not, they are as good as
uninitialized garbage.

Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agocompiler/glsl: Fix warning about unused function
Caio Marcelo de Oliveira Filho [Fri, 23 Aug 2019 14:57:13 +0000 (07:57 -0700)]
compiler/glsl: Fix warning about unused function

The helper check_node_type() is only used when DEBUG is set (in the
function below), but ASSERTED macro uses NDEBUG.  So just guard the
helper with #ifdef.  If we see more such cases we might consider a
ASSERTED-like macro for the DEBUG case.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agoanv: Drop unused local variable
Caio Marcelo de Oliveira Filho [Thu, 22 Aug 2019 14:59:47 +0000 (07:59 -0700)]
anv: Drop unused local variable

Leftover from 021fa28163a ("xintel/nir: Add a helper for getting
BRW_AOP from an intrinsic").

Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agointel/compiler: Silence maybe-uninitialized warning in GCC 9.1.1
Caio Marcelo de Oliveira Filho [Fri, 23 Aug 2019 14:41:18 +0000 (07:41 -0700)]
intel/compiler: Silence maybe-uninitialized warning in GCC 9.1.1

Compiler can't see that d is initialized.

    ../src/intel/compiler/brw_vec4_nir.cpp: In function ‘int brw::try_immediate_source(const nir_alu_instr*, brw::src_reg*, bool, const gen_device_info*)’:
    ../src/intel/compiler/brw_vec4_nir.cpp:984:12: warning: ‘d’ may be used uninitialized in this function [-Wmaybe-uninitialized]
      984 |          d = MAX2(-d, d);

Assert that we expect at least one component -- hence d going to be
set.  That by itself is not enough, so also zero initialize the
variable.

Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
5 years agoradv: additional query fixes
Andres Rodriguez [Wed, 14 Aug 2019 03:52:23 +0000 (23:52 -0400)]
radv: additional query fixes

Make sure we read the updated data from the gpu in cases where WAIT_BIT
is not set.

Cc: 19.1 19.2 <mesa-stable@lists.freedesktop.org
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
5 years agoiris: Fix large timeout handling in rel2abs()
Kenneth Graunke [Thu, 22 Aug 2019 23:08:16 +0000 (16:08 -0700)]
iris: Fix large timeout handling in rel2abs()

...by copying the implementation of anv_get_absolute_timeout().

Appears to fix a CTS test with 32-bit builds:
GTF-GL46.gtf32.GL3Tests.sync.sync_functionality_clientwaitsync_flush

Fixes: f459c56be6b ("iris: Add fence support using drm_syncobj")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
5 years agoiris: Set MOCS in all STATE_BASE_ADDRESS commands
Kenneth Graunke [Thu, 22 Aug 2019 23:52:52 +0000 (16:52 -0700)]
iris: Set MOCS in all STATE_BASE_ADDRESS commands

Rafael Antognolli tracked down a performance gap between i965 and iris
in Synmark2's OglCSDof microbenchmark, noting that iris was performing
substantially more memory reads and writes, with substantially fewer
L3 hits.  He suggested that something might be wrong with MOCS, or L3
configs, at which point I came up with a theory...

It would appear that the STATE_BASE_ADDRESS command updates the MOCS
settings for various base addresses even if you don't specify the
"Modify Enable" bit for that address.  Until now, we had been setting
only the MOCS for bases we intended to change, leaving the others
"blank" which is MOCS table entry 0, which is uncached.

Most data access has a more specific MOCS (e.g. in SURFACE_STATE),
but scratch access uses the Stateless Data Port Access MOCS from
STATE_BASE_ADDRESS.  So this meant all scratch access was uncached.

Improves performance in Synmark2's OglCSDof by 2x, bringing iris
on par with the existing i965 driver.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
5 years agoglx: Fix up glXQueryGLXPbufferSGIX on macOS.
Vinson Lee [Fri, 23 Aug 2019 05:26:26 +0000 (22:26 -0700)]
glx: Fix up glXQueryGLXPbufferSGIX on macOS.

Fix this build error on macOS.

../src/glx/apple/glx_empty.c:158:4: error: void function 'glXQueryGLXPbufferSGIX' should not return a value [-Wreturn-type]
   return 0;
   ^      ~

Fixes: 3dd299c3d5b8 ("glx: Sync <GL/glxext.h> with Khronos")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Adam Jackson <ajax@redhat.com>
5 years agodocs: update calendar, add news item and link release notes for 19.1.5
Juan A. Suarez Romero [Fri, 23 Aug 2019 10:40:40 +0000 (12:40 +0200)]
docs: update calendar, add news item and link release notes for 19.1.5

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
5 years agodocs: add sha256 checksums for 19.1.5
Juan A. Suarez Romero [Fri, 23 Aug 2019 10:38:02 +0000 (12:38 +0200)]
docs: add sha256 checksums for 19.1.5

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit ae2a676cd1748c850f579863003c92f2b137f44a)