mem-cache: prevent prefetcher from saturating the write buffer

When the write buffer is full, it still has space to store an additional
number of entries (reserve) equal to the number of MSHRs so that if any
of them requires a writeback this can be handled. Even if the slave port
is blocked, a prefetcher can generate new MSHR entries that may lead to
additional writebacks and eventually saturate the reserve space. This is
solved by checking if the cache is blocked for accesses before
prefetching data.

Change-Id: Iaad04dd6786a09eab7afae4a53d1b1299c341f33
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29615
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: Replace include of eventq_impl.hh with eventq.hh.

eventq_impl.hh has been merged back into eventq.hh, but that change
passed another change which started using eventq_impl.hh in systemc.

Change-Id: I2e9be5f993fe6a6712a121cd955b0c56a33c87e3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30014
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim,mem,dev: Merge eventq_impl.hh into eventq.hh.

Having some methods (which are supposed to be inline) defined in another
file which is only included sometimes creates a lot of opportunities for
errors. They no longer need to be separate, so merge them together.

Change-Id: I5846e55f53f59b9c2081680a6441659265a765f7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29409
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base,sim: Move DTRACE into base/debug.hh.

All other considerations aside, DTRACE probably fits best in trace.hh
where it is now, but unfortunately that creates an awkward dependence
between that file and eventq.hh and eventq_impl.hh. DTRACE only depends
on flags in the Debug namespace and a universal macro TRACING_ON, so
even though it won't be alongside the things it's most logically
associated with, it will be alongside all of its dependencies.

An alternative would be to re-implement DTRACE in eventq_impl.hh which
wouldn't be too big of a problem because it's so simple, but it's
cleaner and less error prone to still keep a single definition.

Because base/trace.hh includes base/debug.hh, any consumers expecting to
find DTRACE in base/trace.hh will still get that definition, even though
it's no longer direct.

Change-Id: I0dac83295891630686c3a8038eb54138cf40ab44
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29411
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

misc: Make many includes explicit.

A future change will adjust how some includes can be included
transitively. This change fixes up those files so that they include the
headers they need directly, instead of expecting to have them by
accident through other files.

Change-Id: I1f79aa11df2b46bb7018f39c964294c41db4fdac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29407
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-o3: fix IQ missing mem barriers

After commit e2a5063e5f18f902833c84894b0ff103e3371493 some
memory references now tracked as barriers were not having
their completion properly notified to the MemDepUnit.

This patch fixes InstructionQueue and changes MemDepUnit's
completeBarrier to completeInst, which now should be called
for both memory references and barrier instructions.

Change-Id: I28b5f112b45778f6272e71bb3766b364c3d2e7db
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29654
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Merge branch version update into develop

misc: Updated release notes and version to v20.0.0.1

misc: Merge in 'hotfix-m5-tick-rounding-error'

python: Fix m5's tick rounding mechanism

Partially reverts:
https://gem5-review.googlesource.com/c/public/gem5/+/29372 where the
`math.ceil` function was used to fix an issue where 0.5 was rounded to
zero in python3. This has the side effect of giving incorrect clock
frequences due to rounding errors. To demonstrate:

```
>>> import math
>>> 1e-9*1000000000000
1000.0000000000001
>>> int(math.ceil(1e-9*1000000000000))
1001
```

The solution to this problem is to use Python's `decimal` module to
round values.

Issue-on: https://gem5.atlassian.net/browse/GEM5-616
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: Ic76736ccb4b6b8c037103a34493aff7d9731d314
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29577
Reviewed-by: Tiago Mück <tiago.muck@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Fix for Invalid transition in MOESI_CMP_directory

Send the correct sharer count from the memory directory to the requesting
L2 cache in data message reply.

Jira issue: https://gem5.atlassian.net/browse/GEM5-613

Change-Id: If76de630fd0001816e8836d9bf77961a94faaa7c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29552
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Reviewed-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Generate address with masking cacheline bits

makeLineAddress function uses m_block_size_bits to create
masked addresses. m_block_size_bits is used to specify
cache, directory, and memory controller interleaving,
and it can be larger than the cache line size.
To generate addresses that can align with the cache line
rather than the interleaving granularity, a version of
makeLineAddress is created to specify bits that need to
be masked.

Change-Id: I06deec4949da7fa46f1d6f7575334f18ee61c786
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28135
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Onur Kayıran <onur.kayiran@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

configs: Specify cache, dir, and mem cntrl interleaving

This changeset allows setting a variable for interleaving.
That value is used together with the number of directories to
calculate numa_high_bit, which is in turn used to set up
cache, directory, and memory controller interleaving.
A similar approach is used to set xor_low_bit, and calculate
xor_high_bit for address hashing.

Change-Id: Ia342c77c59ca2e3438db218b5c399c3373618320
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28134
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: add function to check for stalled msgs of addr

This patch allows a cache controller to check if there
is any stalled message of a specific address in the
stall_map of an input message buffer.

Change-Id: Id2f9bb98a9201a562f2a8cc371e9bb896ac836af
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28133
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: add slicc stm to defer enqueueing a message

This patch enables cache controllers to make response
messages in advance, store them in a per-address saved
map in an output message buffer and enqueue them altogether
in the future. This patch introduces new slicc statement
called defer_enqueueing. This patch would help simplify
the logic of state machines that deal with coalesing
multiple requests from different requestors.

Change-Id: I566d4004498b367764238bb251260483c5a1a5e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28132
Reviewed-by: Tuan Ta <qtt2@cornell.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

Merge branch 'release-staging-v20.0.0.0' into develop

system: Remove CNTFRQ_EL0 write from arm64 boot

We don't need this anymore since this is initialized at gem5
construction.

JIRA: https://gem5.atlassian.net/browse/GEM5-611

Change-Id: I42a3d53a4defba498a23d9a7c192dfff5852c1c7
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29613
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: Bobby R. Bruce <bbruce@ucdavis.edu>

dev-arm: Make CNTFRQ a GenericTimer parameter

This register should be in theory initialized by the highest
priviledged software. We do this in gem5 to avoid KVM
complications (the gem5 firmware won't run at highest EL)

JIRA: https://gem5.atlassian.net/browse/GEM5-611

Change-Id: I62d368105af48584f2fe9671de7c70b484b40c12
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29612
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: Bobby R. Bruce <bbruce@ucdavis.edu>

misc: Merge branch 'release-staging-v20.0.0.0' into develop

misc: Update release notes

Change-Id: I3851a3780aae283d4dba5ab5afa20a4a02bc8e6d
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29067
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Fixed null-pointer arithmetic error

Doing arithmetic on a null pointer is undefined behavior in C/C++. Clang
compilers complain when this occurs. As this MACRO is used twice, and
does nothing important, it has been removed in favor of a more simple
solution. A comment has been added explaining the MACRO's removal.

Change-Id: I42d9356179ee0fa5cb20f827af34bb11780ad1a9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29534
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

gpu-compute,misc: Removed unused 'vaddr' capture

Clang compilers return a `error: lambda capture 'vaddr' is not used`
error when compiling HSAIL_X86/gem5.opt. This unused lambda capture has
therefore been removed.

Change-Id: I2a7c58174a9ef83435099ab4daf84c762f017dd4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29533
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

mem-ruby,misc: Fixed clang template def error

Without this fix `error: call to function 'operator<<' that is neither
visible in the template definition nor found by argument-dependent
loopup` is thrown  when compiling HSAIL_X86 using a clang compiler (at
`base/cprintf_formats.hhi:139`).

This error is due to a "<<" operator in a template declared prior to its
definition in the code. The operator is used in
`base/cprintf_formats.hh`, included in `base/cprintf.hh`, and defined in
`mem/ruby/common/BoolVec.hh`. Therefore, for clang to compile without
error, `mem/ruby/common/BoolVec.hh` must be included before
`base/cprintf.hh` when generating the
`mem/ruby/protocol/RegionBuffer_Controller.cc` in
`mem/slicc/symbols/StateMachine.py`.

Due to the gem5 style-checker, an overly-verbose solution was required
to permit this patch to be committed to the codebase.

Change-Id: Ie0ae4053e4adc8c4e918e4a714035637925ca104
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29532
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

python,test: Fixed boot test in python3 by removing map

In Python3 `map(lambda c: c.createThreads(), self.cpu)` does not
execute `c.createThreads()`. This has been replaced with a for-loop
which does work. Without this fix, the boot tests do not run in python3.

Change-Id: I50d6c85ec4435ee04e248ea8bc4a3b4cc17c88fa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29456
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

scons: "no-defautled-function-deleted" flag moved to only clang8+

It has been onserved that clang does not function with the
"-Wno-defaulted-function-deleted" for versions below clang8.

Change-Id: I6e6d1476350ae2b46b4de971fe3456697b39e43c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29454
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm,misc: Add M5_CLASS_VAR_USED to faultTick

Clang compilers returned an error that faultTick was unused. Adding
M5_CLASS_VAR_USED resolves this.

Change-Id: I97657b45997d2f1c7416b973cd9c02ae2d92b725
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29453
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby,mem-garnet: Multiple networks per RubySystem

Add support for multiple networks per RubySystem. This is done by
introducing local IDs to each network and translating from a global ID
passed around through Ruby and SLICC code. The local IDs represents the
NodeID of a MachineType in the network and are ordered the same way
that NodeIDs are ordered using MachineType_base_number. If there are
not multiple networks in a RubySystem the local and global IDs are the
same value.

This is useful in cases where multiple isolated networks are needed to
support devices with Ruby caches which do not interact with other
networks. For example, a dGPU device will have a cache hierarchy that
will not interact with the CPU cache hierachy.

Change-Id: I33a917b3a394eec84b16fbf001c3c2c44c047f66
JIRA: https://gem5.atlassian.net/browse/GEM5-445
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27927
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Fix util/gem5img.py for new versions of sfdisk

Newer versions of sfdisk have changed the format of the dump output,
as well as the options for partitioning a disk.

Updated the gem5img.py script to work with the new version of sfdisk.
The script should still work with older versions of sfdisk, but this
has not been tested (see https://askubuntu.com/a/819614).

Tested on Ubuntu 18.04.2 LTS with sfdisk from util-linux 2.31.1.

Change-Id: I1197ecacabdd7caaab00327977fb9ab6eae06654
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29472
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv,misc: Added M5_VAR_USED to MiscRegNames

Clang compilers return an error about MiscRegNames being unused.
M5_VAR_USED fixes this.

Change-Id: I515c5d1e8837020b674de49039c0525f896b7e37
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29452
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons,python: Update makeTheGPUISA to Python3

This function was causing an error to occur when trying to compile HSAIL
and GCN in a Python3 environment. It has now been upgraded to work in
both Python2 and Python3.

Change-Id: If8d6ee1e08c47d5a36182afc10cf86a8e905bda0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29410
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: Disable some warnings generating false positives.

These false positives break the build. The error is below, and is bogus
as best I can tell. The constructor for the sc_unsigned and sc_signed
types, defined with some macro goop in sc_nbcommon.inc, have a call to
vec_copy_and_zero to copy over some data and zero the data that isn't
copied. That only happens if the source is smaller than the destination.
Then in vec_copy_and_zero, it calls vec_zero to set the last elements to
zero. Because of the check back at the constructor, only values that
exist should ever be set.

Also, in gem5, SC_MAX_NBITS is not set, so the definition of the array
it's bounds checking is declared right near where it's used and is sized
based on the variable being passed into vec_copy_and_zero.

In file included from build/ARM/systemc/ext/dt/bit/../int/../fx/sc_fxdefs.hh:52,
                 from build/ARM/systemc/ext/dt/bit/../int/sc_length_param.hh:63,
                 from build/ARM/systemc/ext/dt/bit/sc_bv_base.hh:56,
                 from build/ARM/systemc/dt/int/sc_unsigned.cc:83:
In function 'void sc_dt::vec_zero(int, int, sc_dt::sc_digit*)',
    inlined from 'void sc_dt::vec_copy_and_zero(int, sc_dt::sc_digit*, int, const sc_digit*)' at build/ARM/systemc/ext/dt/bit/../int/../fx/../int/sc_nbutils.hh:407:13,
    inlined from 'sc_dt::sc_unsigned::sc_unsigned(sc_dt::small_type, int, int, sc_dt::sc_digit*, bool)' at build/ARM/systemc/dt/int/sc_nbcommon.inc:2285:26:
build/ARM/systemc/ext/dt/bit/../int/../fx/../int/sc_nbutils.hh:379:14: error: 'void* __builtin_memset(void*, int, long unsigned int)' offset [12, 15] is out of the bounds [0, 12] [-Werror=array-bounds]
  379 |         u[i] = 0;
      |

Change-Id: Ica721178b24de56dbeabf4af7d3422dea6336a23
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29432
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Fix a possible memory error in copyOutStatfsBuf.

When memcpy-ing, we need to be sure not to read beyond the end of the
source, or write beyond the end of the target.

Change-Id: I3cf259bedce4c6e88aef47ef5379aab198338cb7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29404
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: Include eventq_impl.hh in scheduler.hh.

This ensures that we also get the inline definitions of some of the
methods defined in the EventQueue class. In certain circumstances gem5
won't link properly otherwise.

Change-Id: Ie0dfef207a165095bdfe1199cd1f690cebc4cbbf
Issue-on: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-597
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29397
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Disable some warnings in clang.

The defaulted-function-deleted warning triggers in generated code which
would be very tricky to address.

The c99-designator refers to using an array index to specify which
element of an array is being initialized. This makes the code more
clear and is supported by both g++ and clang++. Designated initializers
for structures are being introduced in C++20, but there is no word I
could find on arrays. This warning option seems to only exist in clang
versions 10 and up, so we can only use it on those versions.

Change-Id: I8fb858e643814638c552a49336db2672be8e43c8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29396
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

Revert "systemc: Fix clang9 linker error"

This reverts commit 80a263698323852b1951d8d71ca0d599dff7ef3c.

Change-Id: I24c69d1a5a54ac8b8d5713314f6e91e5a6263c26
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29395
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Fix the Ticked class constructor's event wrapper.

This uses a "name()" method which is not defined by the Ticked class,
and isn't a global method. This was probably originally supposed to be
the name() method of the Serializable class that Ticked inherits from,
but a while ago that was removed. It's not clear how this has been
compiling.

Instead, use the name() method of the ClockedObject which is the first
constructor argument.

Change-Id: Icfb71732c58ea9984ef7343bbaa46097a25abf28
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29406
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Fix a = that was supposed to be a == in an assert.

The KVM CPU has a _status field which is checked by an assert, but
rather than checking it with an ==, it accidentally used a =.

Change-Id: Ic1970d232786af6666c4ec2719c70f3f1509277c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29405
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim,dev: Get rid of the global retryTime constant.

This constant isn't in normalized units, ie doesn't scale when the time
value of a Tick changes, is global, has an extremely generic name even
though it's only used by a few ethernet devices, and has an arbitrary
value.

Get rid of it, and replace it with 1ns, what it would typically be
equivalent to when using the default 1ps time scale.

Change-Id: I31d9dad438f854b4152cd53c9a7042a25d13e0a6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29398
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests,python: Upgrading testlib to function with Python2

Change-Id: I9926b1507e9069ae8564c31bdd377b2b916462a2
Issue-on: https://gem5.atlassian.net/browse/GEM5-395
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29088
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Remove the ancient do_quiesce config option.

This option has existed for a very long time, defaults to True, and is
not used in any of the checked in configs. It enables the "quiesce"
mechanism, originally just pseudo instructions, and it's not clear
why you'd ever want to turn it off.

Change-Id: I92c7e5af22157e8435c7326634857d30bb5d7254
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25143
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: Fix clang9 linker error

Likely a compiler bug, but if this function is allowed to be inlined,
clang9 throws a linker error. Fix this error by making sure the function
isn't inlined.

Change-Id: I4bfade889796915e7bb4b224eafa6e72d4ec59da
Issue-on: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-597
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29394
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fixed spacing issue in ARM_MOESI_hammer

Change-Id: I5e38d1fb0b3c61ae40d26db21b8d20cc3199b391
Jira: https://gem5.atlassian.net/browse/GEM5-594
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29393
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fixed issue building ARM_MESI_Three_Level

Change-Id: I1ef200cd282e189d142a5902b6ddbd33119c4173
Jira: https://gem5.atlassian.net/browse/GEM5-594
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29352
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

misc: Remove GCN3 as a build target

This target currently doesn't compile, so remove it from the list of
supported ISAs for the gem5-20 release. We can add this target back
after the compilation errors have been fixed.

Change-Id: I2b121824fcfee59b62d7d24600ddd0eece884c6b
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29392
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Fixed HSAIL_X86 compilation errors

HSAIL_X86 fail to compile. This patch enables compilation.

Issue-on: https://gem5.atlassian.net/browse/GEM5-556

Change-Id: I663e529622ed90254eaf8be01e23991ed8271b5b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29293
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Update memory tests to be compatible with python3

Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I9bb7444c62e6b29e9c91dbf30320a38718f08b8c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29353
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Change m5's tick mechanism of rounding non intergral ticks

This commit changes m5's tick rounding mechanism from python's round()
to python's ceil() function.

Currently, non intergral ticks are rounded by round() function in python.
In python2, this function rounds values >= 0.5 to 1. However, in python3,
0.5 is rounded to 0. This causes the function to return 0 ticks for
non-zero second values, which doesn't make sense, and also causes
several tests to fail.

ceil() function is now used to round up the tick values. This makes more
sense as non-zero second values won't be rounded to zero in any cases.

Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: I14c43e38e8c678f77baf13407f7eeff4b86f1014
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29372
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-garnet: Remove extraneous loop in Router resetStats.

This outer loop makes no sense.

Change-Id: Ibe4b8b50c5843fba2119906f59ea1cb6c1d8c762
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29254
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-garnet,mem-ruby: Properly reset garnet2.0 statistics.

Statistics for crossbar activity, and link related statistics were not getting reset when using m5_reset_stats.

Change-Id: Ib84c55200e4a86c6f9190de28498112bd43dde9d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29253
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add dockerfile for GCN3 w/machine learning

This dockerfile creates an image that installs the software stack needed
to run both machine learning and non-machine learning applications using
the GCN3 gpu model, while also applying patches to the software stack to
optimize machine learning applications, as well as APUs, which is the
current type of GPU in the GCN3 GPU model.

Change-Id: If36c2df1c00c895e27e9d741027fd10c17bf224e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29192
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: add ruby_mem_test.py to the tests

This catches ruby functional memory errors we have observed, and ensures
that ruby_mem_test.py itself won't be broken.

The test duration is about 10 seconds, and it can be run as:

./main.py run --uid SuiteUID:tests/gem5/test_ruby_mem_test.py:test-ruby\
_mem_test-NULL-x86_64-opt

Change-Id: I39bc559aaea3ebb41217a96cd4e8dae46271ea1f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26805
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Make DOT config generation optional

By default, DOT configs are always generated when pydot is present.
This change allows a user to pass an empty --dot-config='' to disable
generating the DOT configuration. This can be useful to save space, or
to reduce Gem5 startup time when running many small regression tests.

This brings the behavior in-line with providing an empty
--dump_config='' and/or --json_config='' which similarly disables
generation of those output files.

Change-Id: I5bf39fda0409b948a8d14f3afa95db8fc78de6ee
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29232
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-se: ignore all scheduler related syscalls for arm

With the simplistic syscall emulation fork algorithm that we currently have
of running one thread per call, those calls simply cannot be reasonably
implemented.

However, content can often still work without them.

Change-Id: Iac88dfd055564c47b7a7b6898b7582cf4087f708
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28591
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

sim-se: implement the getcpu syscall

Change-Id: I63a1384646829b8cf68453c42aed6a7d12172787
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28590
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Add some methods to create derived symbol tables.

These tables are based on passing the symbols in the current table
through some sort of operator function which can chose to add those
symbols, modified versions of those symbols, or nothing at all into a
new symbol table.

The new table is returned as a shared_ptr so its memory will be
managed automatically.

Change-Id: I8809336e2fc2fda63b16a0400536116ca852ca13
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24786
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Added M5_CLASS_VAR_USED to m_id in OutputUnit

Clang 9 throws an error that 'm_id' is unused (encountered when
compiling X86.fast). M5_CLASS_VAR_USED has been added to avoid this
error.

Change-Id: I722edd1429a074ff484b5ebbdc431af0089561b5
Issue-on: https://gem5.atlassian.net/browse/GEM5-560
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29304
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,base,cpu,sim: Statically allocate debugSymbolTable.

This singleton object is used thruoughout the simulator. There is
really no reason not to have it statically allocated, except that
whether it was allocated seems to sometimes be used as a signal that
something already put symbols in it, specifically in SE mode.

To keep that functionality for the moment, this change adds an "empty"
method to the SymbolTable class to make it easy to check if the symbol
table is empty, or if someone already populated it.

Change-Id: Ia93510082d3f9809fc504bc5803254d8c308d572
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24785
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,base,cpu,kern,sim: Encapsulate symbols in a class.

The SymbolTable class had been tracking symbols as two independent
pieces, a name and an address, and acted as a way to translate between
them. Symbols can be more complex than that, and so this change
encapsulates the information associated with a symbol in a new class.

As a step towards simplifying the API for reading symbols from a
binary, this change also adds a "binding" field to that class so that
global, local and weak symbols can all go in the same table and be
differentiated later as needed. That should unify the current API
which has a method for each symbol type.

While the innards of SymbolTable were being reworked, this change
also makes that class more STL like by adding iterators, and begin
and end methods. These iterate over a new vector which holds all the
symbols. The address and name keyed maps now hold indexes into that
vector instead of the other half of the symbol.

Change-Id: I8084f86fd737f697ec041bac86a635a315fd1194
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24784
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc,sim: Tagged API methods in sim/simobject.hh

Change-Id: I1d4f5b67828e3bef64d781831cec4b25d6fcb6b9
Issue-on: https://gem5.atlassian.net/browse/GEM5-172
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28407
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

misc,base,stats: Tagged API methods in base/stats/group.hh

Change-Id: I61693884d719025f3b1f385793c7a71de0937e79
Issue-on: https://gem5.atlassian.net/browse/GEM5-172
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28390
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

misc: Added src/doxygen/html to .gitignore

Previously `src/doxygen` was ignored, but `src/doxygen` contains some
"source" for creating the doxygen html. Therefore this .gitignore entry
has been removed and replaced with one that only ignores the generated
`src/doxygen/html`.

Change-Id: I5add9fe839a00ad9d216d2082beda637ad0ea87d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28389
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

misc,sim: Tagged API methods and variables in eventq.hh

Change-Id: I76018d4aa08f9bd42a152ec7e0222a0385d3b895
Issue-on: https://gem5.atlassian.net/browse/GEM5-172
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28388
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

misc,sim: Tagged API methods in sim/serialize.hh

Within this some light refactoring has been carried out to avoid
accessing member variable directly and removing some unused/unneeded
ones from the codebase.

Change-Id: I458494f6466628b213816c81f6a8ce42fb91dc3f
Issue-on: https://gem5.atlassian.net/browse/GEM5-172
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27989
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Tagged API methods in sim/drain.hh

Change-Id: Id584d0be027048064d5f650ae0f2ea5a7f075a47
Issue-on: https://gem5.atlassian.net/browse/GEM5-172
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27988
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: fixed unused variable on fast binary

When gem5.fast is compiled, an error on a variable
used only for debug purposes is raised:

build/X86/cpu/o3/mem_dep_unit_impl.hh:262:19: error: unused variable 'producing_store' [-Werror=unused-variable]
         for (auto producing_store : producing_stores)

This patch remove the variable when *.fast is used.

Change-Id: Ib77c26073db39644e3525bc16edcb7d3bc871d76
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29252
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

scons: Revert LTO and partial linking for gcc >=8.1

This reverts commit f41abbdb5cf5c67233f3d730885d43517969afda,
"scons: Enable LTO and partial linking with gcc >= 8.1."

LTO and partial linking does not work on GCC 9.3 on Ubuntu 20.04 when
compiling gem5.fast. This error was exposed via the following command:

```
docker run -u $UID:$GID --volume $(pwd):/gem5 -w /gem5 --rm \
gcr.io/gem5-test/ubuntu-20.04_all-dependencies:latest scons \
build/MIPS/gem5.fast
```

The following error was received:

```
usr/bin/ld: cannot find lib.fo.partial.lto.o: No such file or directory
/usr/bin/ld: error: could not unlink output file
collect2: error: ld returned 1 exit status
scons: *** [build/MIPS/mem/ruby/system/lib.fo.partial] Error 1
```

Issue-on: https://gem5.atlassian.net/browse/GEM5-555
          https://gem5.atlassian.net/browse/GEM5-557
Change-Id: Id9e7fc81aec9f94524acc92c05aabdf96bd284cd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29272
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc,sim: Fixed std::array bracket compiler error

For versions of Clang before 6.0, Clang returns an error if and
std::array initialization is not encompassed in two sets of
encompassing braces. This is a known compiler bug:
https://bugs.llvm.org/show_bug.cgi?id=21629.

As we support Clang 3.9 onwards, we are required to include these
redundant braces to ensure compilation. They do not produce any
ill-effects when using later clang compilers or with any GCC compiler
gem5 presently supports.

Change-Id: Ia512a9b9f583b1cfa28f9fc4c24f6e202e46b4cb
Issue-on: https://gem5.atlassian.net/browse/GEM5-563
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29294
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-minor: fix store-release issuing

Store with release flag are treated like store conditionals and are not
bufferable. Also they are only sent when the store buffer is empty to
satisfy the release semantics.

Change-Id: I253ec5ecd39901b14d0dc8efbc82cf7e4b07f08f
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27135
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>

cpu-o3: fix store-release issuing

Requests from stores with release semantics are only issued when they
are at the head of the store queue.

Change-Id: I19fbceb5ee057d3aa70175cbeec6b9b466334e8c
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27134
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>

arch-arm: Using acquire/release memory flags

Appends the acquire/release memory flags for the instructions with those
semantics.

Change-Id: I9d1e12c6ced511f2ff7a1006c27ae9014965e044
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27133
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>

configs: Updates for python3

Change-Id: Iab2f83716ea2cb19f06282f037314f2db843327a
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29047
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

util: Pull argument parsing functions out of m5.c.

Make them available in other files as well.

Change-Id: I3ddaed1a06023f929acc95c90f8f9adda7ff429c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27243
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>

misc: Update Garnet_standalone build opts

Previously, this used the ALPHA ISA which has been removed.

According to the documentation on the website
(https://www.gem5.org/documentation/general_docs/ruby/
garnet_synthetic_traffic/), using null ISA with no CPUs should be safe.

Change-Id: I7fc55df7217887d21f4832f33b8cbb2de3498253
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29087
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Stop setting the physical address in finalizePhysical.

The physical address has already been set (it's read earlier in the
function), and so doesn't need to be set again. Reading the virtual
address can cause an assert if the virtual address had never been set in
the first place, for example when an access comes from KVM which might
give you an access to complete which is based on a physical address
only.

Change-Id: Ic46a40b1a94235538b5bd53065e5019273b3d3f3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29172
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Added 'python3-config' to the config list

Previously scons looked for 'python-config' and 'python2-config'. This
caused an error in Python3-exclusive environments. With only python3
installed, 'python3-config' is now an option. With this setup,
'python2-config' is used by default, unless overridden by the user
via the scons command line.

Change-Id: I11186328b0eb0825cc53c3889b31a5345a7f40d1
Issue-on: https://gem5.atlassian.net/browse/GEM5-275
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28648
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Update style file->open for python3

Change-Id: Ibcce194b1905f0e7f29aa91fd0ff881ba879ad51
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29068
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

misc: Add Arm contributions to gem5-20 RELEASE-NOTES.md

* Arm architectural extensions
* Arm TFA support
* DRAM changes

Change-Id: I434c501ee8413c8cd64af25c2c18eabf45e3ee77
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28908
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Set a physical address for local accesses.

This avoids problems when other parts of the simulator blindly try to
retrieve the physical address.

Change-Id: Ia13a2b85b9f919e1e81a6a0f67d10858e98244e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28987
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Fixes for mremap

Remapping memory was trying to map old pages to the same new page and
calling MemState mapRegion unnecessarily. Properly increment the new
page address and remove the redundant mapRegion as remapRegion covers
its functionality.

JIRA: https://gem5.atlassian.net/browse/GEM5-475
Change-Id: Ie360755cfe488b09cbd87cd0ce525b11ac446b51
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28948
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Get gem5 to build with Clang 8

Added missing overrides:
- src/mem/token_port.hh
- src/sim/power/mathexpr_powermodel.hh

Remove Unused static constants:
- src/arch/x86/process.cc

Related Issue: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-534

Change-Id: Icc725e2522dcee919e299f4ea7a9f1773f5dfa4d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28947
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Remove infinite queue between Ruby and memory

AbstractController sends requests using a QueuedMasterPort which has an
implicit buffer which is unbounded. Remove this by changing the port to
a MasterPort and implement a retry mechanism for AbstractController.
Although the request remains in the MessageBuffer if a retry is needed,
the additional retry logic optimizes serviceMemoryQueue slightly and
prevents the DRAMCtrl retry stats from being incorrect due to multiple
calls to sendTimingReq.

Change-Id: I8c592af92a1a499a418f34cfee16dd69d84803ad
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28387
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Added missing optional dependencies to 18.04 Docker

Change-Id: Ibc43664f99ce9fbd28d14352243fb17b7754289b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28892
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Added python-six as a dependency in 18.04 docker

Previously the docker utilized Python-Pip. This is an intermediate
dependency we don't need. We can install the Python-six module directly
via the APT framework.

Change-Id: I30e3e1cdca802ca19422140f39af7dc9dc166ed7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28891
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Removed python3 Dockerfile

This was previously used to test gem5 being compiled and run in a
Python3 environment. This is redundant with the introduction of
"util/dockerfiles/ubuntu-20.04_all-dependencies", which uses python3
exclusively.

Change-Id: Ie837da338c3985ba92aff84144948a23fd6ece3f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28890
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Added Dockerfile for Ubuntu 20.04

This Dockerfile creates an image which simulates an Ubuntu 20.04
environment. Unlike the Ubuntu 18.04 Dockerfile, this does not use
Python2. It uses exclusively Python3. Ubuntu 20.04 has Python3 installed
by default. The image this Dockerfile creates can be obtained from
"gcr.io/gem5-test/ubuntu-20.04_all-dependencies". To pull:

docker pull gcr.io/gem5-test/ubuntu-20.04_all-dependencies

Change-Id: I73b51028e0d6a3198aa6e7b1906d20ed6eb6c815
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28889
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm,x86,sim: Use the new return value suppression in GuestABI.

This gets rid of some dummy Return structure definitions. Also augment
the PseudoInst::pseudoInst dispatch function so it can store or not
store results, depending on what's needed at each call sight.

Change-Id: If4a53bc0a27e5214a26ef1a100c99948ca95418d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28289
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Convert GuestABI example signatures to comments.

In the base Result and Argument templates, there were private static
functions which weren't meant to be used, but which would act as
documentation for what those functions should look like. They were
marked as private to prevent them from being accidentally used and
causing confusing, hard to debug errors.

Unfortunately, that also meant that those functions exist, and
apparently cause inconsistent problems with SFINAE. I assume if the
functions don't exist at all, then SFINAE will work properly. When
they're private, that seems to cause a substitution failure which
actually is an error which makes the build fail.

Change-Id: I326e9e1d05eafe1b00732ae10264354b07426e74
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28308
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Update python-config flags for python3.8

Starting in python 3.8 the python3-config utility requires the --embed
flag to output -lpython3.8. Without this flag, gem5 won't link to the
python library.

More details: https://bugs.python.org/issue36721
https://github.com/python/cpython/pull/13500

Change-Id: Id9c63577dcd2defa7ae62cc32e042c4a245e7082
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28687
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Add readCommandWithReturn helper

In this way it will be possible to reliably catch any error
in the command execution which is not raising an exception
to Popen.

Change-Id: I4dc15648423f9bb8e8a470d97291dbd065c48eba
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28847
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv,tests: small update to make gem5.fast compile

This small change is meant to enable gem5.fast compilation
for riscv. Also, the riscv tests based on gem5.fast
work now and are removed from .testignore.

Change-Id: Id9c96d8e4682a74ec1d77a66eae53d6f9b64d302
Issue-On: https://gem5.atlassian.net/browse/GEM5-526
Issue-On: https://gem5.atlassian.net/browse/GEM5-527
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28893
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

gpu-compute,mem-ruby: Refactor GPU coalescer

Remove the read/write tables and coalescing table and introduce a two
levels of tables for uncoalesced and coalesced packets. Tokens are
granted to GPU instructions to place in uncoalesced table. If tokens
are available, the operation always succeeds such that the 'Aliased'
status is never returned. Coalesced accesses are placed in the
coalesced table while requests are outstanding. Requests to the same
address are added as targets to the table similar to how MSHRs
operate.

Change-Id: I44983610307b638a97472db3576d0a30df2de600
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27429
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Defer deletion of respQueue.front() in DRAMCtrl

The front() of respQueue was being deleted before the last usuage of
dram_pkt (which points to the same object) causing random crashes.

Change-Id: I89862d10599dc0d1a50717dac8ed9298b4d74a3d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28808
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Updated resources bucket url to version 20

This will fix this v20.0.0.0 of gem5 to the v20 gem5 resources bucket
subdirectory.

Change-Id: I0c1f1a2c28c18e684bcb009d1650f9e9d2950a93
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28708
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Updated version to 20.0.0.0

Change-Id: I5ba4a6e728b2daccea898685d3c27b0f7c7a02cd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28707
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: MESI_Two_Level missing function compilation fix

The recent commit dd6cd33 removed the Ruby Sequencer function
invalidateSC in favour of doing this implicitely via
evictionCallback. The protocol MESI_Two_Level still contains one
explicit call to this function, however, this is now superflous
as forward_eviction_to_cpu is called in the same transition. This
patch removes the remaining calls to invalidateSC.

JIRA: https://gem5.atlassian.net/browse/GEM5-499

Change-Id: If51d8bebf6aa39d20789639aab0d262d5173ca59
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28747
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: MOESI_CMP_directory sync fix

The recent commit dd6cd33 modified the behaviour of the the Ruby
sequencer to handle load linked requests as loads rather than
stores. This caused the regression test
realview-simple-timing-dual-ruby-ARM-x86_64-opt
to become stuck when booting Linux. This patch fixes the issue by
adding a missing forward_eviction_to_cpu action to the state
transition(OM, Fwd_GETX, IM).

Change-Id: I8f253c5709488b07ddc5143a15eda406e31f3cc6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28787
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: SVE instruction in EL1s cannot be trapped to EL2

haveVirtualization() is not a valid check on its own:
We need to check if EL2 trapping is currently supported and this
can only happen if we are in NS state or if SecEL2 is implemented

Change-Id: Ie2312caba1ac0f186a2a3305c55a23c7705ba3fd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28769
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: CPTR.FPEN controlling SVE enablement

CheckSveEnabled shouldn't check for .ZEN only.
SVE instructions require Advanced SIMD to be supported as
well (CPTR.FPEN) with the caveat of ZEN check having priority
over the FPEN.

Change-Id: Ia1b5f7df3e25e7ffcad472542cb973635f62637b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28768
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Remove checkSveTrap method

This is not part of the arm arm pseudocode and prevents a proper
fix of the checkSveEnabled

Change-Id: I075749095316e59e395d5b84a23db4309bdd7a92
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28767
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-o3: MemDepUnit tracks load-acquire/store-release

MemDepUnit tracks loads/stores that are also barriers, which is the case
of load-acquire / store-release instructions. The tracking logic is also
extended to consider multiple outstanding barriers.

Change-Id: I95b0c710d7c7e4a138492177e3eaaf5143e9a0ba
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27132
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>