i965: Make unsynchronized maps unsynchronized on non-LLC

On Broxton, the performance of Unigine Valley 1.0 is improved by
13.3067% +/- 0.144322% (n=40) at 1280x720/QUALITY_LOW, and by
1.68478% +/- 0.484226% (n=3) at 1920x1080/QUALITY_LOW.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Implement brw_bo_map_unsynchronized() with MAP_ASYNC

This way we can let brw_bo_map() choose the best mapping type.

Part of the patch inlines map_gtt() into brw_bo_map_gtt() (and removes
map_gtt()). brw_bo_map_gtt() just wrapped map_gtt() with locking and a
call to set_domain(). map_gtt() is called by brw_bo_map_unsynchronized()
to avoid the call to set_domain(). With the MAP_ASYNC flag, we now have
the same behavior previously provided by brw_bo_map_unsynchronized().

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Elide call to set_domain() if MAP_ASYNC

No functional change (no callers currently pass MAP_ASYNC)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Add and use brw_bo_map()

We can encapsulate the logic for choosing the mapping type. This will
also help when we add WC mappings.

A few functional changes are made in this patch. On non-LLC, what were
previously WB mappings are now GTT mappings (in the prefilling debug
code in brw_performance_query.c; the shader_time code in brw_program.c;
and in the case of an RW mapping in intel_buffer_objects.c).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Drop MAP_READ from some write-only mappings

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Pass flags to brw_bo_map_*

brw_bo_map_cpu() took a write_enable arg, but it wasn't always clear
whether we were also planning to read from the buffer. I kept everything
semantically identical by passing only MAP_READ or MAP_READ | MAP_WRITE
depending on the write_enable argument.

The other flags are not used yet, but MAP_ASYNC for instance, will be
used in a later patch to remove the need for a separate
brw_bo_map_unsynchronized() function.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Rename brw_bo_map() -> brw_bo_map_cpu()

I'm going to make a new function named brw_bo_map() in a later patch
that is responsible for choosing the mapping type, so this patch clears
the way.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Rename *_virtual -> map_*

I think these are better names, and it reduces the delta between
upstream and Chris Wilson's brw-batch branch.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Pass the map-mode along to intel_mipmap_tree_map_raw()

Since we can distinguish when mapping between READ and WRITE, we can
pass along the map mode to avoid stalls and flushes where possible.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Add a cache_coherent field to brw_bo

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Remove unused 'use_resource_streamer' field

Missing in the resource streamer removal of commit 951f56cd43bc.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Remove brw_bo's virtual member

Just return the map from brw_map_bo_*

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Remove unused brw_bo_map__* functions

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

anv: Set better descriptor set limits

Based on discussions with Jason, Ivy Bridge and Bay Trail only actually
support 16 samplers, while newer hardware can support more than the
current limit of 64. Therefore set the lower limit where needed, and
bump up to 128 for everything else. There is also a limit on the total
number of other resources of around 250.

This allows Dawn of War III to render correctly on ANV.

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv: Set driver version to Mesa version

As already done by RADV.

v2: Move version calculation function to src/vulkan/util to share with
    RADV.

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

radv/vulkan: Move radv_get_driver_version to src/vulkan/util

This means it can be reused for other Vulkan drivers. Also fix up a
typo, need to search for '.' in the version string rather than ','.

v2: Remove unneeded temporary version variable (Emil, Eric)

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

util/vulkan: Move Vulkan utilities to src/vulkan/util

We have Vulkan utilities in both src/util and src/vulkan/util. The
latter seems a more appropriate place for Vulkan-specific things, so
move them there.

v2: Android build system changes (from Tapani Pälli)

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>

intel: gen-decoder: rework how we handle groups

The current way of handling groups doesn't seem to be able to handle
MI_LOAD_REGISTER_* with more than one register. This change reworks
the way we handle groups by building a traversal list on loading the
GENXML files.

Let's say you have

Instruction {
  Field0
  Field1
  Field2
  Group0 (count=2) {
    Field0-0
    Field0-1
  }
  Group1 (count=4) {
    Field1-0
    Field1-1
  }
}

We build of linked on load that goes :

Instruction -> Group0 -> Group1

All of those are gen_group structures, making the traversal trivial.
We just need to iterate groups for the right number of timers (count
field in genxml).

The more fancy case is when you have only a single group of unknown
size (count=0). In that case we keep on reading that group for as long
as we're within the DWordLength of that instruction.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>

radeonsi: fix a GPU hang with tessellation on 2-CU configs

Only harvested Stoney has 2 CUs. Tested on 2-CU Stoney and Fiji forced
to 2 CUs.

Cc: 17.0 17.1 <mesa-stable@lists.freedesktop.org>
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>

mesa: make use of NewWindowRectangles driver flags

Now, st_update_window_rectangles() won't be called when the
scissor is going to be updated.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa: add new gl_driver_flags::NewWindowRectangles

This new driver flag will replace _NEW_SCISSOR which is
emitted when setting new window rectangles but it actually
triggers useless changes in the state tracker (like scissor
and rasterizer).

EXT_window_rectangles is currently only supported by Nouveau.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa: remove call to Driver.Scissor() in _mesa_WindowRectanglesEXT()

This is actually useless because this driver call is only used
by the classic DRI drivers which don't support that extension
and probably won't never support it.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa: only emit _NEW_MULTISAMPLE when min sample shading changes

We usually check that given parameters are different before
updating the state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa: only emit _NEW_MULTISAMPLE when sample mask changes

We usually check that given parameters are different before
updating the state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa: only emit _NEW_MULTISAMPLE when coverage parameters change

We usually check that given parameters are different before
updating the state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

i965: Change INTEL_DEBUG=vec4 to INTEL_SCALAR_VS for consistency.

We moved to INTEL_SCALAR_* when we added more than a single stage, but
never went back and converted the VS to work that way.  Be consistent.

Also update the documentation to actually mention these debug variables.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>

radv: expose integrated device type for APUs.

This just sets the vulkan device type depending on whether
this is an APU or GPU.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver"

ac/surface: Fix HTILE for radv.

We always compute HTILE size using addrlib, even when not TC compatible.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlied <airlied@redhat.com>

radv: fix write event eop on vega.

Typo here, fixes command submission hangs on vega

radv: enable GFX9 on radv

I'm open to reverting this closer to release if bad things
happen, but it might be easier to debugging to leave it for now.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: turn off geom/tess for gfx9.

We don't support these yet, and it'll take a bit of work to do so.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: misc GFX9 changes.

These are just some register changes ported from radeonsi for gfx9.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: add some GFX9 specific events.

These are ported from radeonsi, don't know all the rules for
when they should be inserted.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: add IA_MULTI_VGT_PARAM support for GFX9.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: add rb+ support for GFX9

This adds some rb+ support, as on GFX9 we have to disable
it as per radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: add GFX9 cache flushing support.

GFX9 needs to write event EOP to a fence buffer, allocate some
space for this, and just write an ever increasing number to it,
this isn't exactly what radeonsi does, but it seems to work.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: add texture descriptor/fmask/cmask support for GFX9

This adds gfx9 support for the texture descriptor along
with the fmask/cmask allocation routines.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: add GFX9 to initialisation cmd buffer.

This just adds support for initialising some GFX9 registers,
and handles the different init for the VGT reuse reg.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: don't setup raster_config on gfx9.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: add gfx9 cp dma support.

This adds support to the CP dma code for GFX9, ported from
radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: add gfx9 depth/stencil surface support.

This is ported from radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: add GFX9 support for color surfaces.

This is ported from radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: add some misc gfx9 pieces.

This just adds the strings and includes the gfx9 register defs
in some files that we need them in.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: set offchip hs param like radeonsi.

radeonsi never uses 512 here anymore.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: fix typo in comment.

radv: add a comment from radeonsi before cp dma function.

This is just copied over.

Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: remove doubled up prototype.

Must have snuck in during a rebase.

radv: split metadata struct into legacy/gfx9 parts.

This is just ported from radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: refactor some texture descriptor state.

This just splits out some non-gfx9 bits in advance to avoid
regressions.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: refactor color surface init before gfx9.

This just moves the code around in preparation for gfx9 support.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: refactor depth/stencil state setup

In advance of GFX9 to reduce chances for regression, refactor
this code out so adding the GFX9 changes will be more obvious.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: use radv_foreach_stage in a couple of places.

This just collapses a few per-stage things into a loop,
shouldn't affect anything.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radeon: remove out of date LLVM_REVISION.txt

The file was introduced to track which LLVM revision was required, yet
that has quickly gone out of shape.

It has seen no updates since 2013.

Cc: Nicolai Hähnle <nicolai.haehnle@amd.com>
Cc: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Aaron Watry <awatry@gmail.com>

docs: update calendar, add news item and link release notes for 17.1.2

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>

docs: add sha256 checksums for 17.1.2

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit 4908b1e909ba4cfd5391f61ea551d21cccb52e2f)

docs: add release notes for 17.1.2

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit 97f6404e50212fb65fe047e467f5497bcba5b8ac)

gallium/u_threaded: fixes for MSVC

Replace some static assertions with runtime assertions.  The static
asserts don't work/fail on MSVC, despite the offsets being multiples
of 16 (checked with softpipe).

Use correct parameter types for a few gallium context functions.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

r600: refactor out some compressed resource state code.

This just takes this out to a separate function as it will
get more complex with images.

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>

r600: document some of the missing shader constants.

These are used for fragment shader thread calculations.

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>

r600: add register info for atomic counters.

The atomic counters on evergreen are implemented via append/consume
UAV counters. This just adds the register info for them. The EOS
packets are used to get the atomic totals extracted post shader
execution for storing into a buffer.

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>

r600: add missing RAT registers and operations.

This just documents in the headers the RAT operation list,
and the RAT encoding for exports.

The immediate registers are used to point to buffers for the
RAT return values (_RTN instructions).

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>

r600/sb: fix typo in field definitions

Pointed out by glennk.

tgsi/scan: fix scanning fragment shaders with PrimID and Position/Face

Not relevant to radeonsi, because Position/Face are system values
with radeonsi, while this codepath is for drivers where Position and
Face are ordinary inputs.

Reviewed-by: Brian Paul <brianp@vmware.com>

i965: Finalize miptrees before prepare_texture

In order to do resolves for texture views with different formats, we
need intel_texture_object::_Format to be valid.  Calling
intel_finalize_mipmap_tree can safely be done multiple times in a row
and should be a fairly cheap operation.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

gallium/u_threaded: remove 16 bytes from tc_batch

All other sentinels occupy what is otherwise unused space.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

gallium/u_threaded: align batches and call slots to 16 bytes

not sure if this helps

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

st/mesa: don't load cached TGSI shaders on demand

This fixes a performance issue with the shader cache that delayed Gallium
shader create calls until draw calls.

I'd like this in stable, but it's not a showstopper.

Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

Android: use bionic pthread_barrier_* if possible

The pthread_barrier_* functions were introduced to bionic
since Nougat.

Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Emil Velikov <emil.velikov@collabora.com>

r600: fix incorrect and missing bit field in register headers.

The compression field was incorrect, and we were missing the
depth before shader field.

radv: use ac_compute_surface

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: prepare fmask surface creation

The old code copied over all the surface info from the image
surface, we only want some bits of it, and to modify the flags.

This prevents a regression in dEQP-VK.api.copy_and_blit.resolve_image.*
and others in the subsequent switch to ac_compute_surface.

v2:
- also disable opt4Space in radv_amdgpu_surface, so that we can
  apply this patch separately *before* switching to ac_compute_surface
  and hopefully avoid intermittent regressions (Nicolai)

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radv: use amdgpu_addr_create

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: stop using radv_amdgpu_winsys::family

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: use ac_gpu_info

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: remove radeon_info::name

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: use ac_surface data structures

This is mostly mechanical changes of renaming types and introducing
"legacy" everywhere.

It doesn't use the ac_surface computation functions yet.

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: rename radeon_surf::bo_{size,alignment} to surf_{size,alignment}

To match radeonsi / ac_surface.

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: remove unused RADEON_SURF_HAS_SBUFFER_MIPTREE

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: remove radeon_surf_level::nblk_z

We're not using thick tiling modes, so we can just derive the value
ourselves.

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: remove radeon_surf_level::dcc_enabled

Like radeonsi; replace with radeon_surf::num_dcc_levels.

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: remove radeon_surf_level::pitch_bytes

Like radeonsi. This saves memory, and the information can easily be
recomputed on the fly where necessary.

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: add surface helper variable in radv_GetImageSubresourceLayout

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: fewer than 8 RBs are possible

This fixes the subsequent assertion on Bonaire.

Reviewed-by: Dave Airlie <airlied@redhat.com>

ac/surface/gfx6: explicitly support S8 surfaces

This is needed by radv for dEQP-VK.renderpass.simple.stencil

Reviewed-by: Dave Airlie <airlied@redhat.com>

ac/nir: set workgroup size attribute to correct value.

This ports: 55445ff1891724c78e6573d2f8c721e14c0449fc from radeonsi

    radeonsi: tell LLVM not to remove s_barrier instructions

    LLVM 5.0 removes s_barrier instructions if the max-work-group-size
    attribute is not set. What a surprise.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

ac: add new helper function to add a integer target dependent function attr.

This is needed to add the max workgroup size attribute.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: add external memory support.

This adds support for exporting 2D images, to an
opaque fd.

This implements the:
VK_KHX_external_memory_capabilities
VK_KHX_external_memory
VK_KHX_external_memory_fd

extensions.

These are used by SteamVR, we should work with anv
to decide if we should ship these under an env
var or something.

v2 (Bas): - Don't expose the semaphore ext without implementing it.
          - Only export the capabilities ext as instance ext.
          - Implement radv_GetPhysicalDeviceExternalBufferPropertiesKHX.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>

radv: Add VkPhysicalDeviceIDProperties support.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Add support for external queue family.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv/formats: reverse how the image format properties KHR2 is handled

This just aligns with how anv does it.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: Dirty all descriptors sets when changing the pipeline.

Sets could have been ignored during previous descriptor set flush
due to the shader not using them and therefore no SGPR being assigned.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Fixes: ae61ddabe8c "radv: move userdata sgpr ownership to compiler side."

radv: Set both compute and graphics SGPRS on descriptor set flush.

We clear the descriptors_dirty array afterwards, so the SGPRs for
the other pipeline don't get updated on the flush for that other
draw/dispatch, so we have to make sure we do it immediately.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Fixes: ae61ddabe8c "radv: move userdata sgpr ownership to compiler side."

i965: Order write of query availablity with earlier writes

Currently we signal the availabilty of the query result using an
unordered pipe-control write. As it is unordered, it may be executed
before the write of the query result itself - and so an observer may
read the query result too early. Fix this by requesting that the write
of the availablity flag is ordered after earlier pipe control writes.

Testcase: piglit/arb_query_buffer_object-qbo/*async*
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

nvc0: Add support for ARB_post_depth_coverage

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

st/mesa: Add support for ARB_post_depth_coverage

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

gallium: Add a cap to check if the driver supports ARB_post_depth_coverage

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

gallium: Add TGSI shader token for ARB_post_depth_coverage

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: disable BGRA8 images on Fermi

BGRA8 image stores on Fermi don't work, which results in breaking
PBO downloads, such that they always return 0x0. Discovered this
through a glamor bug, and confirmed it does indeed break a good number
of piglit tests such as spec/arb_pixel_buffer_object/pbo-read-argb8888

Fixes: 8e7893eb53213 ("nvc0: add support for BGRA8 images")
Signed-off-by: Lyude <lyude@redhat.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org

i965: Simplify l3 way size computations

By making use of l3_banks field in gen_device_info struct
l3_way_size for gen7+ = 2 * l3_banks.

V2: Keep the get_l3_way_size() function.

Suggested-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965: Add and initialize l3_banks field for gen7+

This new field helps simplify l3 way size computations
in next patch.

V2: Initialize the l3_banks to 0 in macros.

Suggested-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>